Ðþí  M«   H  Gü   (            ¯  G´                                                                     2   Enclustra Mercury+ SA2 on Mercury+ ST1 Base Board         S   !enclustra,mercury-sa2-st1 enclustra,mercury-sa2 altr,socfpga-cyclone5 altr,socfpga     aliases          ,/soc/serial@ffc02000             4/soc/serial@ffc03000             </soc/timer0@ffc08000             C/soc/timer1@ffc09000             J/soc/timer2@ffd00000             Q/soc/timer3@ffd01000             X/soc/ethernet@ff702000        cpus                                       baltr,socfpga-smp       cpu@0            !arm,cortex-a9            pcpu          |             €            ‘         cpu@1            !arm,cortex-a9            pcpu          |            €            ‘            pmu@ff111000             !arm,cortex-a9-pmu            ™            ª       °          ±            µ               |ÿ    ÿ0          interrupt-controller@fffed000            !arm,cortex-a9-gic            È             Ù         |ÿþÐ    ÿþÁ             ‘         soc                                   !simple-bus           psoc          ™             î   amba             !simple-bus                                     î   pdma@ffe01000            !arm,pl330 arm,primecell          |ÿà          `   ª       h          i          j          k          l          m          n          o            õ                     	  apb_pclk                  <        dma          ‘   4         base_fpga_region             !fpga-region         &                                  can@ffc00000             !bosch,d_can          |ÿÀ           0   ª       ƒ          „          …          †                             7      	  /disabled          can@ffc01000             !bosch,d_can          |ÿÀ          0   ª       ‡          ˆ          ‰          Š               	              8      	  /disabled          clkmgr@ffd04000          !altr,clk-mgr             |ÿÐ@       clocks                               osc1            6             !fixed-clock         Cúð€         ‘   
      osc2            6             !fixed-clock          ‘         f2s_periph_ref_clk          6             !fixed-clock          ‘         f2s_sdram_ref_clk           6             !fixed-clock          ‘         main_pll@40                                   6             !altr,socfpga-pll-clock              
         |   @         ‘      mpuclk@48           6             !altr,socfpga-perip-clk                      S   à       	         |   H         ‘         mainclk@4c          6             !altr,socfpga-perip-clk                      S   ä       	         |   L         ‘         dbg_base_clk@50         6             !altr,socfpga-perip-clk                 
        S   è       	         |   P         ‘         main_qspi_clk@54            6             !altr,socfpga-perip-clk                       |   T         ‘         main_nand_sdmmc_clk@58          6             !altr,socfpga-perip-clk                       |   X         ‘         cfg_h2f_usr0_clk@5c         6             !altr,socfpga-perip-clk                       |   \         ‘            periph_pll@80                                     6             !altr,socfpga-pll-clock              
               |   €         ‘      emac0_clk@88            6             !altr,socfpga-perip-clk                       |   ˆ         ‘         emac1_clk@8c            6             !altr,socfpga-perip-clk                       |   Œ         ‘         per_qsi_clk@90          6             !altr,socfpga-perip-clk                       |            ‘          per_nand_mmc_clk@94         6             !altr,socfpga-perip-clk                       |   ”         ‘         per_base_clk@98         6             !altr,socfpga-perip-clk                       |   ˜         ‘         h2f_usr1_clk@9c         6             !altr,socfpga-perip-clk                       |   œ         ‘            sdram_pll@c0                                      6             !altr,socfpga-pll-clock              
               |   À         ‘      ddr_dqs_clk@c8          6             !altr,socfpga-perip-clk                       |   È         ‘   !      ddr_2x_dqs_clk@cc           6             !altr,socfpga-perip-clk                       |   Ì         ‘   "      ddr_dq_clk@d0           6             !altr,socfpga-perip-clk                       |   Ð         ‘   #      h2f_usr2_clk@d4         6             !altr,socfpga-perip-clk                       |   Ô         ‘   $         mpu_periph_clk          6             !altr,socfpga-perip-clk                      [            ‘   3      mpu_l2_ram_clk          6             !altr,socfpga-perip-clk                      [         l4_main_clk         6             !altr,socfpga-gate-clk                       i   `             ‘         l3_main_clk         6             !altr,socfpga-perip-clk                      [         l3_mp_clk           6             !altr,socfpga-gate-clk                       S   d               i   `            ‘         l3_sp_clk           6             !altr,socfpga-gate-clk                       S   d            l4_mp_clk           6             !altr,socfpga-gate-clk                          S   d              i   `            ‘   *      l4_sp_clk           6             !altr,socfpga-gate-clk                          S   d              i   `            ‘   +      dbg_at_clk          6             !altr,socfpga-gate-clk                       S   h               i   `            ‘         dbg_clk         6             !altr,socfpga-gate-clk                       S   h              i   `         dbg_trace_clk           6             !altr,socfpga-gate-clk                       S   l               i   `         dbg_timer_clk           6             !altr,socfpga-gate-clk                       i   `         cfg_clk         6             !altr,socfpga-gate-clk                       i   `         h2f_user0_clk           6             !altr,socfpga-gate-clk                       i   `   	      emac_0_clk          6             !altr,socfpga-gate-clk                       i                 ‘   &      emac_1_clk          6             !altr,socfpga-gate-clk                       i                ‘   (      usb_mp_clk          6             !altr,socfpga-gate-clk                       i               S   ¤                ‘   5      spi_m_clk           6             !altr,socfpga-gate-clk                       i               S   ¤               ‘   2      can0_clk            6             !altr,socfpga-gate-clk                       i               S   ¤               ‘         can1_clk            6             !altr,socfpga-gate-clk                       i               S   ¤   	            ‘   	      gpio_db_clk         6             !altr,socfpga-gate-clk                       i               S   ¨             h2f_user1_clk           6             !altr,socfpga-gate-clk                       i             sdmmc_clk           6             !altr,socfpga-gate-clk                             i                ‘         sdmmc_clk_divided           6             !altr,socfpga-gate-clk                       i               [            ‘   -      nand_x_clk          6             !altr,socfpga-gate-clk                             i       	         ‘         nand_ecc_clk            6             !altr,socfpga-gate-clk                       i       	         ‘   /      nand_clk            6             !altr,socfpga-gate-clk                       i       
        [            ‘   .      qspi_clk            6             !altr,socfpga-gate-clk                              i                ‘   0      ddr_dqs_clk_gate            6             !altr,socfpga-gate-clk               !        i   Ø          ddr_2x_dqs_clk_gate         6             !altr,socfpga-gate-clk               "        i   Ø         ddr_dq_clk_gate         6             !altr,socfpga-gate-clk               #        i   Ø         h2f_user2_clk           6             !altr,socfpga-gate-clk               $        i   Ø               fpga_bridge@ff400000             !altr,socfpga-lwhps2fpga-bridge           |ÿ@                   a                  	  /disabled          fpga_bridge@ff500000             !altr,socfpga-hps2fpga-bridge             |ÿP                   `                  	  /disabled          fpga-bridge@ff600000             !altr,socfpga-fpga2hps-bridge             |ÿ`                   b                  	  /disabled          fpga-bridge@ffc25080             !altr,socfpga-fpga2sdram-bridge           |ÿÂP€         	  /disabled          fpgamgr@ff706000             !altr,socfpga-fpga-mgr            |ÿp`    ÿ¹              ª       ¯            ‘         stmmac-axi-config           r           ‚           ’                                    ‘   '      ethernet@ff700000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         œ   %   `             |ÿp               ª       s           ¯macirq          ¿                    &      
  stmmaceth                        
  stmmaceth           Ë           æ   €                                 '      	  /disabled          ethernet@ff702000         0   !altr,socfpga-stmmac snps,dwmac-3.70a snps,dwmac         œ   %   `            |ÿp               ª       x           ¯macirq              (      
  stmmaceth                 !      
  stmmaceth           Ë           æ   €                                 '        /okay          	  .rgmii-id            7   )   mdio0                                      !snps,dwmac-mdio    ethernet-phy@3           |           B          N  ¤        [  ¤        h  ¤        u  ¤        ‚  ¤          D        ›            ¨            µ            Â            Ï             ‘   )            gpio@ff708000                                      !snps,dw-apb-gpio             |ÿp€                *              9        /okay       gpio-controller@0            !snps,dw-apb-gpio-port            Ü        ì           ø            |              Ù         È            ª       ¤            gpio@ff709000                                      !snps,dw-apb-gpio             |ÿp                *              :        /okay       gpio-controller@0            !snps,dw-apb-gpio-port            Ü        ì           ø            |              Ù         È            ª       ¥            gpio@ff70a000                                      !snps,dw-apb-gpio             |ÿp                 *              ;      	  /disabled       gpio-controller@0            !snps,dw-apb-gpio-port            Ü        ì           ø            |              Ù         È            ª       ¦            i2c@ffc04000                                       !snps,designware-i2c          |ÿÀ@                  ,            +         ª       ž           /okay              ,        C †    rtc@6f           !isil,isl12022            |   o      crypto@64            !atmel,atsha204a          |   d      clock-controller@70          !silabs,si5338            |   p         i2c@ffc05000                                       !snps,designware-i2c          |ÿÀP                  -            +         ª       Ÿ           /okay              ,      i2c@ffc06000                                       !snps,designware-i2c          |ÿÀ`                  .            +         ª                 	  /disabled          i2c@ffc07000                                       !snps,designware-i2c          |ÿÀp                  /            +         ª       ¡         	  /disabled          eccmgr           !altr,socfpga-ecc-manager                                       î   l2-ecc@ffd08140          !altr,socfpga-l2-ecc          |ÿÐ@            ª       $          %         ocram-ecc@ffd08144           !altr,socfpga-ocram-ecc           |ÿÐD              ,         ª       ²          ³            cache-controller@fffef000            !arm,pl310-cache          |ÿþð             ª       &                     .           :                 J                 [           i            x        Œ                        ¹           Ò            ä            ‘         l3regs@ff800000          !altr,l3regs syscon           |ÿ€           mmc@ff704000             !altr,socfpga-dw-mshc             |ÿp@             ª       ‹                                                    *   -        biu ciu               6        œ   %             /okay             ø                                     /       ‡      nand-controller@ff900000                                       !altr,socfpga-denali-nand             |ÿ     ÿ¸             ?nand_data denali_reg             ª                      .      /        nand nand_x ecc               $      	  /disabled          sram@ffff0000         
   !mmio-sram            |ÿÿ              ‘   ,      spi@ff705000          !   !intel,socfpga-qspi cdns,qspi-nor                                       |ÿpP    ÿ               ª       —           I   €        Y           i                0              %      	  /disabled       flash@0          ~                                  !jedec,spi-nor            |            ’           £           ´ ˜–€        Æ           Ö   2        ä   2        ò                  partition@raw         
  Flash Raw            |                   rstmgr@ffd05000                     !altr,rst-mgr             |ÿÐP            !            ‘         snoop-control-unit@fffec000          !arm,cortex-a9-scu            |ÿþÀ          sdr@ffc25000             !altr,sdr-ctl syscon          |ÿÂP                  =         ‘   1      sdramedac            !altr,sdram-edac         4   1         ª       '         spi@fff00000             !snps,dw-apb-ssi                                    |ÿð              ª       š           D               2              2        spi       	  /disabled          spi@fff01000             !snps,dw-apb-ssi                                    |ÿð             ª       ›           D               2              3        spi       	  /disabled          sysmgr@ffd08000          !altr,sys-mgr syscon          |ÿÐ€   @         KÿÐ€Ä         ‘   %      timer@fffec600           !arm,cortex-a9-twd-timer          |ÿþÆ             ª                    3      timer0@ffc08000          !snps,dw-apb-timer            ª       §            |ÿÀ€                +        timer                 *        timer         timer1@ffc09000          !snps,dw-apb-timer            ª       ¨            |ÿÀ                +        timer                 +        timer         timer2@ffd00000          !snps,dw-apb-timer            ª       ©            |ÿÐ                 
        timer                 (        timer         timer3@ffd01000          !snps,dw-apb-timer            ª       ª            |ÿÐ                
        timer                 )        timer         serial@ffc02000          !snps,dw-apb-uart             |ÿÀ              ª       ¢           [           e               +        r   4      4           wtx rx                 0        Cõá       serial@ffc03000          !snps,dw-apb-uart             |ÿÀ0             ª       £           [           e               +        r   4      4           wtx rx                 1      usbphy                       !usb-nop-xceiv           /okay             ‘   6      usb@ffb00000          
   !snps,dwc2            |ÿ°    ÿÿ         ª       }               5        otg               "        dwc2            Œ   6      	  ‘usb2-phy          	  /disabled          usb@ffb40000          
   !snps,dwc2            |ÿ´    ÿÿ         ª       €               5        otg               #        dwc2            Œ   6      	  ‘usb2-phy            /okay            ›host          watchdog@ffd02000            !snps,dw-wdt          |ÿÐ              ª       «               
              &        /okay          watchdog@ffd03000            !snps,dw-wdt          |ÿÐ0             ª       ¬               
              '      	  /disabled             chosen          £serial0:115200n8          memory           pmemory           |    €            	#address-cells #size-cells model compatible serial0 serial1 timer0 timer1 timer2 timer3 ethernet0 enable-method device_type reg next-level-cache phandle interrupt-parent interrupts interrupt-affinity #interrupt-cells interrupt-controller ranges #dma-cells clocks clock-names resets reset-names fpga-mgr status #clock-cells clock-frequency div-reg fixed-divider clk-gate snps,wr_osr_lmt snps,rd_osr_lmt snps,blen altr,sysmgr-syscon interrupt-names mac-address snps,multicast-filter-bins snps,perfect-filter-entries tx-fifo-depth rx-fifo-depth snps,axi-config phy-mode phy-handle rxc-skew-ps rxd0-skew-ps rxd1-skew-ps rxd2-skew-ps rxd3-skew-ps rxdv-skew-ps txc-skew-ps txd0-skew-ps txd1-skew-ps txd2-skew-ps txd3-skew-ps txen-skew-ps gpio-controller #gpio-cells snps,nr-gpios i2c-sda-hold-time-ns iram cache-unified cache-level arm,tag-latency arm,data-latency prefetch-data prefetch-instr arm,shared-override arm,double-linefill arm,double-linefill-incr arm,double-linefill-wrap arm,prefetch-drop arm,prefetch-offset broken-cd bus-width cap-mmc-highspeed cap-sd-highspeed clk-phase-sd-hs reg-names cdns,fifo-depth cdns,fifo-width cdns,trigger-address u-boot,dm-pre-reloc spi-rx-bus-width spi-tx-bus-width spi-max-frequency cdns,read-delay cdns,tshsl-ns cdns,tsd2d-ns cdns,tchsh-ns cdns,tslch-ns label #reset-cells altr,modrst-offset altr,sdr-syscon num-cs cpu1-start-addr reg-shift reg-io-width dmas dma-names #phy-cells phys phy-names dr_mode stdout-path 