  V   8  R   (              Q                             =    xlnx,versal-net-vnx-revA xlnx,versal-net-vnx xlnx,versal-net             Xilinx Versal NET VNX revA                                    ,             =   options    u-boot            u-boot,config            J                 cpus                                 cpu-map    cluster0       core0            Z         core1            Z         core2            Z         core3            Z            cluster1       core0            Z         core1            Z         core2            Z         core3            Z   	         cluster2       core0            Z   
      core1            Z         core2            Z         core3            Z            cluster3       core0            Z         core1            Z         core2            Z         core3            Z               cpu@0             arm,cortex-a78           ^cpu          jpsci             x             |                                       @                                    @                                	      l2-cache              cache                                      @                                         	            cpu@100           arm,cortex-a78           ^cpu          jpsci             x            |                                       @                                    @                                	      l2-cache              cache                                      @                                         	            cpu@200           arm,cortex-a78           ^cpu          jpsci             x            |                                       @                                    @                                	      l2-cache              cache                                      @                                         	            cpu@300           arm,cortex-a78           ^cpu          jpsci             x            |                                       @                                    @                                	      l2-cache              cache                                      @                                         	            cpu@10000             arm,cortex-a78           ^cpu          jpsci             x            |                                       @                                    @                                	      l2-cache              cache                                      @                                         	            cpu@10100             arm,cortex-a78           ^cpu          jpsci             x           |                                       @                                    @                                	      l2-cache              cache                                      @                                         	            cpu@10200             arm,cortex-a78           ^cpu          jpsci             x           |                                       @                                    @                                	      l2-cache              cache                                      @                                         	            cpu@10300             arm,cortex-a78           ^cpu          jpsci             x           |                                       @                                    @                                	   	   l2-cache              cache                                      @                                         	            cpu@20000             arm,cortex-a78           ^cpu          jpsci             x            |                                       @                                    @                                	   
   l2-cache              cache                                      @                                         	            cpu@20100             arm,cortex-a78           ^cpu          jpsci             x           |                                       @                                    @                                 	      l2-cache              cache                                      @                                         	             cpu@20200             arm,cortex-a78           ^cpu          jpsci             x           |                                       @                                    @                        !        	      l2-cache              cache                                      @                                         	   !         cpu@20300             arm,cortex-a78           ^cpu          jpsci             x           |                                       @                                    @                        "        	      l2-cache              cache                                      @                                         	   "         cpu@30000             arm,cortex-a78           ^cpu          jpsci             x            |                                       @                                    @                        #        	      l2-cache              cache                                      @                                 $        	   #         cpu@30100             arm,cortex-a78           ^cpu          jpsci             x           |                                       @                                    @                        %        	      l2-cache              cache                                      @                                 $        	   %         cpu@30200             arm,cortex-a78           ^cpu          jpsci             x           |                                       @                                    @                        &        	      l2-cache              cache                                      @                                 $        	   &         cpu@30300             arm,cortex-a78           ^cpu          jpsci             x           |                                       @                                    @                        '        	      l2-cache              cache                                      @                                 $        	   '         l3-0-cache            cache                                       @                                 (        	         l3-1-cache            cache                                       @                                 (        	         l3-2-cache            cache                                       @                                 (        	         l3-3-cache            cache                                       @                                 (        	   $      l4-cache              cache                                           	   (      idle-states         +psci       cpu-sleep-0           arm,idle-state          8@            O        `  ,        q  X          '        	               opp-table             operating-points-v2         	      opp-1066000000              ?ހ         B@                opp-1866000000              o8         B@                opp-1900000000              q?          B@                opp-1999000000              w&Q         B@                opp-2050000000              z0         B@                opp-2100000000              }+u          B@                opp-2200000000              !V          B@                opp-2400000000                        B@                   aliases         /axi/serial@f1920000            /axi/serial@f1930000            /dcc            /axi/mmc@f1040000           /axi/mmc@f1050000           /axi/i2c@f1940000           /axi/i2c@f1950000           /axi/rtc@f12a0000           /axi/usb@f1e00000           /axi/usb@f1e10000           /axi/spi@f1010000           /axi/spi@f1030000         dcc           arm,dcc       	  disabled                   firmware       psci              arm,psci-1.0             qsmc       versal-net-firmware       .    xlnx,versal-net-firmware xlnx,versal-firmware                     qsmc          fpga-region           fpga-region            )                               timer             arm,armv8-timer       0                                   
         versal-fpga           xlnx,versal-fpga            	   )      axi           simple-bus                                             "   dma-controller@ebd00000           xlnx,zynqmp-dma-1.0       	  disabled             x                            H           )clk_main clk_apb            5           @   @        O   *   *      dma-controller@ebd10000           xlnx,zynqmp-dma-1.0       	  disabled             x                            I           )clk_main clk_apb            5           @   @        O   *   *      dma-controller@ebd20000           xlnx,zynqmp-dma-1.0       	  disabled             x                            J           )clk_main clk_apb            5           @   @        O   *   *      dma-controller@ebd30000           xlnx,zynqmp-dma-1.0       	  disabled             x                            K           )clk_main clk_apb            5           @   @        O   *   *      dma-controller@ebd40000           xlnx,zynqmp-dma-1.0       	  disabled             x                            L           )clk_main clk_apb            5           @   @        O   *   *      dma-controller@ebd50000           xlnx,zynqmp-dma-1.0       	  disabled             x                            M           )clk_main clk_apb            5           @   @        O   *   *      dma-controller@ebd60000           xlnx,zynqmp-dma-1.0       	  disabled             x                            N           )clk_main clk_apb            5           @   @        O   *   *      dma-controller@ebd70000           xlnx,zynqmp-dma-1.0       	  disabled             x                            O           )clk_main clk_apb            5           @   @        O   *   *      can@f1980000              xlnx,canfd-2.0        	  disabled             x            `                           )can_clk s_axi_aclk          V   @        d            O   +   +      can@f1990000              xlnx,canfd-2.0        	  disabled             x            `                           )can_clk s_axi_aclk          V   @        d            O   +   +      ethernet@f19e0000             xlnx,versal-gem cdns,gem          	  disabled             x                            '          '            )pclk hclk tx_clk rx_clk tsu_clk         O   ,   ,   ,   ,   -      ethernet@f19f0000             xlnx,versal-gem cdns,gem            okay             x                            )          )            )pclk hclk tx_clk rx_clk tsu_clk         O   ,   ,   ,   ,   -        u   .  5        |   /        rmii       mdio                                 ethernet-phy@4           x           	   /            interrupt-controller@e2000000             arm,gic-v3                       x                                                   	                                     "        	      msi-controller@e2040000           arm,gic-v3-its                               x                      gpio@f19d0000             xlnx,versal-gpio-1.0          	  disabled             x                                                                               O   0      gpio@f1020000             xlnx,pmc-gpio-1.0         	  disabled             x                                                                               O   0      i2c@f1940000              cdns,i2c-r1p14        	  disabled             x                                                                          O   0      i2c@f1950000              cdns,i2c-r1p14        	  disabled             x                                                                          O   0      i3c@f1948000              snps,dw-i3c-master-1.00a          	  disabled             x                                                                O   0      i3c@f1958000              snps,dw-i3c-master-1.00a          	  disabled             x                                                                O   0      spi@f1010000          #    xlnx,versal-ospi-1.0 cdns,qspi-nor        	  disabled              x                                                                                       (           O   1        =           u   .  E                                spi@f1030000              xlnx,versal-qspi-1.0          	  disabled             x                                       )ref_clk pclk            O   2   2      rtc@f12a0000              xlnx,zynqmp-rtc       	  disabled             x    *                                           
  Dalarm sec           T        mmc@f1040000          #    xlnx,versal-8.9a arasan,sdhci-8.9a        	  disabled             x                                       )clk_xin clk_ahb gate            `           mclk_out_sd0 clk_in_sd0          O   1   1   3      mmc@f1050000              xlnx,versal-net-emmc            okay             x                                       )clk_xin clk_ahb gate            `           mclk_out_sd1 clk_in_sd1          O   1   1   3        u   .  C                                                     E                  serial@f1920000                    arm,pl011 arm,primecell       	  disabled             x                                                  )uartclk apb_pclk            O   0   0      serial@f1930000                    arm,pl011 arm,primecell         okay             x                                                  )uartclk apb_pclk            O   0   0      iommu@ec000000            arm,smmu-v3         okay             x                               	  Dcombined                                =        	   .      spi@f1960000              cdns,spi-r1p6         	  disabled                               x                     )ref_clk pclk            O   1   1      spi@f1970000              cdns,spi-r1p6         	  disabled                               x                     )ref_clk pclk            O   1   1      timer@f1dc0000        	    cdns,ttc          	  disabled          $         +          ,          -                        x                     O   4      timer@f1dd0000        	    cdns,ttc          	  disabled          $         .          /          0                        x                   timer@f1de0000        	    cdns,ttc          	  disabled          $         1          2          3                        x                   timer@f1df0000        	    cdns,ttc          	  disabled          $         4          5          6                        x                   usb@f1e00000              xlnx,versal-dwc3          	  disabled             x                     )bus_clk ref_clk          "                                 O   5   5   usb@f1b00000          
    snps,dwc3         	  disabled             x                     Dhost peripheral otg wakeup        0                             !          b                                          <peripheral          Dhigh-speed           R        )ref         O   5         usb@f1e10000              xlnx,versal-dwc3          	  disabled             x                     )bus_clk ref_clk          "                                 O   5   5   usb@f1c00000          
    snps,dwc3         	  disabled             x                     Dhost peripheral otg wakeup        0         "          "          &          c                                          <host            Dhigh-speed           R        )ref         O   5         watchdog@ecc10000             xlnx,versal-wwdt          	  disabled             x                     h           O   4      watchdog@ecd10000             xlnx,versal-wwdt          	  disabled             x                     h           O   4      watchdog@ece10000             xlnx,versal-wwdt          	  disabled             x                     h           O   4      watchdog@ecf10000             xlnx,versal-wwdt          	  disabled             x                     h           O   4      watchdog@ea420000             xlnx,versal-wwdt          	  disabled             x    B                 h           O   4      watchdog@ea430000             xlnx,versal-wwdt          	  disabled             x    C                 h           O   4         clk60             fixed-clock         `                     	   5      clk100            fixed-clock         `                     	   0      clk125            fixed-clock         `            sY@        	   ,      clk150            fixed-clock         `            р        	   4      clk160            fixed-clock         `            	h         	   +      clk200            fixed-clock         `                     	   1      clk250            fixed-clock         `            沀        	   -      clk300            fixed-clock         `                     	   2      clk450            fixed-clock         `            t        	   *      clk1200           fixed-clock         `            G         	   3      memory@0             x                        ^memory        memory@800000000             x                      ^memory        memory@50000000000           x                       ^memory        chosen          tconsole=ttyAMA1,115200n8            }serial1:115200n8          reserved-memory                                   "   rproc@bbf14000           x    @                       rpu0vdev0vring0@bbf15000             x    P                       rpu0vdev0vring1@bbf16000             x    `                       rpu0vdev0buffer@bbf17000             x    p                       reserveothers@0          x                              pdiupdate@1c200000           x                             reserveopteeatf@22200000             x    "                              	compatible model #address-cells #size-cells interrupt-parent dma-coherent bootscr-address cpu device_type enable-method reg operating-points-v2 cpu-idle-states d-cache-size d-cache-line-size d-cache-sets i-cache-size i-cache-line-size i-cache-sets next-level-cache phandle cache-level cache-unified entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us opp-hz opp-microvolt clock-latency-ns serial0 serial1 serial2 mmc0 mmc1 i2c0 i2c1 rtc usb0 usb1 spi0 spi1 status bootph-all fpga-mgr interrupts ranges clock-names #dma-cells xlnx,bus-width clocks rx-fifo-depth tx-mailbox-count iommus phy-handle phy-mode #interrupt-cells interrupt-controller msi-controller #msi-cells #gpio-cells gpio-controller clock-frequency cdns,fifo-depth cdns,fifo-width cdns,is-dma cdns,trigger-address num-cs interrupt-names calibration #clock-cells clock-output-names non-removable disable-wp no-sd no-sdio cap-mmc-hw-reset no-1-8-v reg-io-width #iommu-cells timer-width snps,dis_u2_susphy_quirk snps,dis_u3_susphy_quirk snps,quirk-frame-length-adjustment dr_mode maximum-speed snps,usb3_lpm_capable timeout-sec bootargs stdout-path no-map 