 RH   8 F   (            0 E                             .    radxa,nio-12l mediatek,mt8395 mediatek,mt8195                                    +            7Radxa NIO 12L         	   =embedded       aliases          J/soc/dp-intf@1c015000            S/soc/dp-intf@1c113000            \/soc/mailbox@10320000            a/soc/mailbox@10330000            f/soc/hdr-engine@1c114000             m/soc/mutex@1c016000          t/soc/mutex@1c101000          {/soc/vpp-merge@1c10c000          /soc/vpp-merge@1c10d000          /soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000             /soc/i2c@11e02000            /soc/i2c@11e03000            /soc/i2c@11e04000           /soc/i2c@11e00000           
/soc/i2c@11e01000           /soc/ethernet@11021000          /soc/serial@11001100            !/soc/serial@11001200            )/soc/spi@11010000           ./soc/spi@11012000         cpus                         +       cpu@0           3cpu           arm,cortex-a55          ?            Cpsci            Q               eec3@        u  4                                    @                                 @                                            	      cpu@100         3cpu           arm,cortex-a55          ?           Cpsci            Q               eec3@        u  4                                    @                                 @                                            
      cpu@200         3cpu           arm,cortex-a55          ?           Cpsci            Q               eec3@        u  4                                    @                                 @                                                  cpu@300         3cpu           arm,cortex-a55          ?           Cpsci            Q               eec3@        u  4                                    @                                 @                                                  cpu@400         3cpu           arm,cortex-a78          ?           Cpsci            Q              ef        u                                       @                                 @                                                  cpu@500         3cpu           arm,cortex-a78          ?           Cpsci            Q              ef        u                                       @                                 @                                                  cpu@600         3cpu           arm,cortex-a78          ?           Cpsci            Q              ef        u                                       @                                 @                                                  cpu@700         3cpu           arm,cortex-a78          ?           Cpsci            Q              ef        u                                       @                                 @                                                  cpu-map    cluster0       core0              	      core1              
      core2                    core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-retention-l           arm,idle-state          )           @        Q   2        b   _        r  D                 cpu-retention-b           arm,idle-state          )           @        Q   -        b           r                   cpu-off-l             arm,idle-state          )          @        Q   7        b           r  H                 cpu-off-b             arm,idle-state          )          @        Q   2        b           r                      l2-cache0             cache                                    @                                                l2-cache1             cache                                    @                                                l3-cache              cache                                     @                                        dsu-pmu           arm,dsu-pmu                                   	   
                          fail          dmic-codec            dmic-codec                        2      mt8195-sound                     	  disabled          fixed-factor-clock-13m            fixed-factor-clock                                                       clk13m             (      oscillator-26m            fixed-clock                     e        clk26m                   oscillator-32k            fixed-clock                     e           clk32k        performance-controller@11bc10             mediatek,cpufreq-hw          ?                 0                                   opp-table-gpu             operating-points-v2          9           o   opp-390000000           D    >        K 	h      opp-410000000           D    p        K 	      opp-431000000           D            K 	      opp-473000000           D    1h@        K 	<      opp-515000000           D    F        K 	<      opp-556000000           D    !#         K 	Ҧ      opp-598000000           D    #        K 	      opp-640000000           D    &%         K 	      opp-670000000           D    'c        K 
      opp-700000000           D    )'         K 
L      opp-730000000           D    +        K 
}      opp-760000000           D    -L         K 
`      opp-790000000           D    /q        K 
4      opp-820000000           D    05         K       opp-850000000           D    2        K @      opp-880000000           D    4s         K q         pmu-a55           arm,cortex-a55-pmu                                        pmu-a78           arm,cortex-a78-pmu                                        psci              arm,psci-1.0            Jsmc       timer             arm,armv8-timer                   @                                               
             soc                      +             simple-bus           Y        `                          interrupt-controller@c000000              arm,gic-v3          k           |                                 ?                                          	                     ppi-partitions     interrupt-partition-0              	   
                       interrupt-partition-1                                              syscon@10000000            mediatek,mt8195-topckgen syscon         ?                                          syscon@10001000       .    mediatek,mt8195-infracfg_ao syscon simple-mfd           ?                                                    syscon@10003000           mediatek,mt8195-pericfg syscon          ?     0                              >      pinctrl@10005000              mediatek,mt8195-pinctrl         ?     P                                                                                                         B  iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint                                                                                    k                 eth-default-pins               :   pins-cc           U  V  W  X                 pins-mdio             Y  Z               pins-power            [   \                pins-rst              ]       pins-rxd              Q  R  S  T      pins-txd              M  N  O  P                    eth-sleep-pins             ;   pins-cc           U   V   W   X       pins-mdio             Y   Z                   ,      pins-rxd              Q   R   S   T       pins-txd              M   N   O   P          i2c2-pins              ]   pins-bus                        :                      G           i2c4-pins              `   pins-bus                        :           G           i2c6-pins              V   pins                                  mmc0-default-pins              B   pins-clk              z        _   f                 pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y        :   e                          pins-rst              x        :   e                    mmc0-uhs-pins              C   pins-clk              z        _   f                 pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y        :   e                          pins-ds                   _   f                 pins-rst              x        :   e                    mmc1-default-pins              F   pins-clk              o        _   f                 pins-cmd-dat              n  p  q  r  s        :   e                             mmc1-detect-pins               G   pins-insert                     :         mt6360-pins            W   pins-irq              d   e                   :         pcie0-default-pins             Q   pins-bus                           :         pcie1-default-pins             T   pins-bus                                     spi1-default-pins              4   pins-bus                                      spi2-default-pins              5   pins-bus                                      uart0-pins             /   pins-bus              b  c         uart1-pins             0   pins-bus              f  g         wifi-vreg-pins                pins-wifi-pmu-en              A                pins-wifi-vreg-en             C             syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            ?     `           power-controller          !    mediatek,mt8195-power-controller                         +            n              +   power-domain@8          ?                        +            n      power-domain@9          ?   	                            mfg alt                                 +            n      power-domain@10         ?   
        n          power-domain@11         ?           n          power-domain@12         ?           n          power-domain@13         ?           n          power-domain@14         ?           n                power-domain@15         ?                                   	      @      A      K                                                                                                                                vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18                                   +            n      power-domain@24         ?                          vdec1-0                    n          power-domain@27         ?                          venc1-larb                     n          power-domain@16         ?         8              $      %      &      '      (      )      D  vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5                                 +            n      power-domain@17         ?                                     vppsys1 vppsys1-0 vppsys1-1                    n          power-domain@22         ?                                          $  wepsys-0 wepsys-1 wepsys-2 wepsys-3                    n          power-domain@23         ?                           vdec0-0                    n          power-domain@25         ?              !            vdec2-0                    n          power-domain@26         ?              "            venc0-larb                     n          power-domain@18         ?                     #       #      #         &  vdosys1 vdosys1-0 vdosys1-1 vdosys1-2                                   +            n      power-domain@19         ?                      n          power-domain@20         ?                      n          power-domain@21         ?                 Q        hdmi_tx         n             power-domain@28         ?              $       $   
        img-0 img-1                                 +            n      power-domain@29         ?           n          power-domain@30         ?                    $      %           ipe ipe-0 ipe-1                    n             power-domain@31         ?         (     &       &      &      &      &           cam-0 cam-1 cam-2 cam-3 cam-4                                   +            n      power-domain@32         ?            n          power-domain@33         ?   !        n          power-domain@34         ?   "        n                   power-domain@0          ?                       n          power-domain@1          ?                      n          power-domain@2          ?           n          power-domain@3          ?           n          power-domain@4          ?                 5      7        csi_rx_top csi_rx_top1          n          power-domain@5          ?              '           ether           n          power-domain@6          ?                 X      n        adsp adsp1                       +                       n      power-domain@7          ?                  g      "      n      2        audio audio1 audio2 audio3                     n                   watchdog@10007000             mediatek,mt8195-wdt                  ?     p                              .      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           ?                                         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         ?    p                      	                  (      pwrap@10024000            mediatek,mt8195-pwrap syscon            ?    @                pwrap                                                    	  spi wrap                  $                 pmic              mediatek,mt6359                  k                       mt6359codec       regulators     buck_vs1            vs1          5          !        2             N      buck_vgpu11         vgpu11                    7        b          2           w                   N      buck_vmodem         vmodem                            b  *        2         buck_vpu            vpu                   7        b          2           w                   N      buck_vcore          vcore                              b          2           w                   N      buck_vs2            vs2          5          j         2             N      buck_vpa            vpa                    7        2  ,      buck_vproc2         vproc2                    7        b  L        2           w                   N      buck_vproc1         vproc1                    7        b  L        2           w                   N      buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub                      7      ldo_vaud18          vaud18           w@         w@        2            N      ldo_vsim1           vsim1                     /M`      ldo_vibr            vibr             O         2Z           ^      ldo_vrf12           vrf12                               N      ldo_vusb            vusb             -         -        2           N           ?      ldo_vsram_proc2         vsram_proc2                            b  L        2            N      ldo_vio18           vio18                             2           N      ldo_vcamio          vcamio                             N      ldo_vcn18           vcn18            w@         w@        2         ldo_vfe28           vfe28            *         *        2   x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_bt           *         5g      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@        2            N      ldo_vsram_others            vsram_others             q         q        b          2         ldo_vefuse          vefuse                          ldo_vxo22           vxo22            w@         !         N      ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *        2         ldo_vio28           vio28            *         2Z         N      ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z           D      ldo_vcn33_2_bt          vcn33_2_bt           2Z         2Z      ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                   N      ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                               b  *        2            N      ldo_vufs            vufs                                 E      ldo_vm18            vm18                               N      ldo_vbbck           vbbck                     O         N      ldo_vsram_proc1         vsram_proc1                            b  L        2            N      ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              mt6359rtc             mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             ?    p                            pmif spmimst                               E      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux               $                                   +       pmic@6            mediatek,mt6315-regulator           ?          regulators     vbuck1          vbuck1          Vbcpu                     7        2           w                   N            pmic@7            mediatek,mt6315-regulator           ?          regulators     vbuck1          vbuck1          Vgpu                      7        2           w                     p               infra-iommu@10315000              mediatek,mt8195-iommu-infra         ?    1P       P       P                                                                                         N      mailbox@10320000              mediatek,mt8195-gce         ?    2        @                                                                 mailbox@10330000              mediatek,mt8195-gce         ?    3        @                                                           q      scp@10500000              mediatek,mt8195-scp       0  ?    P             r             p                 sram cfg l1tcm                               okay               )                 clock-controller@10720000             mediatek,mt8195-scp_adsp            ?    r                               *      dsp@10803000              mediatek,mt8195-dsp          ?    0                           	  cfg sram          ,        X         n         *          #      K  adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             +           rx tx              ,   -      	  disabled          mailbox@10816000              mediatek,mt8195-adsp-mbox                       ?    `                                        ,      mailbox@10817000              mediatek,mt8195-adsp-mbox                       ?    p                                        -      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           ?                                   +                 6                  .         	  audiosys                                                               g      "      #      n      e      a      b      c      d      2   *            clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  disabled                     serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                                          	  baud bus            okay               /        default       serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                                          	  baud bus            okay               0        default       serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                                          	  baud bus          	  disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                                         	  baud bus          	  disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                                         	  baud bus          	  disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                                         	  baud bus          	  disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           ?                                    main            (         	  disabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           ?     0                              '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                                                     parent-clk sel-clk spi-clk        	  disabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         ?                                                                        :   1   2      $  Flvts-calib-data-1 lvts-calib-data-2         W                    svs@1100bc00              mediatek,mt8195-svs         ?                                                         main            :   3   1      (  Fsvs-calibration-data t-calibration-data                       svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           ?                                              +           m                 *      0        main mm       	  disabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           ?                                          m                 +      N        main mm       	  disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                                             3        parent-clk sel-clk spi-clk          okay               4        default         x          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                                             4        parent-clk sel-clk spi-clk          okay               5        default         x          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?    0                                                        5        parent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                                            <        parent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                                            =        parent-clk sel-clk spi-clk        	  disabled          spi@1101d000              mediatek,mt8195-spi-slave           ?                                                R        spi                                   	  disabled          spi@1101e000              mediatek,mt8195-spi-slave           ?                                                S        spi                                   	  disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           ?           @                              macirq        .  axi apb mac_main ptp_ref rmii_internal mac_cg         0     '       '         R      S      T   '                 R      S      T                                     +                         6           7           8                                          okay            rgmii-rxid             9        default sleep              :           ;        $           9        J      ]            Z      N     mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916            ?              9         stmmac-axi-config           o                                                          6      rx-queues-config                                   7   queue0                             queue1                             queue2                             queue3                                tx-queues-config                                   8   queue0                                        queue1                                       queue2                                       queue3                                             usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           ?            -     >              	  mac ippc            Y                     ?                      +                                       /            B        sys_ck ref_ck mcu_ck            -   <      =            2        @   >      g        okay            Whost             p           ?   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          ?                       mac                                     ,      -                          $        /                     B      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         okay               @      port       endpoint               A           Z            mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          ?    #                                                                              source hclk source_cg           okay            default state_uhs              B           C                             L                                    	         	         	         	         	.   D        	:   E      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          ?    $                                                                      $        source hclk source_cg                                       okay            default state_uhs              F   G           F                             	G        	X                  	a         	         	h         	u        	.   H        	:   I      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          ?    %                                                                       I        source hclk source_cg                                      	  disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            ?    '                                                                  :   1   2      $  Flvts-calib-data-1 lvts-calib-data-2         W                    usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           ?    )             )>              	  mac ippc                                 -   J                 .      /                          $     '                     '         $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         @   >      h         2        okay             	           ?           K      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           ?    *       -    *>              	  mac ippc            Y            *        ?                      +                                      0                         '            '           sys_ck ref_ck mcu_ck            -   L            2        @   >      i        okay               ?   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          ?                       mac                                    1                         '           sys_ck          okay               K         usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           ?    +       -    +>              	  mac ippc            Y            +        ?                      +                                      2                         '            '   	        sys_ck ref_ck mcu_ck            -   M            2        @   >      j      	  disabled       usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          ?                       mac                                    3                         '   	        sys_ck        	  disabled             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           3pci                      +           ?    /        @       	  pcie-mac                                 	             8  Y                                                            	       N              	          0        V      #      &      +      K   '         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                G                      -   O      	  	pcie-phy               +                          mac         k           	                     `  	                  P                      P                     P                     P           okay            default            Q   interrupt-controller                                  k              P         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           3pci                      +           ?    /       @       	  pcie-mac                                 	             8  Y       $       $                  $       $                 	       N              	          (        W         X         Q   '         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                H                      -   R         	  	pcie-phy               +                         mac         k           	                     `  	                  S                      S                     S                     S           okay            default            T   interrupt-controller                                  k              S         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         ?    2                      9                     o   '      '           spi sf axi                       +          	  disabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            ?                                  +      usb3-tx-imp@184,1           ?             	                  f      usb3-rx-imp@184,2           ?             	                 e      usb3-intr@185           ?             	                 d      usb3-tx-imp@186,1           ?             	                  c      usb3-rx-imp@186,2           ?             	                 b      usb3-intr@187           ?             	                 a      usb2-intr-p0@188,1          ?             	             usb2-intr-p1@188,2          ?             	            usb2-intr-p2@189,1          ?             	            usb2-intr-p3@189,2          ?             	            pciephy-rx-ln1@190,1            ?             	                  m      pciephy-tx-ln1-nmos@190,2           ?             	                 l      pciephy-tx-ln1-pmos@191,1           ?             	                  k      pciephy-rx-ln0@191,2            ?             	                 j      pciephy-tx-ln0-nmos@192,1           ?             	                  i      pciephy-tx-ln0-pmos@192,2           ?             	                 h      pciephy-glb-intr@193            ?             	                  g      dp-data@1ac         ?                      lvts1-calib@1bc         ?                1      lvts2-calib@1d0         ?     8           2      svs-calib@580           ?     d           3      socinfo-data1@7a0           ?              t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           Y                   	  disabled       usb-phy@0           ?                             ref         	              L         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           Y                   	  disabled       usb-phy@0           ?                             ref         	              M         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         ?                                mipi_tx0_pll                        	          	  disabled                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         ?                                mipi_tx1_pll                        	          	  disabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                 "                                                   U          ;      	  main dma                         +          	  disabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                "                                                    U         ;      	  main dma                         +            okay            e            V        default    pmic@34           mediatek,mt6360         ?   4              e           IRQB                     k              W   charger           mediatek,mt6360-chg         	 @   usb-otg-vbus-regulator          usb-otg-vbus             C(         X           @         regulator             mediatek,mt6360-regulator           
   X        
   Y   buck1         	  emi_vdd2                               w                   N      buck2         	  emi_vddq                               w                   N           Y      ldo1            ext_lcd_3v3          2Z         2Z        w                N      ldo2            panel1_p1v8          w@         w@        w             ldo3            vmc_pmu          O         6        w                  I      ldo5          	  vmch_pmu             2Z         2Z        w                N           H      ldo6            mt6360_ldo6                              w             ldo7            emi_vmddr_en                                 w                N         typec             mediatek,mt6360-tcpc                  d           PD_IRQB    connector             usb-c-connector         
+USB-C           
1dual            
;         
Mdual            
Xsink            
g"d        
s",   ports                        +       port@0          ?       endpoint               Z           A         port@2          ?      endpoint               [           _                        i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                 "                                                   U         ;      	  main dma                         +          	  disabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          ?    0                              U      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                 "                                                    \          ;      	  main dma                         +          	  disabled          i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                "                                                    \         ;      	  main dma                         +          	  disabled          i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                 "                                                   \         ;      	  main dma                         +            okay            e            ]        default    typec-mux@48              ite,it5205          ?   H         
}         
        
   ^   port       endpoint               _           [               i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    0            "                                                   \         ;      	  main dma                         +          	  disabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    @            "                                                    \         ;      	  main dma                         +            okay            e            `        default       clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          ?    P                              \      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           Y                        +         	  disabled       usb-phy@0           ?                                ref da_ref          	              J      usb-phy@700         ?                                  ref da_ref          :   a   b   c        Fintr rx_imp tx_imp          	              R         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           Y                   	  disabled       usb-phy@0           ?                                ref da_ref          	              <      usb-phy@700         ?                                  ref da_ref          :   d   e   f        Fintr rx_imp tx_imp          	              =         phy@11e80000              mediatek,mt8195-pcie-phy            ?                     sif         :   g   h   i   j   k   l   m      G  Fglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             +           	          	  disabled               O      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           ?                                 
  unipro mp           	          	  disabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           ?             @            n          0                                                 job mmu gpu         
   o      (     +   
   +      +      +      +           
core0 core1 core2 core3 core4           okay            
   p      clock-controller@13fbf000             mediatek,mt8195-mfgcfg          ?                                  n      syscon@14000000           mediatek,mt8195-vppsys0 syscon          ?                                 
   q                            dma-controller@14001000           mediatek,mt8195-mdp3-rdma           ?                     
   q                  
                 +              r                       <     q         q         q         q         q                       display@14002000              mediatek,mt8195-mdp3-fg         ?                      
   q                                display@14003000              mediatek,mt8195-mdp3-stitch         ?     0                
   q      0                        display@14004000              mediatek,mt8195-mdp3-hdr            ?     @                
   q      @                  "      display@14005000              mediatek,mt8195-mdp3-aal            ?     P                      F               
   q      P                  
           +         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?     `                
   q      `            
    %                    display@14007000              mediatek,mt8195-mdp3-tdshp          ?     p                
   q      p                  #      display@14008000              mediatek,mt8195-mdp3-color          ?                           I               
   q                        $           +         display@14009000              mediatek,mt8195-mdp3-ovl            ?                           J               
   q                        %           +              r         display@1400a000              mediatek,mt8195-mdp3-padding            ?                     
   q                                   +         display@1400b000              mediatek,mt8195-mdp3-tcc            ?                     
   q                              dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?                     
   q                  
    +                         r              +                    mutex@1400f000            mediatek,mt8195-vpp-mutex           ?                           P               
   q                                   +         smi@14010000              mediatek,mt8195-smi-sub-common          ?                                               apb smi gals0              s           +              t      smi@14011000              mediatek,mt8195-smi-sub-common          ?                                              apb smi gals0              s           +                    smi@14012000              mediatek,mt8195-smi-common-vpp          ?                                                      apb smi gals0 gals1            +              s      larb@14013000             mediatek,mt8195-smi-larb            ?    0                %              t                            apb smi            +              w      iommu@14018000            mediatek,mt8195-iommu-vpp           ?                  8  6   u   v   w   x   y   z   {   |   }   ~                          R                             bclk                          +              r      clock-controller@14e00000             mediatek,mt8195-wpesys          ?                                         clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         ?                              clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         ?    0                         larb@14e04000             mediatek,mt8195-smi-larb            ?    @                %                                          apb smi            +                    larb@14e05000             mediatek,mt8195-smi-larb            ?    P                %              s                                  apb smi gals               +              y      syscon@14f00000           mediatek,mt8195-vppsys1 syscon          ?                                
   q   	                        mutex@14f01000            mediatek,mt8195-vpp-mutex           ?                          {               
   q   	                    '           +         larb@14f02000             mediatek,mt8195-smi-larb            ?                     %                                                apb smi gals               +                    larb@14f03000             mediatek,mt8195-smi-larb            ?    0                %              t                                  apb smi gals               +              x      display@14f06000              mediatek,mt8195-mdp3-split          ?    `                
   q   	  `                        +      ,           +         display@14f07000              mediatek,mt8195-mdp3-tcc            ?    p                
   q   	  p                        dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           ?                    
   q   	              
                                           +                    dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           ?                    
   q   	              
                  
                         +                    dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           ?                    
   q   	              
                             r              +                    display@14f0b000              mediatek,mt8195-mdp3-fg         ?                    
   q   	                    	      display@14f0c000              mediatek,mt8195-mdp3-fg         ?                    
   q   	                          display@14f0d000              mediatek,mt8195-mdp3-fg         ?                    
   q   	                          display@14f0e000              mediatek,mt8195-mdp3-hdr            ?                    
   q   	                          display@14f0f000              mediatek,mt8195-mdp3-hdr            ?                    
   q   	                          display@14f10000              mediatek,mt8195-mdp3-hdr            ?                     
   q   
                            display@14f11000              mediatek,mt8195-mdp3-aal            ?                          i               
   q   
                               +         display@14f12000              mediatek,mt8195-mdp3-aal            ?                           j               
   q   
                                +         display@14f13000              mediatek,mt8195-mdp3-aal            ?    0                      k               
   q   
  0                  !           +         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?    @                
   q   
  @            
                        display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?    P                
   q   
  P            
                  $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?    `                
   q   
  `            
                  %      display@14f17000              mediatek,mt8195-mdp3-tdshp          ?    p                
   q   
  p                        display@14f18000              mediatek,mt8195-mdp3-tdshp          ?                    
   q   
                    (      display@14f19000              mediatek,mt8195-mdp3-tdshp          ?                    
   q   
                    )      display@14f1a000              mediatek,mt8195-mdp3-merge          ?                    
   q   
                               +         display@14f1b000              mediatek,mt8195-mdp3-merge          ?                    
   q   
                               +         display@14f1c000              mediatek,mt8195-mdp3-color          ?                          t               
   q   
                               +         display@14f1d000              mediatek,mt8195-mdp3-color          ?                    
   q   
                    u                                +         display@14f1e000              mediatek,mt8195-mdp3-color          ?                          v               
   q   
                               +         display@14f1f000              mediatek,mt8195-mdp3-ovl            ?                          w               
   q   
                                +                       display@14f20000              mediatek,mt8195-mdp3-padding            ?                     
   q                                   +         display@14f21000              mediatek,mt8195-mdp3-padding            ?                    
   q                                  +         display@14f22000              mediatek,mt8195-mdp3-padding            ?                     
   q                                   +         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?    0                
   q     0            
                                           +                    dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?    @                
   q     @            
                                           +                    dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?    P                
   q     P            
                             r              +                    clock-controller@15000000             mediatek,mt8195-imgsys          ?                                    $      larb@15001000             mediatek,mt8195-smi-larb            ?                     %   	                      $       $       $   
        apb smi gals               +                    smi@15002000              mediatek,mt8195-smi-sub-common          ?                         $      $                 apb smi gals0              s           +                    smi@15003000              mediatek,mt8195-smi-sub-common          ?     0                   $       $       $   
        apb smi gals0                         +                    clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         ?                                         larb@15120000             mediatek,mt8195-smi-larb            ?                     %   
                      $                  apb smi            +                    clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          ?                              clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         ?    "                                     larb@15230000             mediatek,mt8195-smi-larb            ?    #                 %                         $                  apb smi            +                    clock-controller@15330000             mediatek,mt8195-ipesys          ?    3                               %      larb@15340000             mediatek,mt8195-smi-larb            ?    4                 %                         %      %           apb smi            +              z      clock-controller@16000000             mediatek,mt8195-camsys          ?                                    &      larb@16001000             mediatek,mt8195-smi-larb            ?                     %                         &       &       &           apb smi gals               +                    larb@16002000             mediatek,mt8195-smi-larb            ?                      %                         &      &           apb smi            +              {      smi@16004000              mediatek,mt8195-smi-sub-common          ?     @                   &       &       &           apb smi gals0                         +                    smi@16005000              mediatek,mt8195-smi-sub-common          ?     P                   &      &                 apb smi gals0              s           +                    larb@16012000             mediatek,mt8195-smi-larb            ?                     %                                            apb smi            +               |      larb@16013000             mediatek,mt8195-smi-larb            ?    0                %                                            apb smi            +                     larb@16014000             mediatek,mt8195-smi-larb            ?    @                %                                            apb smi            +   !                 larb@16015000             mediatek,mt8195-smi-larb            ?    P                %                                            apb smi            +   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa         ?                                        clock-controller@1606f000             mediatek,mt8195-camsys_yuva         ?                                        clock-controller@1608f000             mediatek,mt8195-camsys_rawb         ?                                        clock-controller@160af000             mediatek,mt8195-camsys_yuvb         ?    
                                    clock-controller@16140000             mediatek,mt8195-camsys_mraw         ?                                         larb@16141000             mediatek,mt8195-smi-larb            ?                    %                         &              &           apb smi gals               +   "                 larb@16142000             mediatek,mt8195-smi-larb            ?                     %                                            apb smi            +   "                 clock-controller@17200000             mediatek,mt8195-ccusys          ?                                          larb@17201000             mediatek,mt8195-smi-larb            ?                     %                                            apb smi            +              }      video-codec@18000000              mediatek,mt8195-vcodec-dec          E                                     +            ?                   @                Y                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         ?                          r     r                 A                            sel vdec lat top                  A                         +         video-codec@10000             mediatek,mtk-vcodec-lat         ?                                         0                                                A                            sel vdec lat top                  A                         +         video-codec@25000             mediatek,mtk-vcodec-core            ?     P                                   P                                                                   A                          sel vdec lat top                  A                         +            larb@1800d000             mediatek,mt8195-smi-larb            ?                     %                                              apb smi            +                    larb@1800e000             mediatek,mt8195-smi-larb            ?                     %                                            apb smi            +                    clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         ?                                          larb@1802e000             mediatek,mt8195-smi-larb            ?                    %                                            apb smi            +                    clock-controller@1802f000             mediatek,mt8195-vdecsys         ?                                        larb@1803e000             mediatek,mt8195-smi-larb            ?                    %                               !            apb smi            +                    clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           ?                                  !      clock-controller@190f3000             mediatek,mt8195-apusys_pll          ?    0                         clock-controller@1a000000             mediatek,mt8195-vencsys         ?                                    "      larb@1a010000             mediatek,mt8195-smi-larb            ?                     %                         "      "           apb smi            +                    video-codec@1a020000              mediatek,mt8195-vcodec-enc          ?                   H       `     a     b     c     d     v     w     x     y              U               E              "         	  venc_sel                  @                         +                        +         jpgdec-master             mediatek,mt8195-jpgdec             +         0       m     n     r     s     t     u                     +            Y   jpgdec@1a040000           mediatek,mt8195-jpgdec-hw           ?                   0       m     n     r     s     t     u              W                  "           jpgdec             +         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw           ?                   0       m     n     r     s     t     u              X                  "           jpgdec             +         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw           ?                   0     r     r     r     r     r     r                \                             jpgdec             +            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           ?                                          syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            ?                                                 
                             jpgenc-master             mediatek,mt8195-jpgenc             +               r     r     r     r                       +            Y   jpgenc@1a030000           mediatek,mt8195-jpgenc-hw           ?                           g     h     i     l              V                  "           jpgenc             +         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw           ?                         r     r     r     r                [                             jpgenc             +            larb@1b010000             mediatek,mt8195-smi-larb            ?                     %              s                                   apb smi gals               +              ~      ovl@1c000000          2    mediatek,mt8195-disp-ovl mediatek,mt8183-disp-ovl           ?                            |                  +                                        
                   rdma@1c002000             mediatek,mt8195-disp-rdma           ?                            ~                  +                                        
                   color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           ?     0                                        +                         
        0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           ?     @                                        +                         
        @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           ?     P                                        +                         
        P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           ?     `                                        +                         
        `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         ?     p                                        +                 	        
        p          dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         ?                                             +                       *           engine digital hs           -           	dphy          	  disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            ?                                             +                         
                  dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         ?                                             +                       +           engine digital hs           -           	dphy          	  disabled          merge@1c014000            mediatek,mt8195-disp-merge          ?    @                                        +                         
        @          dp-intf@1c015000              mediatek,mt8195-dp-intf         ?    P                                                 ,              engine pixel pll          	  disabled          mutex@1c016000            mediatek,mt8195-disp-mutex          ?    `                                        +                         
        `            
  U      larb@1c018000             mediatek,mt8195-smi-larb            ?                    %                             (      (              apb smi gals               +                    larb@1c019000             mediatek,mt8195-smi-larb            ?                    %              s              (                     apb smi gals               +              u      syscon@1c100000           mediatek,mt8195-vdosys1 syscon          ?                                      
                                              #      smi@1c01b000              mediatek,mt8195-smi-common-vdo          ?                           %      &      )      $        apb smi gals0 gals1            +                    iommu@1c01f000            mediatek,mt8195-iommu-vdo           ?                  8  6                                                                                        '        bclk               +                    mutex@1c101000            mediatek,mt8195-disp-mutex          ?                    vdo1_mutex                                  +              #           vdo1_mutex          
                    
        larb@1c102000             mediatek,mt8195-smi-larb            ?                     %                         #       #       #           apb smi gals               +                    larb@1c103000             mediatek,mt8195-smi-larb            ?    0                %              s           #      #                  apb smi gals               +              v      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           ?    @                                        #              +                 @        
        @                     dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           ?    P                                        #              +              r   `        
        P                     dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           ?    `                                        #              +                 A        
        `                     dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           ?    p                                        #              +              r   a        
        p                     dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           ?                                            #              +                 B        
                             dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           ?                                            #              +              r   b        
                             dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           ?                                            #              +                 C        
                             dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           ?                                            #              +              r   c        
                             vpp-merge@1c10c000            mediatek,mt8195-disp-merge          ?                                            #   	   #           merge merge_async              +           
                     R           #         vpp-merge@1c10d000            mediatek,mt8195-disp-merge          ?                                            #   
   #           merge merge_async              +           
                     R           #         vpp-merge@1c10e000            mediatek,mt8195-disp-merge          ?                                            #      #           merge merge_async              +           
                     R           #         vpp-merge@1c10f000            mediatek,mt8195-disp-merge          ?                                            #      #           merge merge_async              +           
                     R           #         vpp-merge@1c110000            mediatek,mt8195-disp-merge          ?                                             #      #           merge merge_async              +           
                      f           #         dp-intf@1c113000              mediatek,mt8195-dp-intf         ?    0                                        +              #      #   /              engine pixel pll          	  disabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  ?    @            P            p                                                              4  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  
        @            P            p                                                          h     #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *              mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             +              r   d   r   e                           (     #   3   #   4   #   5   #   6   #   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx          ?    P                 :           Fdp_calibration_data            +                                }        	  disabled          dp-tx@1c600000            mediatek,mt8195-dp-tx           ?    `                 :           Fdp_calibration_data            +                                }        	  disabled             thermal-zones      cpu0-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical             cooling-maps       map0                     0     	   
                  cpu1-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical             cooling-maps       map0                     0     	   
                  cpu2-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical             cooling-maps       map0                     0     	   
                  cpu3-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical             cooling-maps       map0                     0     	   
                  cpu4-thermal                                           trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical             cooling-maps       map0                     0                          cpu5-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical             cooling-maps       map0                     0                          cpu6-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical             cooling-maps       map0                     0                          cpu7-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical             cooling-maps       map0                     0                          vpu0-thermal                                          trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                vpu1-thermal                                       	   trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                gpu-thermal                                    
   trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                gpu1-thermal                                          trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                vdec-thermal                                          trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                img-thermal                                       trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                infra-thermal                                         trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                cam0-thermal                                          trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                cam1-thermal                                          trips      trip-alert           L                   Epassive       trip-crit                            	   Ecritical                   chosen          serial0:921600n8          firmware       optee             linaro,optee-tz         Jsmc          memory@40000000         3memory          ?    @                regulator-wifi-3v3-en             regulator-fixed         wifi_3v3_en          N         2Z         2Z                 U      C            default                       K      regulator-vsys            regulator-fixed         vsys             N                  LK@         LK@                      K      regulator-vsys-buck           regulator-fixed       
  vsys_buck            N                  LK@         LK@                      X      regulator-vcc5v0-sys              regulator-fixed         vcc5v0_sys           N                          reserved-memory                      +            Y   optee@43200000          ?    C                   )      memory@50000000           shared-dma-pool         ?    P                  )           )      memory@53000000           shared-dma-pool         ?    S       @        memory@54600000         ?    T`                   )      memory@60000000           shared-dma-pool         ?    `                  )      memory@62000000           shared-dma-pool         ?    b       @              	compatible interrupt-parent #address-cells #size-cells model chassis-type dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c0 i2c1 i2c2 i2c3 i2c4 ethernet0 serial0 serial1 spi0 spi1 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux drive-strength input-enable output-high bias-disable input-disable bias-pull-up drive-strength-microamp bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents interrupts-extended regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-compatible #iommu-cells #mbox-cells memory-region power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-0 pinctrl-names #io-channel-cells nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,tx-delay-ps mediatek,mac-wol snps,reset-gpio snps,reset-delays-us snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup role-switch-default-mode usb-role-switch vusb33-supply vbus-supply remote-endpoint bus-width max-frequency hs400-ds-delay cap-mmc-highspeed cap-mmc-hw-reset mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable vmmc-supply vqmmc-supply cap-sd-highspeed cd-gpios no-mmc sd-uhs-sdr50 sd-uhs-sdr104 usb2-lpm-disable bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN1-supply LDO_VIN3-supply label data-role op-sink-microwatt power-role try-power-role source-pdos sink-pdos mode-switch orientation-switch vcc-supply operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,scp mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path enable-active-high vin-supply regulator-boot-on no-map 