  k   8  ܀   (              H                             4    google,juniper-sku17 google,juniper mediatek,mt8183                                  +            7Google kenzo sku17 board       aliases          =/soc/i2c@11007000            B/soc/i2c@11011000            G/soc/i2c@11009000            L/soc/i2c@1100f000            Q/soc/i2c@11008000            V/soc/i2c@11016000            [/soc/i2c@11005000            `/soc/i2c@1101a000            e/soc/i2c@1101b000            j/soc/i2c@11014000            o/soc/i2c@11015000            u/soc/i2c@11017000            {/soc/ovl@14008000            /soc/ovl@14009000            /soc/ovl@1400a000            /soc/rdma@1400b000           /soc/rdma@1400c000           /soc/serial@11002000             /soc/mmc@11230000            /soc/mmc@11240000         opp-table-cluster0            operating-points-v2                           opp0-793000000               /D8@          	                  opp0-910000000               6=          
}                  opp0-1014000000              <pi          
                  opp0-1131000000              Ci                            opp0-1248000000              Jb           5                   opp0-1326000000              O	'          ~>                  opp0-1417000000              Tu@          P                  opp0-1508000000              YA           A            	      opp0-1586000000              ^p          6            
      opp0-1625000000              `ۈ@          
                  opp0-1677000000              c@          5                  opp0-1716000000              fH           f                  opp0-1781000000              j'@                            opp0-1846000000              n          B@                  opp0-1924000000              r                             opp0-1989000000              v@                               opp-table-cluster1            operating-points-v2                       $   opp1-793000000               /D8@          
`                  opp1-910000000               6=                            opp1-1014000000              <pi          q                  opp1-1131000000              Ci          X                  opp1-1248000000              Jb           5                   opp1-1326000000              O	'                            opp1-1417000000              Tu@          P                  opp1-1508000000              YA           Y            	      opp1-1586000000              ^p                      
      opp1-1625000000              `ۈ@          t                  opp1-1677000000              c@          5                  opp1-1716000000              fH           ~                  opp1-1781000000              j'@                            opp1-1846000000              n          B@                  opp1-1924000000              r                             opp1-1989000000              v@                               opp-table-cci             operating-points-v2                          opp-273000000                E@          	                  opp-338000000                %x          
}                  opp-403000000                J          
                  opp-463000000                                            opp-546000000                 L          5                   opp-624000000                %1|           ~>                  opp-689000000                )N@          P                  opp-767000000                -}          A            	      opp-845000000                2]@          6            
      opp-871000000                3g          
                  opp-923000000                7          5                  opp-962000000                9V          f                  opp-1027000000               =6                            opp-1092000000               A           B@                  opp-1144000000               D0                             opp-1196000000               GI                                cci           mediatek,mt8183-cci                               cci intermediate                                       "      cpus                         +       cpu-map    cluster0       core0                    core1                    core2                    core3                       cluster1       core0                    core1                    core2                    core3                          cpu@0           cpu           arm,cortex-a53          '            +psci            9          L                                     cpu intermediate                         \   T        v              @                                 @                      !                      "                             cpu@1           cpu           arm,cortex-a53          '           +psci            9          L                                     cpu intermediate                         \   T        v              @                                 @                      !                      "                             cpu@2           cpu           arm,cortex-a53          '           +psci            9          L                                     cpu intermediate                         \   T        v              @                                 @                      !                      "                             cpu@3           cpu           arm,cortex-a53          '           +psci            9          L                                     cpu intermediate                         \   T        v              @                                 @                      !                      "                             cpu@100         cpu           arm,cortex-a73          '           +psci            9           L      #                              cpu intermediate                $        \           v              @                                 @                      %                      "           &                  cpu@101         cpu           arm,cortex-a73          '          +psci            9           L      #                              cpu intermediate                $        \           v              @                                 @                      %                      "           &                  cpu@102         cpu           arm,cortex-a73          '          +psci            9           L      #                              cpu intermediate                $        \           v              @                                 @                      %                      "           &                  cpu@103         cpu           arm,cortex-a73          '          +psci            9           L      #                              cpu intermediate                $        \           v              @                                 @                      %                      "           &                  idle-states         psci       cpu-sleep             arm,idle-state                             0           A           Q                     cluster-sleep-0           arm,idle-state                            0           A          Q                    cluster-sleep-1           arm,idle-state                            0           A          Q              #         l2-cache0             cache           b           x              @                    n            !      l2-cache1             cache           b           x              @                    n            %         opp-table-0           operating-points-v2                       z   opp-300000000                           	h      opp-320000000                           	      opp-340000000                C           	<      opp-360000000                u*           	Ҧ      opp-380000000                W           	      opp-400000000                ׄ           
z      opp-420000000                           
      opp-460000000                k           
L      opp-500000000                e           
}      opp-540000000                 /           
`      opp-580000000                "           
4      opp-620000000                $s                 opp-653000000                &@          YF      opp-698000000                )                opp-743000000                ,IG                opp-800000000                /                    pmu-a53           arm,cortex-a53-pmu              '        |            (      pmu-a73           arm,cortex-a73-pmu              '        |            )      psci              arm,psci-1.0            2smc       fixed-factor-clock-13m            fixed-factor-clock                          *                              clk13m              ;      oscillator            fixed-clock                             clk26m              *      timer             arm,armv8-timer             '      @  |                                             
             soc                      +             simple-bus              efuse@8000000         %    mediatek,mt8183-efuse mediatek,efuse            '                                   +           okay          interrupt-controller@c000000              arm,gic-v3                         '               P  '                                @              A             B                  |      	                             '   ppi-partitions     interrupt-partition-0                                    (      interrupt-partition-1                                    )            syscon@c530000            mediatek,mt8183-mcucfg syscon           '    S                                      interrupt-controller@c530a80          .    mediatek,mt8183-sysirq mediatek,mt6577-sysirq                                   '        '    S
       P                  cpu-debug@d410000         &    arm,coresight-cpu-debug arm,primecell           '    A                     +   .      	   apb_pclk                     cpu-debug@d510000         &    arm,coresight-cpu-debug arm,primecell           '    Q                     +   .      	   apb_pclk                     cpu-debug@d610000         &    arm,coresight-cpu-debug arm,primecell           '    a                     +   .      	   apb_pclk                     cpu-debug@d710000         &    arm,coresight-cpu-debug arm,primecell           '    q                     +   .      	   apb_pclk                     cpu-debug@d810000         &    arm,coresight-cpu-debug arm,primecell           '                         +   .      	   apb_pclk                     cpu-debug@d910000         &    arm,coresight-cpu-debug arm,primecell           '                         +   .      	   apb_pclk                     cpu-debug@da10000         &    arm,coresight-cpu-debug arm,primecell           '                         +   .      	   apb_pclk                     cpu-debug@db10000         &    arm,coresight-cpu-debug arm,primecell           '                         +   .      	   apb_pclk                     syscon@10000000            mediatek,mt8183-topckgen syscon         '                                           syscon@10001000            mediatek,mt8183-infracfg syscon         '                                )               +      syscon@10003000           mediatek,mt8183-pericfg syscon          '     0                               k      pinctrl@10005000              mediatek,mt8183-pinctrl         '     P                                                                                                                                   D  6iocfg0 iocfg1 iocfg2 iocfg3 iocfg4 iocfg5 iocfg6 iocfg7 iocfg8 eint          @        P           \   ,                            |                            hSPI_AP_EC_CS_L SPI_AP_EC_MOSI SPI_AP_EC_CLK I2S3_DO USB_PD_INT_ODL     IT6505_HPD_L I2S3_TDM_D3 SOC_I2C6_1V8_SCL SOC_I2C6_1V8_SDA DPI_D0 DPI_D1 DPI_D2 DPI_D3 DPI_D4 DPI_D5 DPI_D6 DPI_D7 DPI_D8 DPI_D9 DPI_D10 DPI_D11 DPI_HSYNC DPI_VSYNC DPI_DE DPI_CK AP_MSDC1_CLK AP_MSDC1_DAT3 AP_MSDC1_CMD AP_MSDC1_DAT0 AP_MSDC1_DAT2 AP_MSDC1_DAT1       OTG_EN DRVBUS DISP_PWM DSI_TE LCM_RST_1V8 AP_CTS_WIFI_RTS AP_RTS_WIFI_CTS SOC_I2C5_1V8_SCL SOC_I2C5_1V8_SDA SOC_I2C3_1V8_SCL SOC_I2C3_1V8_SDA                              SOC_I2C1_1V8_SDA SOC_I2C0_1V8_SDA SOC_I2C0_1V8_SCL SOC_I2C1_1V8_SCL AP_SPI_H1_MISO AP_SPI_H1_CS_L AP_SPI_H1_MOSI AP_SPI_H1_CLK I2S5_BCK I2S5_LRCK I2S5_DO BOOTBLOCK_EN_L MT8183_KPCOL0 SPI_AP_EC_MISO UART_DBG_TX_AP_RX UART_AP_TX_DBG_RX I2S2_MCK I2S2_BCK CLK_5M_WCAM CLK_2M_UCAM I2S2_LRCK I2S2_DI SOC_I2C2_1V8_SCL SOC_I2C2_1V8_SDA SOC_I2C4_1V8_SCL SOC_I2C4_1V8_SDA  SCL8 SDA8 FCAM_PWDN_L                          I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC I2S_PMIC       AP_FLASH_WP_L EC_AP_INT_ODL IT6505_INT_ODL H1_INT_OD_L        AP_SPI_FLASH_MISO AP_SPI_FLASH_CS_L AP_SPI_FLASH_MOSI AP_SPI_FLASH_CLK DA7219_IRQ                                        ,   audiopins                  pins-bus          D  x  a  b  e  f    Y  Z  [                           audiotdmouton                  pins-bus            x            
                    audiotdmoutoff                 pins-bus            x                 
                                       bt-pins             F   pins-bt-en          x  x                   ec-ap-int-odl               c   pins1           x                              h1-int-od-l             X   pins1           x                     i2c0                I   pins-bus            x  R  S                                i2c1                a   pins-bus            x  Q  T                                i2c2                U   pins-bus            x  g  h                              i2c3                _   pins-bus            x  2  3                                i2c4                K   pins-bus            x  i  j                              i2c5                e   pins-bus            x  0  1                                i2c6                H   pins-bus            x                      mmc0-pins-default               o   pins-cmd-dat          $  x  {    }    ~        z                                     pins-clk            x  |                       
      pins-rst            x                                  mmc0-pins-uhs               p   pins-cmd-dat          $  x  {    }    ~        z                                     pins-clk            x  |                       
      pins-ds         x                         
      pins-rst            x                                 mmc1-pins-default               s   pins-cmd-dat            x       "  !                      
      pins-clk            x                       
         mmc1-pins-uhs               t   pins-cmd-dat            x       "  !                                 
      pins-clk            x                         
                  panel-pins-default     panel-reset         x  -                            pwm0-pin-default                ^   pins1           x                           pins2           x  +         scp             :   pins-scp-uart           x  n  p         spi0                W   pins-spi            x  U  V   W  X                  spi1                `   pins-spi            x                          spi2                b   pins-spi            x                      pins-spi-mi         x  ^                      spi3                d   pins-spi            x                          spi4                g   pins-spi            x                          spi5                h   pins-spi            x                          uart0-pins-default              C   pins-rx         x  _                        pins-tx         x  `         uart1-pins-default              D   pins-rx         x  y                        pins-tx         x  s      pins-rts            x  /      pins-cts            x  .                  uart1-pins-sleep                E   pins-rx         x  y                         pins-tx         x  s      pins-rts            x  /      pins-cts            x  .                  wifi-pins-pwrseq                   pins-wifi-enable            x  w                   wifi-pins-wakeup                   pins-wifi-wakeup            x  q                   pp1200-mipibrdg-en                 pins1           x  6                   pp1800-lcd-en                  pins1           x  $                   pp3300-panel-pins                  panel-3v3-enable            x  #                   ppvarp-lcd-en      pins1           x  B                   ppvarn-lcd-en      pins1           x                     anx7625-pins                L   pins1           x  -   I                pins2           x                              touchscreen-pins                J   touch-int-odl           x                           touch-rst-l         x                     trackpad-pins               V   trackpad-int            x                              vddio-mipibrdg-en                  pins1           x  %                   volume-button-pins                 voldn-btn-odl           x                           volup-btn-odl           x                              ts3a227e_pins               f   pins1           x                                 syscon@10006000       )    mediatek,mt8183-scpsys syscon simple-mfd            '     `           power-controller          !    mediatek,mt8183-power-controller                         +            #               ]   power-domain@0          '                      +   /   +   7         audio audio1 audio2         #          power-domain@1          '           7   +        #          power-domain@2          '                           mfg                      +            #           I   -   power-domain@3          '                        +            #           I   .   power-domain@4          '           #          power-domain@5          '           #          power-domain@6          '           7   +        #                power-domain@7          '         X            /       /      /      /      /      /      /      /      /      /   	      5   mm mm-0 mm-1 mm-2 mm-3 mm-4 mm-5 mm-6 mm-7 mm-8 mm-9            7   +        W   0                     +            #      power-domain@8          '         @            1       1   	   1      1      1      1      1         .   cam cam-0 cam-1 cam-2 cam-3 cam-4 cam-5 cam-6           7   +        W   0        #          power-domain@9          '   	               "   2   	   2            isp isp-0 isp-1         7   +        W   0        #          power-domain@10         '   
        W   0        #          power-domain@11         '           W   0        #          power-domain@12         '         @         &      #   3       3      3      3      3      3         -   vpu vpu1 vpu-0 vpu-1 vpu-2 vpu-3 vpu-4 vpu-5            7   +        W   0                     +            #      power-domain@13         '                  $         vpu2            7   +        #          power-domain@14         '                  %         vpu3            7   +        #                      watchdog@10007000             mediatek,mt8183-wdt         '     p                )               m      syscon@1000c000       "    mediatek,mt8183-apmixedsys syscon           '                                    Z      pwrap@1000d000            mediatek,mt8183-pwrap           '                     6pwrap           |                         )   +         	   spi wrap       pmic              mediatek,mt6358                             d   ,         mt6358codec           mediatek,mt6358-sound           x               4      mt6358regulator           mediatek,mt6358-regulator              5           5           5           5           5           5            5           5        #   5        7   5        K   5        [   5        k   6        {   7           8           8           8   buck_vdram1         vdram1                     L          0                     +        ?                   7      buck_vcore          vcore                                j                    +        ?             buck_vpa            vpa                    7          P                   ?             buck_vproc11            vproc11                              j                    +        ?                   &      buck_vproc12            vproc12                              j                    +        ?                         buck_vgpu           vgpu                                 j                   ?               W   -        n             .      buck_vs2            vs2                    L          0                     +            8      buck_vmodem         vmodem                               j                   +        ?             buck_vs1            vs1          B@         '{l          0                     +            6      ldo_vdram2          vdram2           	'         w@                   +      ldo_vsim1           vsim1            )2         )2                ldo_vibr            vibr             O         2Z           <      ldo_vrf12           vrf12            O         O           x      ldo_vio18           vio18            w@         w@          
         +            r      ldo_vusb            vusb             -         /M`                   +            l      ldo_vcamio          vcamio           w@         w@          E      ldo_vcamd           vcamd                     w@          E      ldo_vcn18           vcn18            w@         w@                ldo_vfe28           vfe28            *         *                ldo_vsram_proc11            vsram_proc11                                 j                    +      ldo_vcn28           vcn28            *         *                ldo_vsram_others            vsram_others                                 j                    +      ldo_vsram_gpu         
  vsram_gpu            P         B@          j                   W   .        n             -      ldo_vxo22           vxo22            !         !           x         +      ldo_vefuse          vefuse                                    ldo_vaux18          vaux18           w@         w@                ldo_vmch            vmch             ,@          2Z           <      ldo_vbif28          vbif28           *         *                ldo_vsram_proc12            vsram_proc12                                 j                    +      ldo_vcama1          vcama1           w@         -          E      ldo_vemc            vemc             ,@          2Z           <            q      ldo_vio28           vio28            *         *                ldo_va12            va12             O         O                   +      ldo_vrf18           vrf18            w@         w@           x      ldo_vcn33           vcn33            2Z         5g                ldo_vcama2          vcama2           w@         -          E      ldo_vmc         vmc          w@         2Z           <      ldo_vldo28          vldo28           *         -                ldo_vaud28          vaud28           *         *                      4      ldo_vsim2           vsim2            )2         )2                   rtc           mediatek,mt6358-rtc       keys              mediatek,mt6358-keys       power              t               home               f               keyboard@10010000             mediatek,mt6779-keypad          '                     |                      *         kpd       	  disabled          scp@10500000              mediatek,mt8183-scp          '    P             \             	  6sram cfg            |                      +            main               9        okay            mediatek/mt8183/scp.img         default            :               cros-ec-rpmsg             google,cros-ec-rpmsg            cros-ec-rpmsg            timer@10017000        ,    mediatek,mt8183-timer mediatek,mt6765-timer         '    p                |                      ;      iommu@10205000            mediatek,mt8183-m4u         '     P                |                     <   =   >   ?   @   A   B                       |      mailbox@10238000              mediatek,mt8183-gce         '    #       @         |                                 +            gce             {      auxadc@11001000       .    mediatek,mt8183-auxadc mediatek,mt8173-auxadc           '                         +   #         main                       okay                Y      serial@11002000       *    mediatek,mt8183-uart mediatek,mt6577-uart           '                      |       [               *   +         	   baud bus            okay            default            C      serial@11003000       *    mediatek,mt8183-uart mediatek,mt6577-uart           '     0                    *   +         	   baud bus            okay            default sleep              D        *   E        d          \      ,   y      bluetooth           default            F        okay              qcom,qca6174-bt         4   ,   x                G        nvm_00440302_i2s.bin             serial@11004000       *    mediatek,mt8183-uart mediatek,mt6577-uart           '     @                |       ]               *   +         	   baud bus          	  disabled          i2c@11005000              mediatek,mt8183-i2c          '     P                             |       W               +   W   +   *      	   main dma                                    +            okay            default            H               i2c@11007000              mediatek,mt8183-i2c          '     p                             |       Q               +   
   +   *      	   main dma                                    +            okay            default            I            touchscreen@10            elan,ekth3500           '           default            J        d   ,              A   ,               i2c@11008000              mediatek,mt8183-i2c          '                                  |       R               +      +   *   +   G         main dma arb                                    +            okay            default            K            anx7625@58            analogix,anx7625            '   X        default            L        4   ,   -            A   ,   I            M   M        Z   N        g   O   ports                        +       port@0          '       endpoint            t   P            ~         port@1          '      endpoint            t   Q            T            aux-bus    panel         
    edp-panel              R           S   port       endpoint            t   T            Q                     i2c@11009000              mediatek,mt8183-i2c          '                                 |       S               +      +   *   +   I         main dma arb                                    +            okay            default            U            trackpad@15           elan,ekth3000           '           default            V        d   ,                     trackpad@2c           hid-over-i2c            '   ,                    default            V        d   ,                        spi@1100a000              mediatek,mt8183-spi                      +            '                     |       x                  6         +            parent-clk sel-clk spi-clk          okay            default            W                       ,   V      tpm@0             google,cr50         '             B@        default            X        d   ,               thermal@1100b000                         mediatek,mt8183-thermal         '                         +   	   +   #         therm auxadc               +            |       L              Y           Z           [        &calibration-data                      svs@1100bc00              mediatek,mt8183-svs         '                     |                      +   	         main               \   [      (  &svs-calibration-data t-calibration-data       pwm@1100e000              mediatek,mt8183-disp-pwm            '                     |                  7   ]           E                     +   5         main mm         okay            default            ^                  pwm@11006000              mediatek,mt8183-pwm         '     `                E         0      +      +      +      +      +      +            top main pwm1 pwm2 pwm3 pwm4          i2c@1100f000              mediatek,mt8183-i2c          '                                  |       T               +      +   *      	   main dma                                    +            okay            default            _               spi@11010000              mediatek,mt8183-spi                      +            '                     |       |                  6         +   8         parent-clk sel-clk spi-clk          okay            default            `               flash@0           winbond,w25q64dw jedec,spi-nor          '            }x@         i2c@11011000              mediatek,mt8183-i2c          '                                |       U               +   9   +   *      	   main dma                                    +            okay            default            a               spi@11012000              mediatek,mt8183-spi                      +            '                     |                         6         +   ;         parent-clk sel-clk spi-clk          okay            default            b               cros-ec@0             google,cros-ec-spi          '             -        d   ,              default            c            i2c-tunnel            google,cros-ec-i2c-tunnel           P                        +       sbs-battery@b             sbs,sbs-battery         '           b           v            extcon0           google,extcon-usbc-cros-ec                    typec             google,cros-ec-typec                         +       connector@0           usb-c-connector         '            dual            host            sink             keyboard-controller           google,cros-ec-keyb                                     D    ; < = > ? @ A	 B	 C  D  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	  + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      pwm           google,cros-ec-pwm          E         	  disabled                spi@11013000              mediatek,mt8183-spi                      +            '    0                |                         6         +   <         parent-clk sel-clk spi-clk        	  disabled            default            d                  i2c@11014000              mediatek,mt8183-i2c          '    @                            |                      +   H   +   *   +   G         main dma arb                                    +          	  disabled          i2c@11015000              mediatek,mt8183-i2c          '    P                             |                      +   J   +   *   +   I         main dma arb                                    +          	  disabled          i2c@11016000              mediatek,mt8183-i2c          '    `                             |       V               +   D   +   *   +   E         main dma arb                                    +            okay            default            e            ts3a227e@3b         default            f          ti,ts3a227e         '   ;        d   ,              okay                         i2c@11017000              mediatek,mt8183-i2c          '    p                            |                      +   F   +   *   +   E         main dma arb                                    +          	  disabled          spi@11018000              mediatek,mt8183-spi                      +            '                    |                         6         +   K         parent-clk sel-clk spi-clk        	  disabled            default            g                  spi@11019000              mediatek,mt8183-spi                      +            '                    |                         6         +   L         parent-clk sel-clk spi-clk        	  disabled            default            h                  i2c@1101a000              mediatek,mt8183-i2c          '                                |       X               +   b   +   *      	   main dma                                    +          	  disabled          i2c@1101b000              mediatek,mt8183-i2c          '                                 |       Y               +   c   +   *      	   main dma                                    +          	  disabled          usb@11201000          #    mediatek,mt8183-mtu3 mediatek,mtu3           '            .      >              	  6mac ippc            |       H           	   i      j               +   =   +   Z         sys_ck ref_ck           	   k      e                     +                    okay            	(host                     	0   l   usb@11200000          '    mediatek,mt8183-xhci mediatek,mtk-xhci          '                      6mac         |       I               +   =   +   Z         sys_ck ref_ck           okay                         +            	0   l   hub@1             usb5e3,610          '               audio-controller@11220000              mediatek,mt8183-audiosys syscon         '    "                                n   mt8183-afe-pcm            mediatek,mt8183-audio           |                     m         	  	>audiosys            7   ]         D      n      n      n      n      n      n      n      n      n      n      n      n   
   n   	   n      n       +   /   +   7                  0            H            L            K            O      t      u      v      w      x      y      z      {      |      }      ~         *     w   aud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adc_adda6_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_i2s1_bclk_sw aud_i2s2_bclk_sw aud_i2s3_bclk_sw aud_i2s4_bclk_sw aud_tdm_clk aud_tml_clk aud_infra_clk mtkaif_26m_clk top_mux_audio top_mux_aud_intbus top_syspll_d2_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d8 top_mux_aud_eng2 top_apll2_d8 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_clk26m_clk                       mmc@11230000              mediatek,mt8183-mmc          '    #                              |       M                     +      +            source hclk source_cg           okay            default state_uhs              o        *   p        	J                     	T         	f         	u         	         	         	        	 (        	   q        	   r        	              	      U         	      mmc@11240000              mediatek,mt8183-mmc          '    $                              |       N                  	   +      +   (         source hclk source_cg           okay            default state_uhs              s        *   t        	   u        	   v        
    w        	J                     
         
         
)         
7                  
M         	         
Z         	        	      	        	      V                     +       qca-wifi@1            qcom,ath10k         '           
aGO_JUNIPER           dsi-phy@11e50000              mediatek,mt8183-mipi-tx         '                         Z                       
            mipi_tx0_pll               x        &calibration-data            okay                }      efuse@11f10000        %    mediatek,mt8183-efuse mediatek,efuse            '                                  +      socinfo-data1@4c            '   L         socinfo-data2@60            '   `         calib@180           '                 [      calib@190           '                 x      calib@580           '     d            \         t-phy@11f40000        .    mediatek,mt8183-tphy mediatek,generic-tphy-v2                        +                                okay       usb-phy@0           '                   *         ref         
           
           okay                i      usb-phy@700         '     	             *         ref         
           okay                j         syscon@13000000           mediatek,mt8183-mfgcfg syscon           '                                 7   ]               y      gpu@13040000          '    mediatek,mt8183b-mali arm,mali-bifrost          '            @       $  |                                   
job mmu gpu             y            7   ]      ]      ]           
core0 core1 core2               z        
   .      syscon@14000000           mediatek,mt8183-mmsys syscon            '                                 )           
   {          {              
   {                      /      dma-controller0@14001000              mediatek,mt8183-mdp3-rdma           '                     
   {                 
              7   ]               /      /           
   |            
   {              {                            mdp3-rsz0@14003000            mediatek,mt8183-mdp3-rsz            '     0                
   {     0            
                  /         mdp3-rsz1@14004000            mediatek,mt8183-mdp3-rsz            '     @                
   {     @            
                  /         dma-controller@14005000           mediatek,mt8183-mdp3-wrot           '     P                
   {     P            
      !        7   ]               /           
   |                    mdp3-wdma@14006000            mediatek,mt8183-mdp3-wdma           '     `                
   {     `            
      "        7   ]               /   )        
   |         ovl@14008000              mediatek,mt8183-disp-ovl            '                     |                  7   ]               /           
   |            
   {               ovl@14009000              mediatek,mt8183-disp-ovl-2l         '                     |                  7   ]               /           
   |           
   {               ovl@1400a000              mediatek,mt8183-disp-ovl-2l         '                     |                  7   ]               /           
   |           
   {               rdma@1400b000             mediatek,mt8183-disp-rdma           '                     |                  7   ]               /           
   |                      
   {               rdma@1400c000             mediatek,mt8183-disp-rdma           '                     |                  7   ]               /           
   |                      
   {               color@1400e000        6    mediatek,mt8183-disp-color mediatek,mt8173-disp-color           '                     |                  7   ]               /           
   {               ccorr@1400f000            mediatek,mt8183-disp-ccorr          '                     |                  7   ]               /           
   {               aal@14010000              mediatek,mt8183-disp-aal            '                     |                  7   ]               /           
   {                gamma@14011000            mediatek,mt8183-disp-gamma          '                    |                  7   ]               /           
   {               dither@14012000           mediatek,mt8183-disp-dither         '                     |                  7   ]               /           
   {                dsi@14014000              mediatek,mt8183-dsi         '    @                |                  7   ]               /      /       }         engine digital hs              /           	   }        (dphy            okay       ports      port       endpoint            t   ~            P               mutex@14016000            mediatek,mt8183-disp-mutex          '    `                |                  7   ]           
              
   {     `          larb@14017000             mediatek,mt8183-smi-larb            '    p                W   0            /      /           7   ]            apb smi             <      smi@14019000              mediatek,mt8183-smi-common          '                         /       /       /      /            apb smi gals0 gals1         7   ]               0      mdp3-ccorr@1401c000           mediatek,mt8183-mdp3-ccorr          '                    
   {                 
      1            /   +      syscon@15020000           mediatek,mt8183-imgsys syscon           '                                    2      larb@15021000             mediatek,mt8183-smi-larb            '                    W   0            2   	   2   	   /            apb smi gals            7   ]   	            A      larb@1502f000             mediatek,mt8183-smi-larb            '                    W   0            2      2      /   	         apb smi gals            7   ]   	            >      syscon@16000000           mediatek,mt8183-vdecsys syscon          '                                           video-codec@16020000              mediatek,mt8183-vcodec-dec          '                                                      0            @            P            h            p            x                          (  6misc ld top cm ad av pp hwd hwq hwb hwg         |                8  
   |       |   !   |   "   |   #   |   $   |   %   |   &        2           ?           7   ]   
                         vdec          larb@16010000             mediatek,mt8183-smi-larb            '                     W   0                               apb smi         7   ]   
            =      syscon@17000000           mediatek,mt8183-vencsys syscon          '                                           larb@17010000             mediatek,mt8183-smi-larb            '                     W   0                                apb smi         7   ]               @      jpeg-encoder@17030000         +    mediatek,mt8183-jpgenc mediatek,mtk-jpgenc          '                     |                  
   |      |           7   ]                           jpgenc        syscon@19000000            mediatek,mt8183-ipu_conn syscon         '                                     3      syscon@19010000           mediatek,mt8183-ipu_adl syscon          '                              syscon@19180000       !    mediatek,mt8183-ipu_core0 syscon            '                              syscon@19280000       !    mediatek,mt8183-ipu_core1 syscon            '    (                          syscon@1a000000           mediatek,mt8183-camsys syscon           '                                     1      larb@1a001000             mediatek,mt8183-smi-larb            '                     W   0            1       1       /            apb smi gals            7   ]               B      larb@1a002000             mediatek,mt8183-smi-larb            '                      W   0            1   	   1   	   /            apb smi gals            7   ]               ?         thermal-zones      cpu-thermal         P   d        f          t                    trips      trip-point0          	                  "passive       trip-point1          8                  "passive                   cpu-crit             8                	  "critical             cooling-maps       map0                     0                               map1                     0                                     tzts1           P            f            t                   trips         cooling-maps             tzts2           P            f            t                   trips         cooling-maps             tzts3           P            f            t                   trips         cooling-maps             tzts4           P            f            t                   trips         cooling-maps             tzts5           P            f            t                   trips         cooling-maps             tztsABB         P            f            t                   trips         cooling-maps             tboard1         f          P            t         tboard2         f          P            t            chosen          serial0:115200n8          backlight_lcd0            pwm-backlight                                       4   ,                                         @        okay                S      memory@40000000         memory          '    @                oscillator1           fixed-clock                                clk32k              G      regulator0            regulator-fixed         it6505_pp18          w@         w@        !   ,                &      regulator1            regulator-fixed         lcd_pp3300           2Z         2Z         +         9      regulator2            regulator-fixed       
  bl_pp5000            LK@         LK@         +         9                  regulator3            regulator-fixed         mmc1_power           2Z         2Z            u      regulator4            regulator-fixed         mmc1_io          w@         w@            v      regulator5            regulator-fixed         pp1800_alw           +         9         w@         w@      regulator6            regulator-fixed         pp3300_alw           +         9         2Z         2Z      regulator-vsys            regulator-fixed         vsys             +         9            5      reserved-memory                      +               memory@50000000           shared-dma-pool         '    P                  K            9         mt8183-sound            R         '  default aud_tdm_out_on aud_tdm_out_off                     *           d           okay            n         (    mediatek,mt8183_mt6358_ts3a227_max98357       bt-sco            linux,bt-sco          wifi-pwrseq           mmc-pwrseq-simple           default                    A   ,   w               w      wifi-wakeup       
    gpio-keys           default               event-wowlan            Wake on WiFi            ;   ,   q                                 thermal-sensor1           generic-adc-thermal                        Y            sensor-channel          x              '  .  :    N   l  a    u0      7  @      {  P  (      `      a p  / $   8    L    _    s       y (   h    Z 8   N    C H   ;                  thermal-sensor2           generic-adc-thermal                        Y           sensor-channel          x              '  .  :    N   l  a    u0      7  @      {  P  (      `      a p  / $   8    L    _    s       y (   h    Z 8   N    C H   ;                  pp1200-mipibrdg           regulator-fixed         pp1200_mipibrdg         default                     &         9        !   ,   6                M      pp1800-mipibrdg           regulator-fixed         pp1800_mipibrdg         default                     &         9        !   ,   $                N      pp3300-panel              regulator-fixed         pp3300_panel             2Z         2Z        default                     &         9        !   ,   #                R      vddio-mipibrdg            regulator-fixed         vddio_mipibrdg          default                     &         9        !   ,   %                O      volume-buttons        
    gpio-keys           default               button-volume-down          Volume Down            r           d        ;   ,            button-volume-up          
  Volume Up              s           d        ;   ,               max98357a             maxim,max98357a            ,                	compatible interrupt-parent #address-cells #size-cells model i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 i2c7 i2c8 i2c9 i2c10 i2c11 ovl0 ovl-2l0 ovl-2l1 rdma0 rdma1 serial0 mmc0 mmc1 opp-shared phandle opp-hz opp-microvolt required-opps clocks clock-names operating-points-v2 proc-supply cpu device_type reg enable-method capacity-dmips-mhz cpu-idle-states dynamic-power-coefficient i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells mediatek,cci entry-method local-timer-stop arm,psci-suspend-param entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts #clock-cells clock-div clock-mult clock-output-names clock-frequency ranges status #interrupt-cells interrupt-controller mediatek,broken-save-restore-fw affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux drive-strength input-enable bias-pull-down output-low bias-pull-up mediatek,pull-up-adv mediatek,drive-strength-adv bias-disable mediatek,pull-down-adv output-high #power-domain-cells mediatek,infracfg domain-supply mediatek,smi interrupts-extended mediatek,dmic-mode Avdd-supply vsys-ldo1-supply vsys-ldo2-supply vsys-ldo3-supply vsys-vcore-supply vsys-vdram1-supply vsys-vgpu-supply vsys-vmodem-supply vsys-vpa-supply vsys-vproc11-supply vsys-vproc12-supply vsys-vs1-supply vsys-vs2-supply vs1-ldo1-supply vs2-ldo1-supply vs2-ldo2-supply vs2-ldo3-supply vs2-ldo4-supply regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-enable-ramp-delay regulator-always-on regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread linux,keycodes wakeup-source memory-region firmware-name pinctrl-names pinctrl-0 mediatek,rpmsg-name mediatek,larbs #iommu-cells #mbox-cells #io-channel-cells pinctrl-1 enable-gpios reset-gpios vdd10-supply vdd18-supply vdd33-supply remote-endpoint power-supply backlight hid-descr-addr mediatek,pad-select cs-gpios spi-max-frequency #thermal-sensor-cells resets mediatek,auxadc mediatek,apmixedsys nvmem-cells nvmem-cell-names power-domains #pwm-cells google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count google,usb-port-id power-role data-role try-power-role keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap phys mediatek,syscon-wakeup dr_mode vusb33-supply reset-names bus-width cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply assigned-clocks assigned-clock-parents non-removable mmc-pwrseq cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 keep-power-in-suspend cap-sdio-irq no-mmc qcom,ath10k-calibration-variant #phy-cells mediatek,discth interrupt-names power-domain-names mali-supply mboxes mediatek,gce-client-reg mediatek,gce-events iommus #dma-cells mediatek,rdma-fifo-size phy-names mediatek,scp mediatek,vdecsys polling-delay-passive polling-delay thermal-sensors sustainable-power temperature hysteresis trip cooling-device contribution stdout-path pwms brightness-levels num-interpolated-steps default-brightness-level gpio enable-active-high regulator-boot-on no-map mediatek,platform pinctrl-2 mediatek,headset-codec label linux,code io-channels io-channel-names temperature-lookup-table debounce-interval sdmode-gpios 