     8     (                                               nvidia,p2571 nvidia,tegra210                                     +         '   7NVIDIA Tegra210 P2571 reference design     opp-table-dvfs0           operating-points-v2          =      opp-40800000-800             E 5  5  0         S    n          Z         opp-68000000-800             E 5  5  0         S              Z         opp-102000000-800            E 5  5  0         S    e         Z         opp-204000000-800            E 5  5  0         S    (          Z             k      opp-408000000-812            E c c 0         S    Q          Z         opp-665600000-825            E   0         S    '@          Z         opp-800000000-825            E   0         S    /          Z         opp-1065600000-837           E ň ň 0         S    ?          Z         opp-1331200000-850           E P P 0         S    OX          Z         opp-1600000000-887           E   0         S    _^          Z            opp-table-dvfs1           operating-points-v2          =      opp-40800000             S    n          Z            w 	       opp-68000000             S              Z            w        opp-102000000            S    e         Z            w        opp-204000000            S    (          Z            w 1           k      opp-408000000            S    Q          Z            w c       opp-665600000            S    '@          Z            w        opp-800000000            S    /          Z            w P       opp-1065600000           S    ?          Z            w(       opp-1331200000           S    OX          Z            wE        opp-1600000000           S    _^          Z            w          pcie@1003000              nvidia,tegra210-pcie             pci       0        0             8                               pads afi cs                 b          c         	   intr msi                                                                             b                                        +                                                                                                           B                                           F      H          ,        pex afi pll_e cml                 F      H      J        pex afi pcie_x          #default idle            1           ;         	  Edisabled       pci@1,0          pci         L                                                                  	  Edisabled                         +                     _         pci@2,0          pci         L                                                                 	  Edisabled                         +                     _            host1x@50000000           nvidia,tegra210-host1x               P        @                 A          C            syncpt host1x                          host1x                            
  host1x mc                        +                T       T                  p         dpaux@54040000            nvidia,tegra210-dpaux                T                                                /        dpaux parent                          dpaux           w         	  Edisabled       pinmux-aux        	  dpaux-io            aux          =         pinmux-i2c        	  dpaux-io            i2c          =         pinmux-off        	  dpaux-io            off          =         i2c-bus                      +             vi@54080000           nvidia,tegra210-vi               T                         E         	  Edisabled                               4                       w                        +                    T         csi@838           nvidia,tegra210-csi            8         	  Edisabled                                    G                                  eee9       (         4                       G        csi cilab cilcd cile csi_tpg            w            tsec@54100000             nvidia,tegra210-tsec                 T                         2                  S              S      	  Edisabled          dc@54200000           nvidia,tegra210-dc               T                          I                          dc                        dc          p                 	   
                        dc@54240000           nvidia,tegra210-dc               T$                         J                          dc                        dc          p                 	   
                       dsi@54300000              nvidia,tegra210-dsi              T0                        0                    dsi lp parent                 0        dsi         w                       	  Edisabled                         +             =   	      vic@54340000              nvidia,tegra210-vic              T4                         H                          vic                       vic         p              w         nvjpg@54380000            nvidia,tegra210-nvjpg                T8                                nvjpg                         nvjpg           p              w         dsi@54400000              nvidia,tegra210-dsi              T@                        R                    dsi lp parent                 R        dsi         w                       	  Edisabled                         +             =   
      nvdec@54480000            nvidia,tegra210-nvdec                TH                                nvdec                         nvdec           p              w         nvenc@544c0000            nvidia,tegra210-nvenc                TL                                nvenc                         nvenc           p              w         tsec@54500000             nvidia,tegra210-tsec                 TP                         P                          tsec                          tsec          	  Edisabled          sor@54540000              nvidia,tegra210-sor              TT                         L         (                         /              sor out parent dp safe                        sor         1           ;                      #aux i2c off         w         	  Edisabled             =         sor@54580000              nvidia,tegra210-sor1                 TX                         K         (                         /              sor out parent dp safe                        sor         1           ;                      #aux i2c off         w         	  Edisabled             =         dpaux@545c0000            nvidia,tegra210-dpaux                T\                                                /        dpaux parent                          dpaux           w         	  Edisabled       pinmux-aux        	  dpaux-io            aux          =         pinmux-i2c        	  dpaux-io            i2c          =         pinmux-off        	  dpaux-io            off          =         i2c-bus                      +             isp@54600000              nvidia,tegra210-isp              T`                         G                                        isp       	  Edisabled          isp@54680000              nvidia,tegra210-isp              Th                         F                                        isp       	  Edisabled          i2c@546c0000              nvidia,tegra210-i2c-vi               Tl                                                 Q        div-clk slow                          i2c         w         	  Edisabled                         +             interrupt-controller@50041000             arm,gic-400                                         @       P            P              P@             P`                        	                       =         gpu@57000000              nvidia,gm20b                  W              X                                                stall nonstall                      +              gpu pwr ref                       gpu         p            	  Edisabled          interrupt-controller@60004000             nvidia,tegra210-ictlr         `       ` @        @    ` A        @    ` B        @    ` C        @    ` D        @    ` E        @                                          =         timer@60005000            nvidia,tegra210-timer                ` P                                                       )          *          y                                                                                                          timer         clock@60006000            nvidia,tegra210-car              ` `                !           .            =         flow-controller@60007000              nvidia,tegra210-flowctrl                 ` p              actmon@6000c800       .    nvidia,tegra210-actmon nvidia,tegra124-actmon                `                         -                  w      9        actmon emc                w        actmon          ;           O      '         	  ]cpu-read            p         gpio@6000d000         )    nvidia,tegra210-gpio nvidia,tegra30-gpio                 `               `                     !          "          #          7          W          Y          }                                                  dma-controller@60020000       .    nvidia,tegra210-apbdma nvidia,tegra148-apbdma                `                        h          i          j          k          l          m          n          o          p          q          r          s          t          u          v          w                                                                                                                                                                                  "        dma               "        dma                     =         apbmisc@70000800          /    nvidia,tegra210-apbmisc nvidia,tegra20-apbmisc                p         d    p               pinmux@700008d4           nvidia,tegra210-pinmux                p           p 0               #boot            1      pinmux-sdmmc1-1v8-drv            =   %   sdmmc1          drive_sdmmc1                                   pinmux-sdmmc1-3v3-drv            =   $   sdmmc1          drive_sdmmc1                                   pinmux-sdmmc2-1v8-drv            =   &   sdmmc2          drive_sdmmc2                                   pinmux-sdmmc3-1v8-drv            =   *   sdmmc3          drive_sdmmc3                                   pinmux-sdmmc3-3v3-drv            =   )   sdmmc3          drive_sdmmc3                                   pinmux-sdmmc4-1v8-drv            =   +   sdmmc4          drive_sdmmc4                                   pinmux           =      pex_l0_rst_n_pa0            pex_l0_rst_n_pa0                                                           &          pex_l0_clkreq_n_pa1         pex_l0_clkreq_n_pa1         3rsvd1                                                          &          pex_wake_n_pa2          pex_wake_n_pa2          3rsvd1                                                          &          pex_l1_rst_n_pa3            pex_l1_rst_n_pa3            3rsvd1                                                          &          pex_l1_clkreq_n_pa4         pex_l1_clkreq_n_pa4         3rsvd1                                                          &          sata_led_active_pa5         sata_led_active_pa5                                                      pa6         pa6         3rsvd1                                                        dap1_fs_pb0         dap1_fs_pb0         3rsvd1                                                        dap1_din_pb1            dap1_din_pb1            3rsvd1                                                        dap1_dout_pb2           dap1_dout_pb2           3rsvd1                                                        dap1_sclk_pb3           dap1_sclk_pb3           3rsvd1                                                        spi2_mosi_pb4           spi2_mosi_pb4           3rsvd2                                                        spi2_miso_pb5           spi2_miso_pb5           3rsvd2                                                        spi2_sck_pb6            spi2_sck_pb6            3rsvd2                                                        spi2_cs0_pb7            spi2_cs0_pb7            3rsvd2                                                        spi1_mosi_pc0           spi1_mosi_pc0           3rsvd1                                                        spi1_miso_pc1           spi1_miso_pc1           3rsvd1                                                        spi1_sck_pc2            spi1_sck_pc2            3rsvd1                                                        spi1_cs0_pc3            spi1_cs0_pc3            3rsvd1                                                        spi1_cs1_pc4            spi1_cs1_pc4            3rsvd1                                                        spi4_sck_pc5            spi4_sck_pc5            3rsvd1                                                        spi4_cs0_pc6            spi4_cs0_pc6            3rsvd1                                                        spi4_mosi_pc7           spi4_mosi_pc7           3rsvd1                                                        spi4_miso_pd0           spi4_miso_pd0           3rsvd1                                                        uart3_tx_pd1            uart3_tx_pd1            3rsvd2                                                        uart3_rx_pd2            uart3_rx_pd2            3rsvd2                                                        uart3_rts_pd3           uart3_rts_pd3           3rsvd2                                                        uart3_cts_pd4           uart3_cts_pd4                                                         dmic1_clk_pe0           dmic1_clk_pe0           3i2s3                                                          dmic1_dat_pe1           dmic1_dat_pe1           3i2s3                                                          dmic2_clk_pe2           dmic2_clk_pe2           3i2s3                                                          dmic2_dat_pe3           dmic2_dat_pe3           3i2s3                                                          dmic3_clk_pe4           dmic3_clk_pe4                                                          dmic3_dat_pe5           dmic3_dat_pe5           3rsvd2                                                        pe6         pe6         3rsvd0                                                        pe7         pe7         3pwm3                                                           gen3_i2c_scl_pf0            gen3_i2c_scl_pf0            3i2c3                                                            &          gen3_i2c_sda_pf1            gen3_i2c_sda_pf1            3i2c3                                                            &          uart2_tx_pg0            uart2_tx_pg0                                                          uart2_rx_pg1            uart2_rx_pg1            3uartb                                                        uart2_rts_pg2           uart2_rts_pg2           3rsvd2                                                        uart2_cts_pg3           uart2_cts_pg3           3rsvd2                                                        wifi_en_ph0         wifi_en_ph0                                                        wifi_rst_ph1            wifi_rst_ph1            3rsvd0                                                        wifi_wake_ap_ph2            wifi_wake_ap_ph2                                                         ap_wake_bt_ph3          ap_wake_bt_ph3                                                         bt_rst_ph4          bt_rst_ph4                                                         bt_wake_ap_ph5          bt_wake_ap_ph5                                                       ph6         ph6         3rsvd0                                                        ap_wake_nfc_ph7         ap_wake_nfc_ph7         3rsvd0                                                        nfc_en_pi0          nfc_en_pi0                                                         nfc_int_pi1         nfc_int_pi1                                                       gps_en_pi2          gps_en_pi2          3rsvd0                                                        gps_rst_pi3         gps_rst_pi3         3rsvd0                                                        uart4_tx_pi4            uart4_tx_pi4            3uartd                                                          uart4_rx_pi5            uart4_rx_pi5            3uartd                                                         uart4_rts_pi6           uart4_rts_pi6           3uartd                                                          uart4_cts_pi7           uart4_cts_pi7           3uartd                                                         gen1_i2c_sda_pj0            gen1_i2c_sda_pj0            3i2c1                                                            &          gen1_i2c_scl_pj1            gen1_i2c_scl_pj1            3i2c1                                                            &          gen2_i2c_scl_pj2            gen2_i2c_scl_pj2            3i2c2                                                            &         gen2_i2c_sda_pj3            gen2_i2c_sda_pj3            3i2c2                                                            &         dap4_fs_pj4         dap4_fs_pj4         3rsvd1                                                        dap4_din_pj5            dap4_din_pj5            3rsvd1                                                        dap4_dout_pj6           dap4_dout_pj6           3rsvd1                                                        dap4_sclk_pj7           dap4_sclk_pj7           3rsvd1                                                        pk0         pk0         3rsvd2                                                        pk1         pk1         3rsvd2                                                        pk2         pk2         3rsvd2                                                        pk3         pk3         3rsvd2                                                        pk4         pk4         3rsvd1                                                        pk5         pk5         3rsvd1                                                        pk6         pk6         3rsvd1                                                        pk7         pk7         3rsvd1                                                        pl0         pl0         3rsvd0                                                        pl1         pl1         3rsvd1                                                        sdmmc1_clk_pm0          sdmmc1_clk_pm0          3sdmmc1                                                        sdmmc1_cmd_pm1          sdmmc1_cmd_pm1          3sdmmc1                                                       sdmmc1_dat3_pm2         sdmmc1_dat3_pm2         3sdmmc1                                                       sdmmc1_dat2_pm3         sdmmc1_dat2_pm3         3sdmmc1                                                       sdmmc1_dat1_pm4         sdmmc1_dat1_pm4         3sdmmc1                                                       sdmmc1_dat0_pm5         sdmmc1_dat0_pm5         3sdmmc1                                                       sdmmc3_clk_pp0          sdmmc3_clk_pp0          3sdmmc3                                                        sdmmc3_cmd_pp1          sdmmc3_cmd_pp1          3sdmmc3                                                       sdmmc3_dat3_pp2         sdmmc3_dat3_pp2         3sdmmc3                                                       sdmmc3_dat2_pp3         sdmmc3_dat2_pp3         3sdmmc3                                                       sdmmc3_dat1_pp4         sdmmc3_dat1_pp4         3sdmmc3                                                       sdmmc3_dat0_pp5         sdmmc3_dat0_pp5         3sdmmc3                                                       cam1_mclk_ps0           cam1_mclk_ps0           3rsvd1                                                        cam2_mclk_ps1           cam2_mclk_ps1           3rsvd1                                                        cam_i2c_scl_ps2         cam_i2c_scl_ps2         3i2cvi                                                           &          cam_i2c_sda_ps3         cam_i2c_sda_ps3         3i2cvi                                                           &          cam_rst_ps4         cam_rst_ps4         3rsvd1                                                        cam_af_en_ps5           cam_af_en_ps5           3rsvd2                                                        cam_flash_en_ps6            cam_flash_en_ps6            3rsvd2                                                        cam1_pwdn_ps7           cam1_pwdn_ps7           3rsvd1                                                        cam2_pwdn_pt0           cam2_pwdn_pt0           3rsvd1                                                        cam1_strobe_pt1         cam1_strobe_pt1         3rsvd1                                                        uart1_tx_pu0            uart1_tx_pu0            3uarta                                                          uart1_rx_pu1            uart1_rx_pu1            3uarta                                                        uart1_rts_pu2           uart1_rts_pu2           3uarta                                                          uart1_cts_pu3           uart1_cts_pu3           3uarta                                                        lcd_bl_pwm_pv0          lcd_bl_pwm_pv0          3pwm0                                                           lcd_bl_en_pv1           lcd_bl_en_pv1                                                          lcd_rst_pv2         lcd_rst_pv2         3rsvd0                                                        lcd_gpio1_pv3           lcd_gpio1_pv3           3rsvd1                                                        lcd_gpio2_pv4           lcd_gpio2_pv4           3pwm1                                                           ap_ready_pv5            ap_ready_pv5            3rsvd0                                                        touch_rst_pv6           touch_rst_pv6                                                          touch_clk_pv7           touch_clk_pv7           3rsvd1                                                        modem_wake_ap_px0           modem_wake_ap_px0           3rsvd0                                                        touch_int_px1           touch_int_px1           3rsvd0                                                        motion_int_px2          motion_int_px2          3rsvd0                                                        als_prox_int_px3            als_prox_int_px3            3rsvd0                                                        temp_alert_px4          temp_alert_px4                                                       button_power_on_px5         button_power_on_px5         3rsvd0                                                        button_vol_up_px6           button_vol_up_px6                                                        button_vol_down_px7         button_vol_down_px7                                                      button_slide_sw_py0         button_slide_sw_py0         3rsvd0                                                        button_home_py1         button_home_py1                                                      lcd_te_py2          lcd_te_py2          3rsvd1                                                        pwr_i2c_scl_py3         pwr_i2c_scl_py3         3i2cpmu                                                          &          pwr_i2c_sda_py4         pwr_i2c_sda_py4         3i2cpmu                                                          &          clk_32k_out_py5         clk_32k_out_py5         3soc                                                      pz0         pz0                                                      pz1         pz1         3sdmmc1                                                       pz2         pz2         3rsvd2                                                        pz3         pz3         3rsvd1                                                        pz4         pz4                                                        pz5         pz5         3soc                                                      dap2_fs_paa0            dap2_fs_paa0            3i2s2                                                          dap2_sclk_paa1          dap2_sclk_paa1          3i2s2                                                          dap2_din_paa2           dap2_din_paa2           3i2s2                                                          dap2_dout_paa3          dap2_dout_paa3          3i2s2                                                          aud_mclk_pbb0           aud_mclk_pbb0           3aud                                                        dvfs_pwm_pbb1           dvfs_pwm_pbb1           3cldvfs                                                        dvfs_clk_pbb2           dvfs_clk_pbb2                                                          gpio_x1_aud_pbb3            gpio_x1_aud_pbb3            3rsvd0                                                        gpio_x3_aud_pbb4            gpio_x3_aud_pbb4            3rsvd0                                                        hdmi_cec_pcc0           hdmi_cec_pcc0           3cec                                                         &         hdmi_int_dp_hpd_pcc1            hdmi_int_dp_hpd_pcc1                                                           &          spdif_out_pcc2          spdif_out_pcc2          3rsvd1                                                        spdif_in_pcc3           spdif_in_pcc3                                                         usb_vbus_en0_pcc4           usb_vbus_en0_pcc4           3usb                                                         &         usb_vbus_en1_pcc5           usb_vbus_en1_pcc5           3usb                                                         &         dp_hpd0_pcc6            dp_hpd0_pcc6            3rsvd1                                                        pcc7            pcc7            3rsvd0                                                          &          spi2_cs1_pdd0           spi2_cs1_pdd0           3rsvd1                                                        qspi_sck_pee0           qspi_sck_pee0           3rsvd1                                                        qspi_cs_n_pee1          qspi_cs_n_pee1          3rsvd1                                                        qspi_io0_pee2           qspi_io0_pee2           3rsvd1                                                        qspi_io1_pee3           qspi_io1_pee3           3rsvd1                                                        qspi_io2_pee4           qspi_io2_pee4           3rsvd1                                                        qspi_io3_pee5           qspi_io3_pee5           3rsvd1                                                        core_pwr_req            core_pwr_req            3core                                                           cpu_pwr_req         cpu_pwr_req         3cpu                                                        pwr_int_n         
  pwr_int_n           3pmi                                                      clk_32k_in          clk_32k_in          3clk                                                       jtag_rtck         
  jtag_rtck           3jtag                                                           clk_req         clk_req         3sys                                                        shutdown          	  shutdown          	  3shutdown                                                                 serial@70006000       )    nvidia,tegra210-uart nvidia,tegra20-uart                 p `        @        C                   $                                        Eokay          serial@70006040       )    nvidia,tegra210-uart nvidia,tegra20-uart                 p `@       @        C                   %                                        M      	      	        Rrx tx         	  Edisabled          serial@70006200       )    nvidia,tegra210-uart nvidia,tegra20-uart                 p b        @        C                   .                  7              7        M      
      
        Rrx tx         	  Edisabled          serial@70006300       )    nvidia,tegra210-uart nvidia,tegra20-uart                 p c        @        C                   Z                  A              A        M                    Rrx tx         	  Edisabled          pwm@7000a000          '    nvidia,tegra210-pwm nvidia,tegra20-pwm               p                 \                                        pwm       	  Edisabled          i2c@7000c000          (    nvidia,tegra210-i2c nvidia,tegra124-i2c              p                         &                        +                           div-clk                       i2c         M                    Rrx tx         	  Edisabled          i2c@7000c400          (    nvidia,tegra210-i2c nvidia,tegra124-i2c              p                         T                        +                   6        div-clk               6        i2c         M                    Rrx tx         	  Edisabled          i2c@7000c500          (    nvidia,tegra210-i2c nvidia,tegra124-i2c              p                         \                        +                   C        div-clk               C        i2c         M                    Rrx tx         	  Edisabled          i2c@7000c700          (    nvidia,tegra210-i2c nvidia,tegra124-i2c              p                         x                        +                   g        div-clk               g        i2c         M                    Rrx tx           1           ;           #default idle          	  Edisabled          i2c@7000d000          (    nvidia,tegra210-i2c nvidia,tegra124-i2c              p                         5                        +                   /        div-clk               /        i2c         M                    Rrx tx           Eokay            g       i2c@7000d100          (    nvidia,tegra210-i2c nvidia,tegra124-i2c              p                         ?                        +                           div-clk                       i2c         M                    Rrx tx           1           ;           #default idle          	  Edisabled          spi@7000d400          (    nvidia,tegra210-spi nvidia,tegra114-spi              p                         ;                        +                   )        spi               )        spi         M                    Rrx tx         	  Edisabled          spi@7000d600          (    nvidia,tegra210-spi nvidia,tegra114-spi              p                         R                        +                   ,        spi               ,        spi         M                    Rrx tx         	  Edisabled          spi@7000d800          (    nvidia,tegra210-spi nvidia,tegra114-spi              p                         S                        +                   .        spi               .        spi         M                    Rrx tx         	  Edisabled          spi@7000da00          (    nvidia,tegra210-spi nvidia,tegra114-spi              p                         ]                        +                   D        spi               D        spi         M                    Rrx tx         	  Edisabled          rtc@7000e000          '    nvidia,tegra210-rtc nvidia,tegra20-rtc               p                                                           rtc       pmc@7000e400              nvidia,tegra210-pmc              p                       %           pclk clk32k_in          !                                 w         =      pinmux     pex-dpd-disable         pex-bias pex-clk1 pex-clk2                    =         pex-dpd-enable          pex-bias pex-clk1 pex-clk2                    =         sdmmc1-1v8          sdmmc1                       =   #      sdmmc1-3v3          sdmmc1                      =   "      sdmmc3-1v8          sdmmc3                       =   (      sdmmc3-3v3          sdmmc3                      =   '      gpio-1v8            gpio                      gpio-3v3            gpio                        powergates     aud                      k                                   =   -      mpe                                                   =         nvdec                                                     =         sor       P                                       0      R                  8      8                    0      R                  8                     =         venc                         4                          4                     =         vic                                                   =         xusba                                                     =          xusbb                 !              _                     =   ,      xusbc                  Y              Y                     =         nvjpg                                                     =               fuse@7000f800             nvidia,tegra210-efuse                p                                fuse                  '        fuse          cec@70015000              nvidia,tegra210-cec              pP                                                  cec       	  Edisabled          memory-controller@70019000            nvidia,tegra210-mc               p                                mc                  M                      .            =         external-memory-controller@7001b000           nvidia,tegra210-emc       0       p            p            p                       9        emc                 N                      ;           p            =         sata@70020000             nvidia,tegra210-ahci          0       pp             p        p     p                                           |      {        sata sata-oob                 |            {        sata sata-cold sata-oob       	  Edisabled          hda@70030000          '    nvidia,tegra210-hda nvidia,tegra30-hda               p                         Q                  }            o        hda hda2hdmi hda2codec_2x                 }            o        hda hda2hdmi hda2codec_2x           w         	  Edisabled          usb@70090000              nvidia,tegra210-xusb          0       p	             p	            p	                 hcd fpci ipfs                   '          (         X         Y                     j          "                            x  xusb_host xusb_host_src xusb_falcon_src xusb_ss xusb_ss_div2 xusb_ss_src xusb_hs_src xusb_fs_src pll_u_480m clk_m pll_e               Y                    xusb_host xusb_ss xusb_src          w               xusb_host xusb_ss              !      	  Edisabled          padctl@7009f000           nvidia,tegra210-xusb-padctl              p	                        1                         padctl                   	  Edisabled             =   !   pads       usb2                           trk       	  Edisabled       lanes      usb2-0        	  Edisabled            *          usb2-1        	  Edisabled            *          usb2-2        	  Edisabled            *          usb2-3        	  Edisabled            *                hsic                           trk       	  Edisabled       lanes      hsic-0        	  Edisabled            *          hsic-1        	  Edisabled            *                pcie                          pll                       phy       	  Edisabled       lanes      pcie-0        	  Edisabled            *          pcie-1        	  Edisabled            *          pcie-2        	  Edisabled            *          pcie-3        	  Edisabled            *          pcie-4        	  Edisabled            *          pcie-5        	  Edisabled            *          pcie-6        	  Edisabled            *                sata                          pll                       phy       	  Edisabled       lanes      sata-0        	  Edisabled            *                   ports      usb2-0        	  Edisabled          usb2-1        	  Edisabled          usb2-2        	  Edisabled          usb2-3        	  Edisabled          hsic-0        	  Edisabled          usb3-0        	  Edisabled          usb3-1        	  Edisabled          usb3-2        	  Edisabled          usb3-3        	  Edisabled                mmc@700b0000              nvidia,tegra210-sdhci                p                                                         sdhci tmclk                       sdhci         0  #sdmmc-3v3 sdmmc-1v8 sdmmc-3v3-drv sdmmc-1v8-drv         1   "        ;   #           $        5   %        ?            e   }           {           {                                /           B                      4     .             4         ; ;       	  Edisabled          mmc@700b0200              nvidia,tegra210-sdhci                p                                          	              sdhci tmclk               	        sdhci           #sdmmc-1v8-drv           1   &                              /           B          	  Edisabled          mmc@700b0400              nvidia,tegra210-sdhci                p                                          E              sdhci tmclk               E        sdhci         0  #sdmmc-3v3 sdmmc-1v8 sdmmc-3v3-drv sdmmc-1v8-drv         1   '        ;   (           )        5   *        ?            e   }           {           {        /           B         	  Edisabled          mmc@700b0600              nvidia,tegra210-sdhci                p                                                        sdhci tmclk                       sdhci           #sdmmc-3v3-drv sdmmc-1v8-drv         1   +        ;   +                              /           B                       4             4        V   (         f        Eokay            u                  usb@700d0000              nvidia,tegra210-xudc          0       p             p            p                 base fpci ipfs                  ,         (        !           >          "        dev ss ss_src fs_src hs_src         w   ,            dev ss             !      	  Edisabled          thermal-sensor@700e2000           nvidia,tegra210-soctherm                  p             ` `                 soctherm-reg car-reg                    0          3            thermal edp                d      N        tsensor soctherm                  N      	  soctherm                        =   M   throttle-cfgs      heavy              d           U                   p            =   O            mipi@700e3000             nvidia,tegra210-mipi                 p0                       8      	  mipi-cal            w                       =         clock@70110000            nvidia,tegra210-dfll          @       p             p             p            p                        >                 )     (      /        soc ref i2c                           
  dvco dfll           !             dfllCPU_out       	  Edisabled             =   F      aconnect@702c0000             nvidia,tegra210-aconnect                         k        ape apb2ape         w   -                     +            p,      p,           	  Edisabled       ahub@702d0800             nvidia,tegra210-ahub             p-                   j        ahub                  j                                            +            p-  p-           	  Edisabled       admaif@702d0000           nvidia,tegra210-admaif           p-             M   .      .      .      .      .      .      .      .      .      .      .      .      .      .      .      .      .   	   .   	   .   
   .   
      R  Rrx1 tx1 rx2 tx2 rx3 tx3 rx4 tx4 rx5 tx5 rx6 tx6 rx7 tx7 rx8 tx8 rx9 tx9 rx10 tx10         	  Edisabled       ports                        +       port@0                  endpoint               /         =   9         port@1                 endpoint               0         =   :         port@2                 endpoint               1         =   ;         port@3                 endpoint               2         =   <         port@4                 endpoint               3         =   =         port@5                 endpoint               4         =   >         port@6                 endpoint               5         =   ?         port@7                 endpoint               6         =   @         port@8                 endpoint               7         =   A         port@9              	   endpoint               8         =   B               i2s@702d1000              nvidia,tegra210-i2s          p-                        	        i2s sync_input                                       p         #I2S1          	  Edisabled          i2s@702d1100              nvidia,tegra210-i2s          p-                        
        i2s sync_input                                       p         #I2S2          	  Edisabled          i2s@702d1200              nvidia,tegra210-i2s          p-                                i2s sync_input                                       p         #I2S3          	  Edisabled          i2s@702d1300              nvidia,tegra210-i2s          p-                   e             i2s sync_input                e                       p         #I2S4          	  Edisabled          i2s@702d1400              nvidia,tegra210-i2s          p-                   f             i2s sync_input                f                       p         #I2S5          	  Edisabled          sfc@702d2000              nvidia,tegra210-sfc          p-             #SFC1          	  Edisabled          sfc@702d2200              nvidia,tegra210-sfc          p-"            #SFC2          	  Edisabled          sfc@702d2400              nvidia,tegra210-sfc          p-$            #SFC3          	  Edisabled          sfc@702d2600              nvidia,tegra210-sfc          p-&            #SFC4          	  Edisabled          amx@702d3000              nvidia,tegra210-amx          p-0            #AMX1          	  Edisabled          amx@702d3100              nvidia,tegra210-amx          p-1            #AMX2          	  Edisabled          adx@702d3800              nvidia,tegra210-adx          p-8            #ADX1          	  Edisabled          adx@702d3900              nvidia,tegra210-adx          p-9            #ADX2          	  Edisabled          dmic@702d4000             nvidia,tegra210-dmic             p-@                           dmic                                         .         #DMIC1         	  Edisabled          dmic@702d4100             nvidia,tegra210-dmic             p-A                           dmic                                         .         #DMIC2         	  Edisabled          dmic@702d4200             nvidia,tegra210-dmic             p-B                           dmic                                         .         #DMIC3         	  Edisabled          processing-engine@702d8000            nvidia,tegra210-ope          p-                         +                     #OPE1          	  Edisabled       equalizer@702d8100            nvidia,tegra210-peq          p-          dynamic-range-compressor@702d8200             nvidia,tegra210-mbdrc            p-             processing-engine@702d8400            nvidia,tegra210-ope          p-                         +                     #OPE2          	  Edisabled       equalizer@702d8500            nvidia,tegra210-peq          p-          dynamic-range-compressor@702d8600             nvidia,tegra210-mbdrc            p-             mvc@702da000              nvidia,tegra210-mvc          p-            #MVC1          	  Edisabled          mvc@702da200              nvidia,tegra210-mvc          p-            #MVC2          	  Edisabled          amixer@702dbb00           nvidia,tegra210-amixer           p-            #MIXER1        	  Edisabled          ports                        +       port@0                  endpoint               9         =   /         port@1                 endpoint               :         =   0         port@2                 endpoint               ;         =   1         port@3                 endpoint               <         =   2         port@4                 endpoint               =         =   3         port@5                 endpoint               >         =   4         port@6                 endpoint               ?         =   5         port@7                 endpoint               @         =   6         port@8                 endpoint               A         =   7         port@9              	   endpoint               B         =   8               dma-controller@702e2000           nvidia,tegra210-adma             p.                  C                                                                                                          !          "          #          $          %          &          '          (          )          *          +          ,          -                             j        d_audio       	  Edisabled             =   .      interrupt-controller@702f9000             nvidia,tegra210-agic                                  p/    p/                     f                         clk       	  Edisabled             =   C         spi@70410000              nvidia,tegra210-qspi                 pA                         
                        +                                qspi qspi_out                         M                    Rrx tx         	  Edisabled          usb@7d000000          )    nvidia,tegra210-ehci nvidia,tegra30-ehci                 }         @                            5utmi                           usb                       usb         >   D      	  Edisabled          usb-phy@7d000000          /    nvidia,tegra210-usb-phy nvidia,tegra30-usb-phy                }         @     }         @         5utmi                                       reg pll_u utmi-pads                             usb utmi-pads           I            c           z                         	                                                                       	  Edisabled             =   D      usb@7d004000          )    nvidia,tegra210-ehci nvidia,tegra30-ehci                 } @       @                            5utmi                   :        usb               :        usb         >   E      	  Edisabled          usb-phy@7d004000          /    nvidia,tegra210-usb-phy nvidia,tegra30-usb-phy                } @       @     }         @         5utmi                   :                    reg pll_u utmi-pads               :              usb utmi-pads           I            c           z                         	                                                              	  Edisabled             =   E      cpus                         +       cpu@0            cpu           arm,cortex-a57                             &              F        cpu_g pll_x pll_p dfll          =         K   G        [   H        lpsci             =   I      cpu@1            cpu           arm,cortex-a57                      K   G        [   H        lpsci             =   J      cpu@2            cpu           arm,cortex-a57                      K   G        [   H        lpsci             =   K      cpu@3            cpu           arm,cortex-a57                      K   G        [   H        lpsci             =   L      idle-states         zpsci       cpu-sleep             arm,idle-state          @             d                                      
  cpu-sleep         	  Edisabled             =   G         l2-cache              cache                                =   H         pmu           arm,cortex-a57-pmu        0                                                      I   J   K   L      sound         	  Edisabled                                 pll_a plla_out0                           x                                          thermal-zones      cpu-thermal                   5            C   M       trips      cpu-shutdown-trip           S d        _          	   critical          throttle-trip           S         _           hot          =   N         cooling-maps       map0            j   N        o   O                  mem-thermal                     5            C   M      trips      mem-nominal-trip            S  P        _           passive          =   P      mem-throttle-trip           S p        _           active           =   Q      mem-hot-trip            S         _           hot       mem-shutdown-trip           S X        _          	   critical             cooling-maps       dram-passive            o                   j   P      dram-active         o                 j   Q            gpu-thermal                   5            C   M      trips      gpu-shutdown-trip           S X        _          	   critical          throttle-trip           S         _           hot          =   R         cooling-maps       map0            j   R        o   O                  pllx-thermal                        5            C   M      trips      pllx-shutdown-trip          S X        _          	   critical          pllx-throttle-trip          S         _           hot          cooling-maps                timer             arm,armv8-timer       0                                 
                       ~      aliases         /rtc@7000e000           /serial@70006000          chosen          serial0:115200n8          memory@80000000          memory                               clock-32k             fixed-clock         g           !             =         psci              arm,psci-0.2            ssmc          	compatible interrupt-parent #address-cells #size-cells model phandle opp-microvolt opp-hz opp-supported-hw opp-suspend opp-peak-kBps device_type reg reg-names interrupts interrupt-names #interrupt-cells interrupt-map-mask interrupt-map bus-range ranges clocks clock-names resets reset-names pinctrl-names pinctrl-0 pinctrl-1 status assigned-addresses nvidia,num-lanes iommus power-domains groups function assigned-clocks assigned-clock-parents assigned-clock-rates nvidia,outputs nvidia,head nvidia,mipi-calibrate pinctrl-2 interrupt-controller #clock-cells #reset-cells operating-points-v2 interconnects interconnect-names #cooling-cells #gpio-cells gpio-controller #dma-cells nvidia,pins nvidia,pull-down-strength nvidia,pull-up-strength nvidia,pull nvidia,tristate nvidia,enable-input nvidia,open-drain nvidia,io-hv nvidia,function reg-shift dmas dma-names #pwm-cells clock-frequency nvidia,invert-interrupt low-power-disable low-power-enable power-source #power-domain-cells #iommu-cells nvidia,memory-controller power-domain-names nvidia,xusb-padctl nvidia,pmc #phy-cells pinctrl-3 nvidia,pad-autocal-pull-up-offset-3v3 nvidia,pad-autocal-pull-down-offset-3v3 nvidia,pad-autocal-pull-up-offset-1v8 nvidia,pad-autocal-pull-down-offset-1v8 nvidia,pad-autocal-pull-up-offset-sdr104 nvidia,pad-autocal-pull-down-offset-sdr104 nvidia,default-tap nvidia,default-trim nvidia,dqs-trim mmc-hs400-1_8v bus-width non-removable #thermal-sensor-cells nvidia,priority nvidia,cpu-throt-percent nvidia,gpu-throt-level #nvidia,mipi-calibrate-cells clock-output-names remote-endpoint sound-name-prefix phy_type nvidia,phy nvidia,hssync-start-delay nvidia,idle-wait-delay nvidia,elastic-limit nvidia,term-range-adj nvidia,xcvr-setup nvidia,xcvr-lsfslew nvidia,xcvr-lsrslew nvidia,hssquelch-level nvidia,hsdiscon-level nvidia,xcvr-hsslew nvidia,has-utmi-pad-registers clock-latency cpu-idle-states next-level-cache enable-method entry-method arm,psci-suspend-param entry-latency-us exit-latency-us min-residency-us wakeup-latency-us idle-state-name cache-level cache-unified interrupt-affinity polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device arm,no-tick-in-suspend rtc1 serial0 stdout-path 