  N   8  0   (              
                                                                     ,Marvell 8080 board        Z   2marvell,armada-8080-db marvell,armada-8080 marvell,armada-ap810-octa marvell,armada-ap810      aliases           =/soc/bus@e8000000/serial@512000           E/soc/bus@e8000000/serial@512100       psci             2arm,psci-0.2             Msmc       timer            2arm,armv8-timer       0   T                                 
         soc                                   2simple-bus            _   bus@e8000000                                      2simple-bus           _                             interrupt-controller@3000000             2arm,gic-v3           f                                      w         T      	             _      (                                                 msi-controller@3040000           2arm,gic-v3-its                                                           xor@400000        %   2marvell,armada-7k-xor marvell,xor-v2              @      A                                    xor@420000        %   2marvell,armada-7k-xor marvell,xor-v2              B      C                                    xor@440000        %   2marvell,armada-7k-xor marvell,xor-v2              D      E                                    xor@460000        %   2marvell,armada-7k-xor marvell,xor-v2              F      G                                    serial@512000            2snps,dw-apb-uart              Q                          T                               okay                     serial@512100            2snps,dw-apb-uart              Q!                         T                            	   disabled                cpus                                 cpu@0            cpu          2arm,cortex-a72                       psci          cpu@1            cpu          2arm,cortex-a72                      psci          cpu@100          cpu          2arm,cortex-a72                      psci          cpu@101          cpu          2arm,cortex-a72                     psci          cpu@200          cpu          2arm,cortex-a72                      psci          cpu@201          cpu          2arm,cortex-a72                     psci          cpu@300          cpu          2arm,cortex-a72                      psci          cpu@301          cpu          2arm,cortex-a72                     psci             chosen          serial0:115200n8          memory@0             memory                                   	#address-cells #size-cells interrupt-parent model compatible serial0 serial1 method interrupts ranges #interrupt-cells interrupt-controller reg phandle msi-controller #msi-cells msi-parent dma-coherent reg-shift reg-io-width status clock-frequency device_type enable-method stdout-path 