 7V   8 !   (             !P                                                                      ,Kontron BL i.MX8MP OSM-S          8   2kontron,imx8mp-bl-osm-s kontron,imx8mp-osm-s fsl,imx8mp    aliases       &   =/soc@0/bus@30800000/ethernet@30be0000         &   G/soc@0/bus@30800000/ethernet@30bf0000         "   Q/soc@0/bus@30000000/gpio@30200000         "   W/soc@0/bus@30000000/gpio@30210000         "   ]/soc@0/bus@30000000/gpio@30220000         "   c/soc@0/bus@30000000/gpio@30230000         "   i/soc@0/bus@30000000/gpio@30240000         !   o/soc@0/bus@30800000/i2c@30a20000          !   t/soc@0/bus@30800000/i2c@30a30000          !   y/soc@0/bus@30800000/i2c@30a40000          !   ~/soc@0/bus@30800000/i2c@30a50000          !   /soc@0/bus@30800000/i2c@30ad0000          !   /soc@0/bus@30800000/i2c@30ae0000          !   /soc@0/bus@30800000/mmc@30b40000          !   /soc@0/bus@30800000/mmc@30b50000          !   /soc@0/bus@30800000/mmc@30b60000          6   /soc@0/bus@30800000/spba-bus@30800000/serial@30860000         6   /soc@0/bus@30800000/spba-bus@30800000/serial@30890000         6   /soc@0/bus@30800000/spba-bus@30800000/serial@30880000         $   /soc@0/bus@30800000/serial@30a60000       !   /soc@0/bus@30800000/spi@30bb0000          (   /soc@0/bus@30800000/i2c@30ad0000/rtc@52       .   /soc@0/bus@30000000/snvs@30370000/snvs-rtc-lp         cpus                                 idle-states          psci       cpu-pd-wait          2arm,idle-state             3                                       !  
        2          D            cpu@0           Lcpu          2arm,cortex-a53          X            \             cpsci            q           ~   @                                 @                                         speed_grade                                          *           D      thermal-idle                       5  '                  D            cpu@1           Lcpu          2arm,cortex-a53          X           \             cpsci            q           ~   @                                 @                                                               *           D      thermal-idle                       5  '                  D            cpu@2           Lcpu          2arm,cortex-a53          X           \             cpsci            q           ~   @                                 @                                                               *           D      thermal-idle                       5  '                  D            cpu@3           Lcpu          2arm,cortex-a53          X           \             cpsci            q           ~   @                                 @                                                               *           D      thermal-idle                       5  '                  D            l2-cache0            2cache            A        O           s              @                   D            opp-table            2operating-points-v2          [        D      opp-1200000000          f    G         m P        {              I               opp-1600000000          f    _^         m ~        {               I               opp-1800000000          f    kI         m B@        {                I                  clock-osc-32k            2fixed-clock                                osc_32k         D   .      clock-osc-24m            2fixed-clock                     n6         osc_24m         D   /      clock-ext1           2fixed-clock                     k@      	  clk_ext1            D   0      clock-ext2           2fixed-clock                     k@      	  clk_ext2            D   1      clock-ext3           2fixed-clock                     k@      	  clk_ext3            D   2      clock-ext4           2fixed-clock                     k@      	  clk_ext4            D   3      funnel           2arm,coresight-static-funnel    in-ports                                 port@0          X       endpoint                       D            port@1          X      endpoint               	        D            port@2          X      endpoint               
        D            port@3          X      endpoint                       D               out-ports      port       endpoint                       D                   reserved-memory                                      dsp@92400000            X    @                        	  disabled            D            pmu          2arm,cortex-a53-pmu                        psci             2arm,psci-1.0             smc       thermal-zones      cpu-thermal         	                     -         trips      trip0           = L        I          Spassive         D         trip1           = s        I        	  Scritical            D            cooling-maps       map0            T           Y                               2          2          2          2            soc-thermal         	                     -          trips      trip0           = L        I          Spassive         D         trip1           = s        I        	  Scritical            D            cooling-maps       map0            T           Y                               2          2          2          2               timer            2arm,armv8-timer       0                                
           z          h      soc@0            2fsl,imx8mp-soc simple-bus                                                >                      soc_unique_id           D      etm@28440000          "   2arm,coresight-etm4x arm,primecell           X(D                        \      ]      	  apb_pclk            D      out-ports      port       endpoint                       D                  etm@28540000          "   2arm,coresight-etm4x arm,primecell           X(T                        \      ]      	  apb_pclk            D      out-ports      port       endpoint                       D   	               etm@28640000          "   2arm,coresight-etm4x arm,primecell           X(d                        \      ]      	  apb_pclk            D      out-ports      port       endpoint                       D   
               etm@28740000          "   2arm,coresight-etm4x arm,primecell           X(t                        \      ]      	  apb_pclk            D      out-ports      port       endpoint                       D                  funnel@28c03000       +   2arm,coresight-dynamic-funnel arm,primecell          X(0            \      ]      	  apb_pclk       in-ports                                 port@0          X       endpoint                        D            port@1          X      endpoint            D            port@2          X      endpoint            D               out-ports      port       endpoint               !        D   "               etf@28c04000              2arm,coresight-tmc arm,primecell         X(@            \      ]      	  apb_pclk       in-ports       port       endpoint               "        D   !            out-ports      port       endpoint               #        D   $               etr@28c06000              2arm,coresight-tmc arm,primecell         X(`            \      ]      	  apb_pclk       in-ports       port       endpoint               $        D   #               bus@30000000             2fsl,aips-bus simple-bus         X0    @                                            D      gpio@30200000            2fsl,imx8mp-gpio fsl,imx35-gpio          X0                     @          A           \                                                         %                  default            &       GPIO_A_0 GPIO_A_1    GPIO_A_2 GPIO_A_3 GPIO_A_4 GPIO_A_5 USB_B_EN USB_A_ID USB_B_ID USB_A_EN USB_A_OC CAM_MCK USB_B_OC ETH_B_MDC ETH_B_MDIO ETH_B_TXD3 ETH_B_TXD2 ETH_B_TXD1 ETH_B_TXD0 ETH_B_TX_EN ETH_B_TX_CLK ETH_B_RX_DV ETH_B_RX_CLK ETH_B_RXD0 ETH_B_RXD1 ETH_B_RXD2 ETH_B_RXD3           D   P      gpio@30210000            2fsl,imx8mp-gpio fsl,imx35-gpio          X0!                    B          C           \                                                         %       #         h              SDIO_A_CD SDIO_A_CLK SDIO_A_CMD SDIO_A_D0 SDIO_A_D1 SDIO_A_D2 SDIO_A_D3 CAN_ADDR2 CAN_ADDR3         default            '        D   \      gpio@30220000            2fsl,imx8mp-gpio fsl,imx35-gpio          X0"                    D          E           \                                                          %       8      %                 default            (     "  PCIE_WAKE PCIE_CLKREQ PCIE_A_PERST SDIO_B_D5 SDIO_B_D6 SDIO_B_D7 SPI_A_WP SPI_A_HOLD UART_B_RTS UART_B_CTS SDIO_B_D0 SDIO_B_D1 SDIO_B_D2 SDIO_B_D3 SDIO_B_WP SDIO_B_D4 PCIE_SM_ALERT SDIO_B_CLK SDIO_B_CMD IO_EXP_INT IO_EXP_RST  BOOT_SEL0 BOOT_SEL1   SDIO_B_CD SDIO_B_PWR_EN HDMI_CEC HDMI_HPD           D   D      gpio@30230000            2fsl,imx8mp-gpio fsl,imx35-gpio          X0#                    F          G           \                                                         %       R            default            )     /      ETH_A_MDC ETH_A_MDIO ETH_A_RXD0 ETH_A_RXD1 ETH_A_RXD2 ETH_A_RXD3 ETH_A_RX_DV ETH_A_RX_CLK ETH_A_TXD0 ETH_A_TXD1 ETH_A_TXD2 ETH_A_TXD3 ETH_A_TX_EN ETH_A_TX_CLK CSI_ENABLE  USB_HUB_RST TFT_RESET CAN_A_TX UART_A_CTS UART_A_RTS CAN_A_RX CAN_B_TX CAN_B_RX TFT_STBY CARRIER_PWR_EN I2S_A_DATA_IN I2S_LRCLK          D         gpio@30240000            2fsl,imx8mp-gpio fsl,imx35-gpio          X0$                    H          I           \                                                         %       r        /  I2S_BITCLK I2S_A_DATA_OUT I2S_MCLK PWM_2 PWM_1 PWM_0 SPI_A_SCK CAN_ADDR1 CAN_ADDR0 SPI_A_CS0 SPI_B_SCK SPI_B_SDO SPI_B_SDI SPI_B_CS0 I2C_A_SCL I2C_A_SDA I2C_B_SCL I2C_B_SDA PCIE_SMCLK PCIE_SMDAT I2C_CAM_SCL I2C_CAM_SDA UART_A_RX UART_A_TX UART_C_RX UART_C_TX UART_CON_RX UART_CON_TX UART_B_RX UART_B_TX          default            *        D   :      tmu@30260000             2fsl,imx8mp-tmu          X0&             \                +        calib                      D         watchdog@30280000            2fsl,imx8mp-wdt fsl,imx21-wdt            X0(                    N           \             okay            default            ,                 D         watchdog@30290000            2fsl,imx8mp-wdt fsl,imx21-wdt            X0)                    O           \           	  disabled            D         watchdog@302a0000            2fsl,imx8mp-wdt fsl,imx21-wdt            X0*                    
           \           	  disabled            D         timer@302d0000           2fsl,imx8mp-gpt fsl,imx6dl-gpt           X0-                    7           \                    ipg per         D         timer@302e0000           2fsl,imx8mp-gpt fsl,imx6dl-gpt           X0.                    6           \                    ipg per         D         timer@302f0000           2fsl,imx8mp-gpt fsl,imx6dl-gpt           X0/                    5           \                    ipg per         D         pinctrl@30330000             2fsl,imx8mp-iomuxc           X03             D   %   csimckgrp           0   L                Y        D         ecspi1grp         `  0    H  \           D    D  `           D    @  X           D    L              @        D   9      ecspi2grp         `  0    X  l          D    T  p          D    P  h          D    \              @        D   ;      enetrgmiigrp         P  0  X                  \    |           `               d               h                  l                  t                  p               x                  |                                                                                                D   c      eqosrgmiigrp         P  0   T                    X                 |                                                                                x                    t                    h                    d                    `                    \                    p                    l                         D   g      flexcan1grp       0  0                  T      L        T        D   @      flexcan2grp       0  0                 T      P        T        D   A      gpio1grp            0     t                    x                  (                    ,                    0                    4                         D   &      gpio3grp          x  0     D                ,                  0                  8                  <                        D   (      gpio4grp            0  H                  L                  P                  T                                                                                                D   )      hdmigrp         0  L                         D         i2c1grp       0  0     `         @      d         @          D   B      i2c1gpiogrp       0  0     `                  d                      D   C      i2c2grp       0  0    h         @      l         @          D   E      i2c2gpiogrp       0  0    h                  l                      D   F      i2c3grp       0  0    p         @      t         @          D   G      i2c3gpiogrp       0  0    p                  t                      D   H      i2c4grp       0  0    x         @      |         @          D   I      i2c4gpiogrp       0  0    x                  |                      D   J      i2c5grp       0  0  4          @    D          @          D   M      i2c5gpiogrp       0  0  4                  D                        D   N      pciegrp       `  0  8                  H                   @                                         D         pmicgrp         0                            D   O      pwm1grp         0    <                      D   5      pwm2grp         0    8                      D   6      pwm3grp         0    4                      D   7      regusb1vbusgrp          0   D                         D         regusb2vbusgrp          0   8                         D         regusdhc2vccgrp         0     8                      D         regusdhc3vccgrp         0  D                        D         regvddcarriergrp            0                          D         rtcgrp          0  @                       D   Q      sai3grp         0                     ,                                     $                  0                 \                (                    D   l      uart1grp          `  0                @  $                @              @                 @        D   <      uart2grp          0  0  (             @  ,                @        D   >      uart3grp          0  0  0             @  4                @        D   =      uart4grp          `  0     X           @  <                @    d          @     `             @        D   K      usb1idgrp           0   <                        D         usb1ocgrp           0   H                       D         usb2idgrp           0   @                       D         usb2ocgrp           0   P                       D         usdhc1grp           0                                                                                                                                                                                                                  A                           D   R      usdhc1-100mhzgrp            0                                                                                                                                                                                                                  A                           D   S      usdhc1-200mhzgrp            0                                                                                                                                                                                                                  A                           D   T      usdhc2grp           0                         $                   (                   ,                   0                   4                 $             @         D   W      usdhc2-100mhzgrp            0                         $                   (                   ,                   0                   4                 $             @         D   Y      usdhc2-200mhzgrp            0                         $                   (                   ,                   0                   4                 $             @         D   Z      usdhc2gpiogrp           0                           D   X      usdhc2wpgrp         0     <            @          D         usdhc3grp           0  $              (                h              l              p              t              |                L  $             P  (             T  ,                D   ]      usdhc3-100mhzgrp            0  $              (                h              l              p              t              |                L  $             P  (             T  ,                D   _      usdhc3-200mhzgrp            0  $              (                h              l              p              t              |                L  $             P  (             T  ,                D   `      usdhc3gpiogrp         0  0  @                    x                      D   ^      wdoggrp         0     |                      D   ,      ethphy0grp          0     x               F        D   e      ethphy1grp          0     t               F        D   i      gpio2grp          0  0     8              F     <              F        D   '      gpio5grp          0  0    D              F    H              F        D   *         syscon@30340000          2fsl,imx8mp-iomuxc-gpr syscon            X04             D   ?      efuse@30350000        )   2fsl,imx8mp-ocotp fsl,imx8mm-ocotp syscon            X05             \                                       D      unique-id@8         X              D         speed-grade@10          X              D         mac-address@90          X              D   b      mac-address@96          X              D   f      calib@264           X  d           D   +         clock-controller@30360000         $   2fsl,imx8mp-anatop fsl,imx8mm-anatop         X06                        D         snvs@30370000         #   2fsl,sec-v4.0-mon syscon simple-mfd          X07             D   -   snvs-rtc-lp          2fsl,sec-v4.0-mon-rtc-lp         9   -        @   4                                    \            	  snvs-rtc            D         snvs-powerkey            2fsl,sec-v4.0-pwrkey         9   -                          \              snvs-pwrkey         G   t         U        okay            D         snvs-lpgpr        +   2fsl,imx8mp-snvs-lpgpr fsl,imx7d-snvs-lpgpr          D            clock-controller@30380000            2fsl,imx8mp-ccm          X08                    U          V                      \   .   /   0   1   2   3      4  osc_32k osc_24m clk_ext1 clk_ext2 clk_ext3 clk_ext4       (  c      B            g      h            (  s      8      ,      A      8      @                ; / e         D         reset-controller@30390000            2fsl,imx8mp-src syscon           X09                    Y                      D   |      gpc@303a0000             2fsl,imx8mp-gpc          X0:                                 W                               D      pgc                              power-domain@0                      X            D   w      power-domain@1                      X           D         power-domain@2                      X           D         power-domain@3                      X           D         power-domain@4                      X           \      i      j             c     2      i      j        s      A      8      8        ; / ׄ         D         power-domain@5                      X           \          6        c      l      H        s      8      8        ׄ /         D   j      power-domain@6                      X           \                 4        D         power-domain@7                      X           \           f        c      e      f        s      8      8        / ׄ         D   4      power-domain@8                      X           \             D         power-domain@9                      X   	        \           4           4        D         power-domain@10                     X   
        \                  D   v      power-domain@11                     X           D         power-domain@12                     X           D         power-domain@13                     X           D         power-domain@14                     X           \           c        c      d      c        s      @      3        e k@        D         power-domain@15                     X           D         power-domain@16                     X           D   x      power-domain@17                     X           \     7             c     7        s      @        e         D   ~      power-domain@18                     X           \             D   y               bus@30400000             2fsl,aips-bus simple-bus         X0@   @                                            D      pwm@30660000             2fsl,imx8mp-pwm fsl,imx27-pwm            X0f                    Q           \                    ipg per                  	  disabled            default            5        D         pwm@30670000             2fsl,imx8mp-pwm fsl,imx27-pwm            X0g                    R           \                    ipg per                    okay            default            6        D         pwm@30680000             2fsl,imx8mp-pwm fsl,imx27-pwm            X0h                    S           \                    ipg per                  	  disabled            default            7        D         pwm@30690000             2fsl,imx8mp-pwm fsl,imx27-pwm            X0i                    T           \                    ipg per                  	  disabled            D         timer@306a0000           2nxp,sysctr-timer            X0j                    /           \   /        per         D         timer@306e0000           2fsl,imx8mp-gpt fsl,imx6dl-gpt           X0n                    3           \                    ipg per         D         timer@306f0000           2fsl,imx8mp-gpt fsl,imx6dl-gpt           X0o                    3           \                    ipg per         D         timer@30700000           2fsl,imx8mp-gpt fsl,imx6dl-gpt           X0p                    4           \                    ipg per         D            bus@30800000             2fsl,aips-bus simple-bus         X0   @                                            D      spba-bus@30800000            2fsl,spba-bus simple-bus         X0                                          spi@30820000                                    "   2fsl,imx8mp-ecspi fsl,imx6ul-ecspi           X0                               \                    ipg per         Ĵ         c              s      8            8             8                 rx tx         	  disabled            default            9           :   	           D         spi@30830000                                    "   2fsl,imx8mp-ecspi fsl,imx6ul-ecspi           X0                                \                    ipg per         Ĵ         c              s      8            8            8                 rx tx           okay            default            ;           :              D      eeram@0          2microchip,48l640            X            1-          spi@30840000                                    "   2fsl,imx8mp-ecspi fsl,imx6ul-ecspi           X0                    !           \                    ipg per         Ĵ         c              s      8            8            8                 rx tx         	  disabled            D         serial@30860000          2fsl,imx8mp-uart fsl,imx6q-uart          X0                               \                    ipg per             8             8                  rx tx           okay            default            <                 D         serial@30880000          2fsl,imx8mp-uart fsl,imx6q-uart          X0                               \                    ipg per             8             8                  rx tx           okay            default            =        D         serial@30890000          2fsl,imx8mp-uart fsl,imx6q-uart          X0                               \                    ipg per             8             8                  rx tx         	  disabled            default            >        D         can@308c0000             2fsl,imx8mp-flexcan          X0                               \      n              ipg per         c      t        s      0        bZ                     "   ?              okay            default            @        D         can@308d0000             2fsl,imx8mp-flexcan          X0                               \      n              ipg per         c      u        s      0        bZ                     "   ?            	  disabled            default            A        D            crypto@30900000          2fsl,sec-v4.0                                     X0                 0                    [           \      k      n      	  aclk ipg            D      jr@1000          2fsl,sec-v4.0-job-ring           X                     i         	  disabled            D         jr@2000          2fsl,sec-v4.0-job-ring           X                      j           D         jr@3000          2fsl,sec-v4.0-job-ring           X  0                   r           D            i2c@30a20000             2fsl,imx8mp-i2c fsl,imx21-i2c                                      X0                    #           \              okay                     default gpio               B        0   C        :   :              D   :              D      io-expander@20           2ti,tca6408          X                              D  DIO1_OUT DIO1_IN DIO2_OUT DIO2_IN DIO3_OUT DIO3_IN DIO4_OUT DIO4_IN              D                      N   D              D            i2c@30a30000             2fsl,imx8mp-i2c fsl,imx21-i2c                                      X0                    $           \              okay                     default gpio               E        0   F        :   :              D   :              D         i2c@30a40000             2fsl,imx8mp-i2c fsl,imx21-i2c                                      X0                    %           \            	  disabled                     default gpio               G        0   H        :   :              D   :              D         i2c@30a50000             2fsl,imx8mp-i2c fsl,imx21-i2c                                      X0                    &           \              okay                     default gpio               I        0   J        :   :              D   :              D         serial@30a60000          2fsl,imx8mp-uart fsl,imx6q-uart          X0                               \                    ipg per             8             8                  rx tx           okay            default            K         Z                 D         mailbox@30aa0000             2fsl,imx8mp-mu fsl,imx6sx-mu         X0                    X           \              {           D         mailbox@30e60000             2fsl,imx8mp-mu fsl,imx6sx-mu         X0                               {           \   L   $      	  disabled            D         i2c@30ad0000             2fsl,imx8mp-i2c fsl,imx21-i2c                                      X0                    L           \              okay                     default gpio               M        0   N        :   D              D   D              D      pmic@25          2nxp,pca9450c            X   %        default            O             P                               D      regulators     BUCK1           +0V8_VDD_SOC (BUCK1)             P         ~                            5        D         BUCK2           +0V9_VDD_ARM (BUCK2)             P         ~                            5         ~        ' P        D         BUCK4           +3V3 (BUCK4)             2Z         2Z                          D   U      BUCK5           +1V8 (BUCK5)             w@         w@                          D   V      BUCK6           +1V1_NVCC_DRAM (BUCK6)                                              D         LDO1            +1V8_NVCC_SNVS (LDO1)            w@         w@                          D         LDO3            +1V8_VDDA (LDO3)             w@         w@                          D         LDO5            NVCC_SD (LDO5)           w@         2Z        ?   P               D   [            eeprom@50            2onnn,n24s64b atmel,24c64            X   P        M            y            V         rtc@52           2microcrystal,rv3028         X   R        default            Q        d   D              D            i2c@30ae0000             2fsl,imx8mp-i2c fsl,imx21-i2c                                      X0                    M           \            	  disabled            D         mmc@30b40000          2   2fsl,imx8mp-usdhc fsl,imx8mm-usdhc fsl,imx7d-usdhc           X0                               \      n      _             ipg ahb per         x                                 okay          "  default state_100mhz state_200mhz              R        0   S           T           U           V                 D         mmc@30b50000          2   2fsl,imx8mp-usdhc fsl,imx8mm-usdhc fsl,imx7d-usdhc           X0                               \      n      _             ipg ahb per         x                                 okay          "  default state_100mhz state_200mhz              W   X        0   Y   X           Z   X           U           [           \              D         mmc@30b60000          2   2fsl,imx8mp-usdhc fsl,imx8mm-usdhc fsl,imx7d-usdhc           X0                               \      n      _             ipg ahb per         x                               	  disabled          "  default state_100mhz state_200mhz              ]   ^        0   _   ^           `   ^           a           [           D                 D               D         spi@30bb0000             2nxp,imx8mp-fspi         X0                   fspi_base fspi_mmap                k           \                    fspi_en fspi            Ĵ         c                                      	  disabled            D         dma-controller@30bd0000           2fsl,imx8mp-sdma fsl,imx8mq-sdma         X0                               \            k        ipg ahb                    imx/sdma/sdma-imx7d.bin         D   8      ethernet@30be0000         -   2fsl,imx8mp-fec fsl,imx8mq-fec fsl,imx6sx-fec            X0           0         v          w          x          y         (  \                                    "  ipg ahb ptp enet_clk_ref enet_out            c      ^                           s      6      :      ;      9             sY@                       *              b        mac-address         "   ?              okay            default            c      	  <rgmii-id            P   d        D      mdio                                 ethernet-phy@1           2ethernet-phy-id4f51.e91b            X              e        default         [  '        N   P              D   d            ethernet@30bf0000         '   2nxp,imx8mp-dwmac-eqos snps,dwmac-5.10a          X0                                         kmacirq eth_wake_irq          \                                stmmaceth pclk ptp_ref tx           c      ^                    s      6      :      ;             sY@           f        mac-address         {   ?           okay            default            g      	  rgmii-id            P   h        D      mdio             2snps,dwmac-mdio                              ethernet-phy@1           2ethernet-phy-id4f51.e91b            X              i        default         [  '        N   P               D   h               bus@30df0000             2fsl,imx8mp-aipstz           X0                j                                            0  0   @          D      spba-bus@30c00000            2fsl,spba-bus simple-bus         X0                                          sai@30c10000             2fsl,imx8mp-sai fsl,imx8mq-sai           X0                       (  \   L              L      L      L           bus mclk0 mclk1 mclk2 mclk3             k              k                  rx tx                  _         	  disabled            D         sai@30c20000             2fsl,imx8mp-sai fsl,imx8mq-sai           X0                       (  \   L             L      L      L           bus mclk0 mclk1 mclk2 mclk3             k             k                  rx tx                  `         	  disabled            D         sai@30c30000             2fsl,imx8mp-sai fsl,imx8mq-sai           X0                       (  \   L             L   	   L   
   L           bus mclk0 mclk1 mclk2 mclk3             k             k                  rx tx                  2         	  disabled            default            l        D         sai@30c50000             2fsl,imx8mp-sai fsl,imx8mq-sai           X0                       (  \   L             L      L      L           bus mclk0 mclk1 mclk2 mclk3             k             k   	               rx tx                  Z         	  disabled            D         sai@30c60000             2fsl,imx8mp-sai fsl,imx8mq-sai           X0                       (  \   L             L      L      L           bus mclk0 mclk1 mclk2 mclk3             k   
          k                  rx tx                  Z         	  disabled            D         sai@30c80000             2fsl,imx8mp-sai fsl,imx8mq-sai           X0                       (  \   L             L      L      L           bus mclk0 mclk1 mclk2 mclk3             k             k                  rx tx                  o         	  disabled            D         easrc@30c90000        "   2fsl,imx8mp-easrc fsl,imx8mn-easrc           X0                    z           \   L           mem            k             k             k             k             k             k             k             k                @  ctx0_rx ctx0_tx ctx1_rx ctx1_tx ctx2_rx ctx2_tx ctx3_rx ctx3_tx         imx/easrc/easrc-imx8mn.bin            @                 	  disabled            D         audio-controller@30ca0000            2fsl,imx8mp-micfil           X0                       0         m          n          ,          -         (  \   L      L   6      &      '            )  ipg_clk ipg_clk_app pll8k pll11k clkext3               k                 rx        	  disabled            D         aud2htx@30cb0000             2fsl,imx8mp-aud2htx          X0                               \   L   !        bus            k                  tx        	  disabled            D         xcvr@30cc0000            2fsl,imx8mp-xcvr          X0     0    0    0            ram regs rxfifo txfifo        $                                         \   L      L   &   L      L   #        ipg phy spba pll_ipg                k             k                  rx tx              L          	  disabled            D            dma-controller@30e00000           2fsl,imx8mp-sdma fsl,imx8mq-sdma         X0                        \   L                ipg ahb                "           imx/sdma/sdma-imx7d.bin         D         dma-controller@30e10000           2fsl,imx8mp-sdma fsl,imx8mq-sdma         X0                        \   L                ipg ahb                g           imx/sdma/sdma-imx7d.bin         D   k      clock-controller@30e20000            2fsl,imx8mp-audio-blk-ctrl           X0                                 @  \           {      |      }                       A      &  ahb sai1 sai2 sai3 sai5 sai6 sai7 axi              j        c                    p           D   L         interconnect@32700000            2fsl,imx8mp-noc fsl,imx8m-noc            X2p             \      g                      m        D   z   opp-table            2operating-points-v2         D   m   opp-200000000           f           opp-800000000           f    /       opp-1000000000          f    ;             bus@32c00000             2fsl,aips-bus simple-bus         X2   @                                            D      isi@32e00000             2fsl,imx8mp-isi          X2    @                          *           \                  axi apb            n           n         	  disabled            D      ports                                port@0          X       endpoint               o        D   q         port@1          X      endpoint               p        D   r               isp@32e10000             2fsl,imx8mp-isp          X2                    J            \                            isp aclk hclk pclk             n      n         	  isp csi2               n          	  disabled            D      ports                                port@1          X               isp@32e20000             2fsl,imx8mp-isp          X2                    K            \                            isp aclk hclk pclk             n      n         	  isp csi2               n         	  disabled            D      ports                                port@1          X               dwe@32e30000             2nxp,imx8mp-dw100            X2                    d           \                  axi ahb            n           D         csi@32e40000          *   2fsl,imx8mp-mipi-csi2 fsl,imx8mm-mipi-csi2           X2                               沀         \                            pclk wrap phy axi           c                    s      >                 n                    	  disabled            D      ports                                port@0          X          port@1          X      endpoint               q        D   o               csi@32e50000          *   2fsl,imx8mp-mipi-csi2 fsl,imx8mm-mipi-csi2           X2                    P           沀         \                            pclk wrap phy axi           c                    s      >                 n                    	  disabled            D      ports                                port@0          X          port@1          X      endpoint               r        D   p               dsi@32e60000             2fsl,imx8mp-mipi-dsim            X2             \                   bus_clk sclk_mipi           c      b              s      8               n6         0n6                              n          	  disabled            D      ports                                port@0          X       endpoint               s        D   t         port@1          X      endpoint            D                  display-controller@32e80000          2fsl,imx8mp-lcdif            X2             \                       pix axi disp_axi                                 n         	  disabled            D     port       endpoint               t        D   s            display-controller@32e90000          2fsl,imx8mp-lcdif            X2                               \                       pix axi disp_axi               n         	  disabled            D     port       endpoint               u        D   {            blk-ctrl@32ec0000         !   2fsl,imx8mp-media-blk-ctrl syscon            X2                                    (     v   w   w   v   v   x   v   y   y   x      F  bus mipi-dsi1 mipi-csi1 lcdif1 isi mipi-csi2 lcdif2 isp dwe mipi-dsi2           L   z      z      z      z      z      z      z      z      z       z      z   !   z      z   "   z      z   #   z         /  Zlcdif-rd lcdif-wr isi0 isi1 isi2 isp0 isp1 dwe        @  \                                              &  apb axi cam1 cam2 disp1 disp2 isp phy         0  c      a      b           9     8            (  s      A      8      (      (      @        e          e =                   D   n   bridge@5c            2fsl,imx8mp-ldb          X   \     (         	  ldb lvds            \     I        ldb         c              s      (      	  disabled            D     ports                                port@0          X       endpoint               {        D   u         port@1          X      endpoint            D           port@2          X      endpoint            D                    pcie-phy@32f00000            2fsl,imx8mp-pcie-phy         X2                |      |           mpciephy perst              }           y          	  disabled            D         blk-ctrl@32f10000             2fsl,imx8mp-hsio-blk-ctrl syscon         X2     $        \                  	  usb pcie               ~   ~         ~         (  bus usb usb-phy1 usb-phy2 pcie pcie-phy       @  L   z      z      z      z      z      z      z      z           Znoc-pcie usb1 usb2 pcie                                D   }      blk-ctrl@32fc0000             2fsl,imx8mp-hdmi-blk-ctrl syscon         X2           (  \      c                               apb axi ref_266m ref_24m fdcc         (                                      =  bus irqsteer lcdif pai pvi trng hdmi-tx hdmi-tx-phy hdcp hrv          0  L   z      z      z      z      z      z           Zhrv lcdif-hdmi hdcp                    D         interrupt-controller@32fc2000         %   2fsl,imx8mp-irqsteer fsl,imx-irqsteer            X2                    +                                             @        \      c        ipg                        D         display-bridge@32fc4000          2fsl,imx8mp-hdmi-pvi         X2@                                                  okay            D     ports                                port@0          X       endpoint                       D            port@1          X      endpoint                       D                  audio-bridge@32fc4800            2fsl,imx8mp-hdmi-pai         X2H                                    \      c        apb                     	  disabled            D     port       endpoint                       D               display-controller@32fc6000          2fsl,imx8mp-lcdif            X2`                                    \         c             pix axi disp_axi                          okay            D     port       endpoint                       D               hdmi@32fd8000            2fsl,imx8mp-hdmi-tx          X2   ~                                 \      c                       iahb isfr cec pix           c              s      6                                 okay            default                               D  	   ports                                port@0          X       endpoint                       D            port@1          X         port@2          X      endpoint                       D                  phy@32fdff00             2fsl,imx8mp-hdmi-phy         X2            \      c              apb ref         c              s                                        y            okay            D            pcie@33800000            2fsl,imx8mp-pcie         X3   @               dbi config          \          7              pcie pcie_bus pcie_aux          c      x                 s      9                                 Lpci                      0                                                                                         kmsi                                                                    ~                            }                            |                            {                      	               }              |      |           mapps turnoff            	         	  	!pcie-phy          	  disabled            D  
      pcie-ep@33800000             2fsl,imx8mp-pcie-ep           X3           3     3             dbi addr_space dbi2 atu         \          7              pcie pcie_bus pcie_aux          c      x                 s      9                                     kdma                       }              |      |           mapps turnoff            	         	  	!pcie-phy            	+           	:         	  disabled            D        gpu@38000000             2vivante,gc          X8                                 \           4           f        core shader bus reg                    c     3     4        s      A      A        ; ;                    D         gpu@38008000             2vivante,gc          X8                               \                 f        core bus reg                       c     5        s      A        ;                    D         video-codec@38300000             2nxp,imx8mm-vpu-g1           X80                               \             c      r        s      8        /                        D        video-codec@38310000             2nxp,imx8mq-vpu-g2           X81                               \     
        c      s      +        s      +        )' )'                       D        blk-ctrl@38330000            2fsl,imx8mp-vpu-blk-ctrl syscon          X83                                            bus g1 g2 vc8000e           \          
     	        g1 g2 vc8000e           c      `        s      8        /       0  L   z   %   z   $   z   &   z   $   z   '   z   $        Zg1 g2 vc8000e           D         npu@38500000             2vivante,gc          X8P                                 \                i      j        core shader bus reg                               D         interrupt-controller@38800000            2arm,gic-v3          X8     8                                                    	                        D         memory-controller@3d400000           2snps,ddrc-3.80a         X=@   @                            D        ddr-pmu@3d800000          %   2fsl,imx8mp-ddr-pmu fsl,imx8m-ddr-pmu            X=   @                 b         usb-phy@381f0040             2fsl,imx8mp-usb-phy          X8 @   @        \              phy         c              s                 }           y            okay            D         usb@32f10100             2fsl,imx8mp-dwc3         X2    8              \          @        hsio suspend                                 }                                     	I@   @                       okay            default                     	T        D     usb@38100000          
   2snps,dwc3           X8             \                 @        bus_early ref suspend                  (           	              	!usb2-phy usb3-phy            	p         	         	         	         	        	otg          	        	peripheral          okay            D     port       endpoint                       D                  usb-phy@382f0040             2fsl,imx8mp-usb-phy          X8/ @   @        \              phy         c              s                 }           y            okay            D         usb@32f10108             2fsl,imx8mp-dwc3         X2   8/              \          @        hsio suspend                                 }                                     	I@   @                       okay            default                     	T         
         
$        D     usb@38200000          
   2snps,dwc3           X8              \                 @        bus_early ref suspend                  )           	              	!usb2-phy usb3-phy            	p         	                                  	host            okay            D     usb-hub@1            2usb424,2514         X           N                     dsp@3b6e8000             2fsl,imx8mp-hifi4            X;n            \   L      L       L      L           ipg ocram core debug               j        
=tx rx rxdb        $  
H                                       imx/dsp/hifi4.bin              L         	  mrunstall            
O                   	  disabled            D           memory@40000000         Lmemory          X    @                chosen        6  
b/soc@0/bus@30800000/spba-bus@30800000/serial@30880000         regulator-usb1-vbus          2regulator-fixed         default                    
n   P                
s         LK@         LK@        VBUS_USB_A          D         regulator-usb2-vbus          2regulator-fixed         default                    
n   P   	             
s         LK@         LK@        VBUS_USB_B          D        regulator-usdhc2-vcc             2regulator-fixed         default                    
n   \                
s         2Z         2Z        VCC_SDIO_A        	  disabled            D        regulator-usdhc3-vcc             2regulator-fixed         default                    
n   D                
s         2Z         2Z        VCC_SDIO_B          D   a      regulator-vdd-carrier            2regulator-fixed         default                    
n   D                
s                          VDD_CARRIER         D     regulator-state-standby          
      regulator-state-mem          
      regulator-state-disk             
         connector         %   2gpio-usb-b-connector usb-b-connector            
   P   
            
Type-C          default                    Smicro           
      port       endpoint                       D               leds          
   2gpio-leds      led1            
led1               P             
  
heartbeat            pwm-beeper           2pwm-beeper          
                   regulator-vcc-panel          2regulator-fixed         
n                   
s         2Z         2Z      
  VCC_PANEL           D        __symbols__         
/cpus/idle-states/cpu-pd-wait           
/cpus/cpu@0         
/cpus/cpu@0/thermal-idle            
/cpus/cpu@1         /cpus/cpu@1/thermal-idle            /cpus/cpu@2         !/cpus/cpu@2/thermal-idle            ,/cpus/cpu@3         2/cpus/cpu@3/thermal-idle            =/cpus/l2-cache0         D/opp-table          R/clock-osc-32k          Z/clock-osc-24m          b/clock-ext1         k/clock-ext2         t/clock-ext3         }/clock-ext4       !  /funnel/in-ports/port@0/endpoint          !  /funnel/in-ports/port@1/endpoint          !  /funnel/in-ports/port@2/endpoint          !  /funnel/in-ports/port@3/endpoint             /funnel/out-ports/port/endpoint         /reserved-memory/dsp@92400000         '  /thermal-zones/cpu-thermal/trips/trip0        '  /thermal-zones/cpu-thermal/trips/trip1        '  /thermal-zones/soc-thermal/trips/trip0        '  /thermal-zones/soc-thermal/trips/trip1          /soc@0          !/soc@0/etm@28440000       ,  &/soc@0/etm@28440000/out-ports/port/endpoint         4/soc@0/etm@28540000       ,  9/soc@0/etm@28540000/out-ports/port/endpoint         G/soc@0/etm@28640000       ,  L/soc@0/etm@28640000/out-ports/port/endpoint         Z/soc@0/etm@28740000       ,  _/soc@0/etm@28740000/out-ports/port/endpoint       0  m/soc@0/funnel@28c03000/in-ports/port@0/endpoint       0  /soc@0/funnel@28c03000/in-ports/port@1/endpoint       0  /soc@0/funnel@28c03000/in-ports/port@2/endpoint       /  /soc@0/funnel@28c03000/out-ports/port/endpoint        +  /soc@0/etf@28c04000/in-ports/port/endpoint        ,  /soc@0/etf@28c04000/out-ports/port/endpoint       +  /soc@0/etr@28c06000/in-ports/port/endpoint          /soc@0/bus@30000000       "   W/soc@0/bus@30000000/gpio@30200000         "   ]/soc@0/bus@30000000/gpio@30210000         "   c/soc@0/bus@30000000/gpio@30220000         "   i/soc@0/bus@30000000/gpio@30230000         "  /soc@0/bus@30000000/gpio@30240000         !  /soc@0/bus@30000000/tmu@30260000          &  /soc@0/bus@30000000/watchdog@30280000         &  /soc@0/bus@30000000/watchdog@30290000         &  /soc@0/bus@30000000/watchdog@302a0000         #  	/soc@0/bus@30000000/timer@302d0000        #  /soc@0/bus@30000000/timer@302e0000        #  /soc@0/bus@30000000/timer@302f0000        %  /soc@0/bus@30000000/pinctrl@30330000          /  /soc@0/bus@30000000/pinctrl@30330000/csimckgrp        /  //soc@0/bus@30000000/pinctrl@30330000/ecspi1grp        /  >/soc@0/bus@30000000/pinctrl@30330000/ecspi2grp        2  M/soc@0/bus@30000000/pinctrl@30330000/enetrgmiigrp         2  `/soc@0/bus@30000000/pinctrl@30330000/eqosrgmiigrp         1  s/soc@0/bus@30000000/pinctrl@30330000/flexcan1grp          1  /soc@0/bus@30000000/pinctrl@30330000/flexcan2grp          .  /soc@0/bus@30000000/pinctrl@30330000/gpio1grp         .  /soc@0/bus@30000000/pinctrl@30330000/gpio3grp         .  /soc@0/bus@30000000/pinctrl@30330000/gpio4grp         -  /soc@0/bus@30000000/pinctrl@30330000/hdmigrp          -  /soc@0/bus@30000000/pinctrl@30330000/i2c1grp          1  /soc@0/bus@30000000/pinctrl@30330000/i2c1gpiogrp          -  /soc@0/bus@30000000/pinctrl@30330000/i2c2grp          1  /soc@0/bus@30000000/pinctrl@30330000/i2c2gpiogrp          -  
/soc@0/bus@30000000/pinctrl@30330000/i2c3grp          1  /soc@0/bus@30000000/pinctrl@30330000/i2c3gpiogrp          -  )/soc@0/bus@30000000/pinctrl@30330000/i2c4grp          1  6/soc@0/bus@30000000/pinctrl@30330000/i2c4gpiogrp          -  H/soc@0/bus@30000000/pinctrl@30330000/i2c5grp          1  U/soc@0/bus@30000000/pinctrl@30330000/i2c5gpiogrp          -  g/soc@0/bus@30000000/pinctrl@30330000/pciegrp          -  t/soc@0/bus@30000000/pinctrl@30330000/pmicgrp          -  /soc@0/bus@30000000/pinctrl@30330000/pwm1grp          -  /soc@0/bus@30000000/pinctrl@30330000/pwm2grp          -  /soc@0/bus@30000000/pinctrl@30330000/pwm3grp          4  /soc@0/bus@30000000/pinctrl@30330000/regusb1vbusgrp       4  /soc@0/bus@30000000/pinctrl@30330000/regusb2vbusgrp       5  /soc@0/bus@30000000/pinctrl@30330000/regusdhc2vccgrp          5  /soc@0/bus@30000000/pinctrl@30330000/regusdhc3vccgrp          6  /soc@0/bus@30000000/pinctrl@30330000/regvddcarriergrp         ,  /soc@0/bus@30000000/pinctrl@30330000/rtcgrp       -  &/soc@0/bus@30000000/pinctrl@30330000/sai3grp          .  3/soc@0/bus@30000000/pinctrl@30330000/uart1grp         .  A/soc@0/bus@30000000/pinctrl@30330000/uart2grp         .  O/soc@0/bus@30000000/pinctrl@30330000/uart3grp         .  ]/soc@0/bus@30000000/pinctrl@30330000/uart4grp         /  k/soc@0/bus@30000000/pinctrl@30330000/usb1idgrp        /  {/soc@0/bus@30000000/pinctrl@30330000/usb1ocgrp        /  /soc@0/bus@30000000/pinctrl@30330000/usb2idgrp        /  /soc@0/bus@30000000/pinctrl@30330000/usb2ocgrp        /  /soc@0/bus@30000000/pinctrl@30330000/usdhc1grp        6  /soc@0/bus@30000000/pinctrl@30330000/usdhc1-100mhzgrp         6  /soc@0/bus@30000000/pinctrl@30330000/usdhc1-200mhzgrp         /  /soc@0/bus@30000000/pinctrl@30330000/usdhc2grp        6  /soc@0/bus@30000000/pinctrl@30330000/usdhc2-100mhzgrp         6  /soc@0/bus@30000000/pinctrl@30330000/usdhc2-200mhzgrp         3  !/soc@0/bus@30000000/pinctrl@30330000/usdhc2gpiogrp        1  5/soc@0/bus@30000000/pinctrl@30330000/usdhc2wpgrp          /  G/soc@0/bus@30000000/pinctrl@30330000/usdhc3grp        6  V/soc@0/bus@30000000/pinctrl@30330000/usdhc3-100mhzgrp         6  l/soc@0/bus@30000000/pinctrl@30330000/usdhc3-200mhzgrp         3  /soc@0/bus@30000000/pinctrl@30330000/usdhc3gpiogrp        -  /soc@0/bus@30000000/pinctrl@30330000/wdoggrp          0  /soc@0/bus@30000000/pinctrl@30330000/ethphy0grp       0  /soc@0/bus@30000000/pinctrl@30330000/ethphy1grp       .  /soc@0/bus@30000000/pinctrl@30330000/gpio2grp         .  /soc@0/bus@30000000/pinctrl@30330000/gpio5grp         $  /soc@0/bus@30000000/syscon@30340000       #  /soc@0/bus@30000000/efuse@30350000        /  /soc@0/bus@30000000/efuse@30350000/unique-id@8        2  /soc@0/bus@30000000/efuse@30350000/speed-grade@10         2  /soc@0/bus@30000000/efuse@30350000/mac-address@90         2  /soc@0/bus@30000000/efuse@30350000/mac-address@96         -  /soc@0/bus@30000000/efuse@30350000/calib@264          .   /soc@0/bus@30000000/clock-controller@30360000         "  '/soc@0/bus@30000000/snvs@30370000         .  ,/soc@0/bus@30000000/snvs@30370000/snvs-rtc-lp         0  5/soc@0/bus@30000000/snvs@30370000/snvs-powerkey       -  A/soc@0/bus@30000000/snvs@30370000/snvs-lpgpr          .  L/soc@0/bus@30000000/clock-controller@30380000         .  P/soc@0/bus@30000000/reset-controller@30390000         !  T/soc@0/bus@30000000/gpc@303a0000          4  X/soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@0       4  f/soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@1       4  s/soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@2       4  /soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@3       4  /soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@4       4  /soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@5       4  /soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@6       4  /soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@7       4  /soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@8       4  /soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@9       5  /soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@10          5  /soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@11          5  /soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@12          5  /soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@13          5  /soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@14          5  
/soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@15          5  /soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@16          5  %/soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@17          5  1/soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@18            </soc@0/bus@30400000       !  /soc@0/bus@30400000/pwm@30660000          !  /soc@0/bus@30400000/pwm@30670000          !  /soc@0/bus@30400000/pwm@30680000          !  B/soc@0/bus@30400000/pwm@30690000          #  G/soc@0/bus@30400000/timer@306a0000        #  V/soc@0/bus@30400000/timer@306e0000        #  [/soc@0/bus@30400000/timer@306f0000        #  `/soc@0/bus@30400000/timer@30700000          e/soc@0/bus@30800000       3  7/soc@0/bus@30800000/spba-bus@30800000/spi@30820000        3  F/soc@0/bus@30800000/spba-bus@30800000/spi@30830000        3  k/soc@0/bus@30800000/spba-bus@30800000/spi@30840000        6  ;/soc@0/bus@30800000/spba-bus@30800000/serial@30860000         6  W/soc@0/bus@30800000/spba-bus@30800000/serial@30880000         6  I/soc@0/bus@30800000/spba-bus@30800000/serial@30890000         3  {/soc@0/bus@30800000/spba-bus@30800000/can@308c0000        3  /soc@0/bus@30800000/spba-bus@30800000/can@308d0000        $  r/soc@0/bus@30800000/crypto@30900000       ,  y/soc@0/bus@30800000/crypto@30900000/jr@1000       ,  /soc@0/bus@30800000/crypto@30900000/jr@2000       ,  /soc@0/bus@30800000/crypto@30900000/jr@3000       !   t/soc@0/bus@30800000/i2c@30a20000          0  /soc@0/bus@30800000/i2c@30a20000/io-expander@20       !   y/soc@0/bus@30800000/i2c@30a30000          !   ~/soc@0/bus@30800000/i2c@30a40000          !   /soc@0/bus@30800000/i2c@30a50000          $  e/soc@0/bus@30800000/serial@30a60000       %  /soc@0/bus@30800000/mailbox@30aa0000          %  /soc@0/bus@30800000/mailbox@30e60000          !   /soc@0/bus@30800000/i2c@30ad0000          )  /soc@0/bus@30800000/i2c@30ad0000/pmic@25          :  /soc@0/bus@30800000/i2c@30ad0000/pmic@25/regulators/BUCK1         :  /soc@0/bus@30800000/i2c@30ad0000/pmic@25/regulators/BUCK2         :  /soc@0/bus@30800000/i2c@30ad0000/pmic@25/regulators/BUCK4         :  /soc@0/bus@30800000/i2c@30ad0000/pmic@25/regulators/BUCK5         :  /soc@0/bus@30800000/i2c@30ad0000/pmic@25/regulators/BUCK6         9  /soc@0/bus@30800000/i2c@30ad0000/pmic@25/regulators/LDO1          9  /soc@0/bus@30800000/i2c@30ad0000/pmic@25/regulators/LDO3          9  /soc@0/bus@30800000/i2c@30ad0000/pmic@25/regulators/LDO5          (  /soc@0/bus@30800000/i2c@30ad0000/rtc@52       !  /soc@0/bus@30800000/i2c@30ae0000          !  /soc@0/bus@30800000/mmc@30b40000          !  /soc@0/bus@30800000/mmc@30b50000          !  O/soc@0/bus@30800000/mmc@30b60000          !  /soc@0/bus@30800000/spi@30bb0000          ,  $/soc@0/bus@30800000/dma-controller@30bd0000       &  */soc@0/bus@30800000/ethernet@30be0000         :  /soc@0/bus@30800000/ethernet@30be0000/mdio/ethernet-phy@1         &  ./soc@0/bus@30800000/ethernet@30bf0000         :  /soc@0/bus@30800000/ethernet@30bf0000/mdio/ethernet-phy@1           3/soc@0/bus@30df0000       3  9/soc@0/bus@30df0000/spba-bus@30c00000/sai@30c10000        3  >/soc@0/bus@30df0000/spba-bus@30c00000/sai@30c20000        3  ./soc@0/bus@30df0000/spba-bus@30c00000/sai@30c30000        3  C/soc@0/bus@30df0000/spba-bus@30c00000/sai@30c50000        3  H/soc@0/bus@30df0000/spba-bus@30c00000/sai@30c60000        3  M/soc@0/bus@30df0000/spba-bus@30c00000/sai@30c80000        5  R/soc@0/bus@30df0000/spba-bus@30c00000/easrc@30c90000          @  X/soc@0/bus@30df0000/spba-bus@30c00000/audio-controller@30ca0000       7  _/soc@0/bus@30df0000/spba-bus@30c00000/aud2htx@30cb0000        4  g/soc@0/bus@30df0000/spba-bus@30c00000/xcvr@30cc0000       ,  l/soc@0/bus@30df0000/dma-controller@30e00000       ,  r/soc@0/bus@30df0000/dma-controller@30e10000       .  x/soc@0/bus@30df0000/clock-controller@30e20000           /soc@0/interconnect@32700000          '  /soc@0/interconnect@32700000/opp-table          /soc@0/bus@32c00000       !  /soc@0/bus@32c00000/isi@32e00000          7  /soc@0/bus@32c00000/isi@32e00000/ports/port@0/endpoint        7  /soc@0/bus@32c00000/isi@32e00000/ports/port@1/endpoint        !  /soc@0/bus@32c00000/isp@32e10000          !  /soc@0/bus@32c00000/isp@32e20000          !  /soc@0/bus@32c00000/dwe@32e30000          !  /soc@0/bus@32c00000/csi@32e40000          7  /soc@0/bus@32c00000/csi@32e40000/ports/port@1/endpoint        !  /soc@0/bus@32c00000/csi@32e50000          7  /soc@0/bus@32c00000/csi@32e50000/ports/port@1/endpoint        !  /soc@0/bus@32c00000/dsi@32e60000          7  /soc@0/bus@32c00000/dsi@32e60000/ports/port@0/endpoint        7  /soc@0/bus@32c00000/dsi@32e60000/ports/port@1/endpoint        0  /soc@0/bus@32c00000/display-controller@32e80000       >  %/soc@0/bus@32c00000/display-controller@32e80000/port/endpoint         0  4/soc@0/bus@32c00000/display-controller@32e90000       >  ;/soc@0/bus@32c00000/display-controller@32e90000/port/endpoint         &  I/soc@0/bus@32c00000/blk-ctrl@32ec0000         0  X/soc@0/bus@32c00000/blk-ctrl@32ec0000/bridge@5c       F  d/soc@0/bus@32c00000/blk-ctrl@32ec0000/bridge@5c/ports/port@0/endpoint         F  t/soc@0/bus@32c00000/blk-ctrl@32ec0000/bridge@5c/ports/port@1/endpoint         F  /soc@0/bus@32c00000/blk-ctrl@32ec0000/bridge@5c/ports/port@2/endpoint         &  j/soc@0/bus@32c00000/pcie-phy@32f00000         &  /soc@0/bus@32c00000/blk-ctrl@32f10000         &  /soc@0/bus@32c00000/blk-ctrl@32fc0000         2  /soc@0/bus@32c00000/interrupt-controller@32fc2000         ,  /soc@0/bus@32c00000/display-bridge@32fc4000       B  /soc@0/bus@32c00000/display-bridge@32fc4000/ports/port@0/endpoint         B  /soc@0/bus@32c00000/display-bridge@32fc4000/ports/port@1/endpoint         *  /soc@0/bus@32c00000/audio-bridge@32fc4800         8  /soc@0/bus@32c00000/audio-bridge@32fc4800/port/endpoint       0  /soc@0/bus@32c00000/display-controller@32fc6000       >  /soc@0/bus@32c00000/display-controller@32fc6000/port/endpoint         "  /soc@0/bus@32c00000/hdmi@32fd8000         8  /soc@0/bus@32c00000/hdmi@32fd8000/ports/port@0/endpoint       8  /soc@0/bus@32c00000/hdmi@32fd8000/ports/port@2/endpoint       !  (/soc@0/bus@32c00000/phy@32fdff00            4/soc@0/pcie@33800000            o/soc@0/pcie@33800000            :/soc@0/pcie-ep@33800000         C/soc@0/pcie-ep@33800000         /soc@0/gpu@38000000         /soc@0/gpu@38008000         /soc@0/video-codec@38300000         /soc@0/video-codec@38310000         K/soc@0/blk-ctrl@38330000            [/soc@0/npu@38500000       %  _/soc@0/interrupt-controller@38800000          "  c/soc@0/memory-controller@3d400000           j/soc@0/usb-phy@381f0040         t/soc@0/usb@32f10100       !  {/soc@0/usb@32f10100/usb@38100000          /  /soc@0/usb@32f10100/usb@38100000/port/endpoint          /soc@0/usb-phy@382f0040         /soc@0/usb@32f10108       !  /soc@0/usb@32f10108/usb@38200000            /soc@0/dsp@3b6e8000         /regulator-usb1-vbus            /regulator-usb2-vbus            /regulator-usdhc2-vcc           /regulator-usdhc3-vcc           
/regulator-vdd-carrier          /connector/port/endpoint            /regulator-vcc-panel             	interrupt-parent #address-cells #size-cells model compatible ethernet0 ethernet1 gpio0 gpio1 gpio2 gpio3 gpio4 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 mmc0 mmc1 mmc2 serial0 serial1 serial2 serial3 spi0 rtc0 rtc1 entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us wakeup-latency-us phandle device_type reg clocks enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache nvmem-cells nvmem-cell-names operating-points-v2 #cooling-cells cpu-idle-states cpu-supply duration-us cache-unified cache-level opp-shared opp-hz opp-microvolt opp-supported-hw clock-latency-ns opp-suspend #clock-cells clock-frequency clock-output-names remote-endpoint ranges no-map status interrupts polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device arm,no-tick-in-suspend cpu clock-names gpio-controller #gpio-cells interrupt-controller #interrupt-cells gpio-ranges pinctrl-names pinctrl-0 gpio-line-names #thermal-sensor-cells fsl,ext-reset-output fsl,pins regmap offset linux,keycode wakeup-source assigned-clocks assigned-clock-parents assigned-clock-rates #reset-cells #power-domain-cells power-domains #pwm-cells dmas dma-names cs-gpios spi-max-frequency uart-has-rtscts fsl,clk-source fsl,stop-mode pinctrl-1 scl-gpios sda-gpios reset-gpios linux,rs485-enabled-at-boot-time #mbox-cells nxp,i2c-lt-enable regulator-name regulator-min-microvolt regulator-max-microvolt regulator-boot-on regulator-always-on regulator-ramp-delay nxp,dvs-run-voltage nxp,dvs-standby-voltage sd-vsel-gpios pagesize num-addresses interrupts-extended fsl,tuning-start-tap fsl,tuning-step bus-width pinctrl-2 vmmc-supply vqmmc-supply non-removable cd-gpios wp-gpios reg-names #dma-cells fsl,sdma-ram-script-name fsl,num-tx-queues fsl,num-rx-queues phy-connection-type phy-handle reset-assert-us interrupt-names intf_mode phy-mode #access-controller-cells #sound-dai-cells firmware-name fsl,asrc-rate fsl,asrc-format resets #interconnect-cells fsl,blk-ctrl power-domain-names fsl,num-channels samsung,pll-clock-frequency interconnects interconnect-names reset-names #phy-cells fsl,channel fsl,num-irqs reg-io-width ddc-i2c-bus bus-range num-lanes num-viewport interrupt-map-mask interrupt-map fsl,max-link-speed linux,pci-domain phys phy-names num-ib-windows num-ob-windows dma-ranges fsl,over-current-active-low snps,gfladj-refclk-lpm-sel-quirk snps,parkmode-disable-ss-quirk adp-disable hnp-disable srp-disable dr_mode usb-role-switch role-switch-default-mode fsl,disable-port-power-control fsl,permanently-attached mbox-names mboxes access-controllers stdout-path gpio enable-active-high regulator-on-in-suspend regulator-off-in-suspend id-gpios label vbus-supply linux,default-trigger pwms cpu_pd_wait A53_0 cpu0_therm A53_1 cpu1_therm A53_2 cpu2_therm A53_3 cpu3_therm A53_L2 a53_opp_table osc_32k osc_24m clk_ext1 clk_ext2 clk_ext3 clk_ext4 ca_funnel_in_port0 ca_funnel_in_port1 ca_funnel_in_port2 ca_funnel_in_port3 ca_funnel_out_port0 dsp_reserved cpu_alert0 cpu_crit0 soc_alert0 soc_crit0 soc etm0 etm0_out_port etm1 etm1_out_port etm2 etm2_out_port etm3 etm3_out_port hugo_funnel_in_port0 hugo_funnel_in_port1 hugo_funnel_in_port2 hugo_funnel_out_port0 etf_in_port etf_out_port etr_in_port aips1 gpio5 tmu wdog1 wdog2 wdog3 gpt1 gpt2 gpt3 iomuxc pinctrl_csi_mck pinctrl_ecspi1 pinctrl_ecspi2 pinctrl_enet_rgmii pinctrl_eqos_rgmii pinctrl_flexcan1 pinctrl_flexcan2 pinctrl_gpio1 pinctrl_gpio3 pinctrl_gpio4 pinctrl_hdmi pinctrl_i2c1 pinctrl_i2c1_gpio pinctrl_i2c2 pinctrl_i2c2_gpio pinctrl_i2c3 pinctrl_i2c3_gpio pinctrl_i2c4 pinctrl_i2c4_gpio pinctrl_i2c5 pinctrl_i2c5_gpio pinctrl_pcie pinctrl_pmic pinctrl_pwm1 pinctrl_pwm2 pinctrl_pwm3 pinctrl_reg_usb1_vbus pinctrl_reg_usb2_vbus pinctrl_reg_usdhc2_vcc pinctrl_reg_usdhc3_vcc pinctrl_reg_vdd_carrier pinctrl_rtc pinctrl_sai3 pinctrl_uart1 pinctrl_uart2 pinctrl_uart3 pinctrl_uart4 pinctrl_usb1_id pinctrl_usb1_oc pinctrl_usb2_id pinctrl_usb2_oc pinctrl_usdhc1 pinctrl_usdhc1_100mhz pinctrl_usdhc1_200mhz pinctrl_usdhc2 pinctrl_usdhc2_100mhz pinctrl_usdhc2_200mhz pinctrl_usdhc2_gpio pinctrl_usdhc2_wp pinctrl_usdhc3 pinctrl_usdhc3_100mhz pinctrl_usdhc3_200mhz pinctrl_usdhc3_gpio pinctrl_wdog pinctrl_ethphy0 pinctrl_ethphy1 pinctrl_gpio2 pinctrl_gpio5 gpr ocotp imx8mp_uid cpu_speed_grade eth_mac1 eth_mac2 tmu_calib anatop snvs snvs_rtc snvs_pwrkey snvs_lpgpr clk src gpc pgc_mipi_phy1 pgc_pcie_phy pgc_usb1_phy pgc_usb2_phy pgc_mlmix pgc_audio pgc_gpu2d pgc_gpumix pgc_vpumix pgc_gpu3d pgc_mediamix pgc_vpu_g1 pgc_vpu_g2 pgc_vpu_vc8000e pgc_hdmimix pgc_hdmi_phy pgc_mipi_phy2 pgc_hsiomix pgc_ispdwp aips2 pwm4 system_counter gpt6 gpt5 gpt4 aips3 ecspi3 crypto sec_jr0 sec_jr1 sec_jr2 gpio_expander_dio mu2 pca9450 reg_vdd_soc reg_vdd_arm reg_vdd_3v3 reg_vdd_1v8 reg_nvcc_dram reg_nvcc_snvs reg_vdda reg_nvcc_sd rv3028 i2c6 flexspi sdma1 fec eqos aips5 sai1 sai2 sai5 sai6 sai7 easrc micfil aud2htx xcvr sdma3 sdma2 audio_blk_ctrl noc noc_opp_table aips4 isi_0 isi_in_0 isi_in_1 isp_0 isp_1 dewarp mipi_csi_0 mipi_csi_0_out mipi_csi_1 mipi_csi_1_out mipi_dsi dsim_from_lcdif1 mipi_dsi_out lcdif1_to_dsim lcdif2 lcdif2_to_ldb media_blk_ctrl lvds_bridge ldb_from_lcdif2 ldb_lvds_ch0 ldb_lvds_ch1 hsio_blk_ctrl hdmi_blk_ctrl irqsteer_hdmi hdmi_pvi pvi_from_lcdif3 pvi_to_hdmi_tx hdmi_pai pai_to_hdmi_tx lcdif3_to_pvi hdmi_tx_from_pvi hdmi_tx_from_pai hdmi_tx_phy pcie0 pcie0_ep pcie_ep vpumix_blk_ctrl npu gic edacmc usb3_phy0 usb3_0 usb_dwc3_0 usb3_dwc usb3_phy1 usb3_1 usb_dwc3_1 dsp usb_dr_connector reg_vcc_panel 