Ðþí  4ß   8  3¸   (            '  3€                             "    renesas,ironhide renesas,r8a78000                                    &         )   7Renesas Ironhide board based on r8a78000       cpus                                cpu-map    cluster0       core0            =         core1            =         core2            =         core3            =            cluster1       core0            =         core1            =         core2            =         core3            =   	         cluster2       core0            =   
      core1            =         core2            =         core3            =            cluster3       core0            =         core1            =         core2            =         core3            =            cluster4       core0            =         core1            =         core2            =         core3            =            cluster5       core0            =         core1            =         core2            =         core3            =            cluster6       core0            =         core1            =         core2            =         core3            =            cluster7       core0            =         core1            =         core2            =          core3            =   !            cpu@0             arm,cortex-a720ae            A                 Ecpu          Q   "         b         cpu@100           arm,cortex-a720ae            A                Ecpu          Q   #         b         cpu@200           arm,cortex-a720ae            A                Ecpu          Q   $         b         cpu@300           arm,cortex-a720ae            A                Ecpu          Q   %         b         cpu@10000             arm,cortex-a720ae            A                Ecpu          Q   &         b         cpu@10100             arm,cortex-a720ae            A               Ecpu          Q   '         b         cpu@10200             arm,cortex-a720ae            A               Ecpu          Q   (         b         cpu@10300             arm,cortex-a720ae            A               Ecpu          Q   )         b   	      cpu@20000             arm,cortex-a720ae            A                Ecpu          Q   *         b   
      cpu@20100             arm,cortex-a720ae            A               Ecpu          Q   +         b         cpu@20200             arm,cortex-a720ae            A               Ecpu          Q   ,         b         cpu@20300             arm,cortex-a720ae            A               Ecpu          Q   -         b         cpu@30000             arm,cortex-a720ae            A                Ecpu          Q   .         b         cpu@30100             arm,cortex-a720ae            A               Ecpu          Q   /         b         cpu@30200             arm,cortex-a720ae            A               Ecpu          Q   0         b         cpu@30300             arm,cortex-a720ae            A               Ecpu          Q   1         b         cpu@40000             arm,cortex-a720ae            A                Ecpu          Q   2         b         cpu@40100             arm,cortex-a720ae            A               Ecpu          Q   3         b         cpu@40200             arm,cortex-a720ae            A               Ecpu          Q   4         b         cpu@40300             arm,cortex-a720ae            A               Ecpu          Q   5         b         cpu@50000             arm,cortex-a720ae            A                Ecpu          Q   6         b         cpu@50100             arm,cortex-a720ae            A               Ecpu          Q   7         b         cpu@50200             arm,cortex-a720ae            A               Ecpu          Q   8         b         cpu@50300             arm,cortex-a720ae            A               Ecpu          Q   9         b         cpu@60000             arm,cortex-a720ae            A                Ecpu          Q   :         b         cpu@60100             arm,cortex-a720ae            A               Ecpu          Q   ;         b         cpu@60200             arm,cortex-a720ae            A               Ecpu          Q   <         b         cpu@60300             arm,cortex-a720ae            A               Ecpu          Q   =         b         cpu@70000             arm,cortex-a720ae            A                Ecpu          Q   >         b         cpu@70100             arm,cortex-a720ae            A               Ecpu          Q   ?         b         cpu@70200             arm,cortex-a720ae            A               Ecpu          Q   @         b          cpu@70300             arm,cortex-a720ae            A               Ecpu          Q   A         b   !      cache-controller-200              cache             j         x            Q   B         b   "      cache-controller-201              cache             j         x            Q   B         b   #      cache-controller-202              cache             j         x            Q   B         b   $      cache-controller-203              cache             j         x            Q   B         b   %      cache-controller-204              cache             j         x            Q   C         b   &      cache-controller-205              cache             j         x            Q   C         b   '      cache-controller-206              cache             j         x            Q   C         b   (      cache-controller-207              cache             j         x            Q   C         b   )      cache-controller-208              cache             j         x            Q   D         b   *      cache-controller-209              cache             j         x            Q   D         b   +      cache-controller-210              cache             j         x            Q   D         b   ,      cache-controller-211              cache             j         x            Q   D         b   -      cache-controller-212              cache             j         x            Q   E         b   .      cache-controller-213              cache             j         x            Q   E         b   /      cache-controller-214              cache             j         x            Q   E         b   0      cache-controller-215              cache             j         x            Q   E         b   1      cache-controller-216              cache             j         x            Q   F         b   2      cache-controller-217              cache             j         x            Q   F         b   3      cache-controller-218              cache             j         x            Q   F         b   4      cache-controller-219              cache             j         x            Q   F         b   5      cache-controller-220              cache             j         x            Q   G         b   6      cache-controller-221              cache             j         x            Q   G         b   7      cache-controller-222              cache             j         x            Q   G         b   8      cache-controller-223              cache             j         x            Q   G         b   9      cache-controller-224              cache             j         x            Q   H         b   :      cache-controller-225              cache             j         x            Q   H         b   ;      cache-controller-226              cache             j         x            Q   H         b   <      cache-controller-227              cache             j         x            Q   H         b   =      cache-controller-228              cache             j         x            Q   I         b   >      cache-controller-229              cache             j         x            Q   I         b   ?      cache-controller-230              cache             j         x            Q   I         b   @      cache-controller-231              cache             j         x            Q   I         b   A      cache-controller-30           cache             j         x            b   B      cache-controller-31           cache             j         x            b   C      cache-controller-32           cache             j         x            b   D      cache-controller-33           cache             j         x            b   E      cache-controller-34           cache             j         x            b   F      cache-controller-35           cache             j         x            b   G      cache-controller-36           cache             j         x            b   H      cache-controller-37           cache             j         x            b   I         dummy-clk-sgasyncd16              fixed-clock          „             ‘ù>         b   J      dummy-clk-sgasyncd4           fixed-clock          „             ‘äè          b   L      extal-clk             fixed-clock          „             ‘ þOè      extalr-clk            fixed-clock          „             ‘  €       scif-clk              fixed-clock          „             ‘Œº€         b   K      soc           simple-bus                                    ¡   chipid@189e0044           renesas,prr          A    ž D             interrupt-controller@39000000             arm,gic-v3           ¨                          ¹          A    9              9       €           Î      	            b         serial@c0700000       :    renesas,scif-r8a78000 renesas,rcar-gen5-scif renesas,scif            A    Àp         @         Î      
            Ù   J   J   K         àfck brg_int scif_clk          	   ìdisabled          serial@c0704000       :    renesas,scif-r8a78000 renesas,rcar-gen5-scif renesas,scif            A    Àp@        @         Î                  Ù   J   J   K         àfck brg_int scif_clk          	   ìdisabled          serial@c0708000       :    renesas,scif-r8a78000 renesas,rcar-gen5-scif renesas,scif            A    Àp€        @         Î                  Ù   J   J   K         àfck brg_int scif_clk          	   ìdisabled          serial@c070c000       :    renesas,scif-r8a78000 renesas,rcar-gen5-scif renesas,scif            A    ÀpÀ        @         Î                  Ù   J   J   K         àfck brg_int scif_clk          	   ìdisabled          serial@c0710000       =    renesas,hscif-r8a78000 renesas,rcar-gen5-hscif renesas,hscif             A    Àq         `         Î                  Ù   L   L   K         àfck brg_int scif_clk             ìokay              ó      serial@c0714000       =    renesas,hscif-r8a78000 renesas,rcar-gen5-hscif renesas,hscif             A    Àq@        `         Î                  Ù   L   L   K         àfck brg_int scif_clk          	   ìdisabled          serial@c0718000       =    renesas,hscif-r8a78000 renesas,rcar-gen5-hscif renesas,hscif             A    Àq€        `         Î                  Ù   L   L   K         àfck brg_int scif_clk          	   ìdisabled          serial@c071c000       =    renesas,hscif-r8a78000 renesas,rcar-gen5-hscif renesas,hscif             A    ÀqÀ        `         Î                  Ù   L   L   K         àfck brg_int scif_clk          	   ìdisabled             timer             arm,armv8-timer       <   Î                                 
                  %  sec-phys phys virt hyp-phys hyp-virt          aliases         /soc/serial@c0710000          chosen          serial0:1843200n8         memory@60600000          Ememory           A    ``      _         memory@1080000000            Ememory           A   €       €         memory@1200000000            Ememory           A                    memory@1400000000            Ememory           A                    memory@1600000000            Ememory           A                    memory@1800000000            Ememory           A                    memory@1a00000000            Ememory           A                    memory@1c00000000            Ememory           A                    memory@1e00000000            Ememory           A                       	compatible #address-cells #size-cells interrupt-parent model cpu reg device_type next-level-cache phandle cache-unified cache-level #clock-cells clock-frequency ranges #interrupt-cells interrupt-controller interrupts clocks clock-names status uart-has-rtscts interrupt-names serial0 stdout-path 