 ,   8    (            B                              4    grinn,genio-700-sbc mediatek,mt8390 mediatek,mt8188                                  +         	   7embedded             DGrinn GenioSBC-700     aliases          J/soc/dp-intf@1c015000            S/soc/dp-intf@1c113000            \/soc/dsc@1c009000            a/soc/ethdr@1c114000          h/soc/mailbox@10320000            m/soc/mailbox@10330000            r/soc/merge0@1c014000             y/soc/merge@1c10c000          /soc/merge@1c10d000          /soc/merge@1c10e000          /soc/merge@1c10f000          /soc/merge@1c110000          /soc/mutex@1c016000          /soc/mutex@1c101000          /soc/padding@1c11d000            /soc/padding@1c11e000            /soc/padding@1c11f000            /soc/padding@1c120000            /soc/padding@1c121000            /soc/padding@1c122000            /soc/padding@1c123000            /soc/padding@1c124000            /soc/rdma@1c104000           /soc/rdma@1c105000          /soc/rdma@1c106000          /soc/rdma@1c107000          /soc/rdma@1c108000          )/soc/rdma@1c109000          4/soc/rdma@1c10a000          ?/soc/rdma@1c10b000          J/soc/i2c@11e00000           O/soc/mmc@11230000           T/soc/ethernet@11021000          ^/soc/i2c@11280000           c/soc/i2c@11281000           h/soc/i2c@11282000           m/soc/i2c@11ec0000           r/soc/i2c@11ec1000           w/soc/serial@11001100          cpus                         +       cpu@0           cpu           arm,cortex-a55                      psci            w5                                               @                              	   @                   (           9               M           \   	      cpu@100         cpu           arm,cortex-a55                     psci            w5                                               @                              	   @                   (           9               M           \   
      cpu@200         cpu           arm,cortex-a55                     psci            w5                                               @                              	   @                   (           9               M           \         cpu@300         cpu           arm,cortex-a55                     psci            w5                                               @                              	   @                   (           9               M           \         cpu@400         cpu           arm,cortex-a55                     psci            w5                                               @                              	   @                   (           9               M           \         cpu@500         cpu           arm,cortex-a55                     psci            w5                                               @                              	   @                   (           9               M           \         cpu@600         cpu           arm,cortex-a78                     psci                                                            @                              	   @                   (           9              M           \         cpu@700         cpu           arm,cortex-a78                     psci                                                            @                              	   @                   (           9              M           \         cpu-map    cluster0       core0           d   	      core1           d   
      core2           d         core3           d         core4           d         core5           d         core6           d         core7           d               idle-states         hpsci       cpu-off-l             arm,idle-state          u                       2           _          D        \         cpu-off-b             arm,idle-state          u                       -                             \         cluster-off-l             arm,idle-state          u                     7                     H        \         cluster-off-b             arm,idle-state          u                     2                             \            l2-cache0             cache                                    @                   (                    \         l2-cache1             cache                                    @                   (                    \         l3-cache              cache                                     @                            \            oscillator-13m            fixed-clock                      ]@        clk13m          \   7      oscillator-26m            fixed-clock                             clk26m          \   9      oscillator-32k            fixed-clock                                clk32k        opp-table-gpu             operating-points-v2          	        \   i   opp-390000000               >                 )         opp-431000000                                )         opp-473000000               1h@         	'        )         opp-515000000               F         	X        )         opp-556000000               !#          	h        )         opp-598000000               #         	<        )         opp-640000000               &%          	        )         opp-670000000               'c         
        )         opp-700000000               )'          
L        )         opp-730000000               +         
}        )         opp-760000000               -L          
`        )         opp-790000000               /q         
4        )         opp-835000000               1         (r        )         opp-880000000               4s          q        )         opp-915000000               6         X        )         opp-915000000-5             6                 )   0      opp-915000000-6             6         q        )   p      opp-950000000               8ـ         5         )         opp-950000000-5             8ـ         X        )   0      opp-950000000-6             8ـ         q        )   p         pmu-a55           arm,cortex-a55-pmu                      :                  pmu-a78           arm,cortex-a78-pmu                      :                  psci              arm,psci-1.0            smc       sound           E           Wokay          6    mediatek,mt8390-mt6359-evk mediatek,mt8188-mt6359-evb            Dmt8390-evk          ^default         l         t  vHeadphone Headphone L Headphone Headphone R AP DMIC AUDGLB AP DMIC MIC_BIAS_0 AP DMIC MIC_BIAS_2 DMIC_INPUT AP DMIC                  thermal-zones      cpu-little0-thermal                                        trips      trip-alert0          L                   ?passive         \         trip-alert1          s                   ?hot       trip-crit                              	   ?critical             cooling-maps       map0                     H     	   
                        cpu-little1-thermal                                       trips      trip-alert0          L                   ?passive         \         trip-alert1          s                   ?hot       trip-crit                              	   ?critical             cooling-maps       map0                     H     	   
                        cpu-little2-thermal                                       trips      trip-alert0          L                   ?passive         \         trip-alert1          s                   ?hot       trip-crit                              	   ?critical             cooling-maps       map0                     H     	   
                        cpu-little3-thermal                                       trips      trip-alert0          L                   ?passive         \         trip-alert1          s                   ?hot       trip-crit                              	   ?critical             cooling-maps       map0                     H     	   
                        cpu-big0-thermal                         d                 trips      trip-alert0          L                   ?passive         \         trip-alert1          s                   ?hot       trip-crit                              	   ?critical             cooling-maps       map0                                         cpu-big1-thermal                         d                 trips      trip-alert0          L                   ?passive         \         trip-alert1          s                   ?hot       trip-crit                              	   ?critical             cooling-maps       map0                                         apu-thermal                                        trips      trip-alert0          L                   ?passive       trip-alert1          s                   ?hot       trip-crit                              	   ?critical                gpu-thermal                                       trips      trip-alert0          L                   ?passive         \         trip-alert1          s                   ?hot       trip-crit                              	   ?critical             cooling-maps       map0                                       gpu1-thermal                                          trips      trip-alert0          L                   ?passive         \   !      trip-alert1          s                   ?hot       trip-crit                              	   ?critical             cooling-maps       map0               !                        adsp-thermal                                          trips      trip-alert0          L                   ?passive       trip-alert1          s                   ?hot       trip-crit                              	   ?critical                vdo-thermal                                       trips      trip-alert0          L                   ?passive       trip-alert1          s                   ?hot       trip-crit                              	   ?critical                infra-thermal                                         trips      trip-alert0          L                   ?passive       trip-alert1          s                   ?hot       trip-crit                              	   ?critical                cam1-thermal                                          trips      trip-alert0          L                   ?passive       trip-alert1          s                   ?hot       trip-crit                              	   ?critical                cam2-thermal                                          trips      trip-alert0          L                   ?passive       trip-alert1          s                   ?hot       trip-crit                              	   ?critical                   timer             arm,armv8-timer                   @  :                                             
                ]@      soc                      +             simple-bus                                             performance-controller@11bc10             mediatek,cpufreq-hw                           0                          \         interrupt-controller@c000000              arm,gic-v3                     '                        >                                             :      	               \      ppi-partitions     interrupt-partition-0           S   	   
                    \         interrupt-partition-1           S              \               syscon@10000000            mediatek,mt8188-topckgen syscon                                          \   %      syscon@10001000       #    mediatek,mt8188-infracfg-ao syscon                                          \           \   &      syscon@10003000           mediatek,mt8188-pericfg syscon               0                           \   H      pinctrl@10005000              mediatek,mt8188-pinctrl       `       P                                                                               0  iiocfg0 iocfg_rm iocfg_lt iocfg_lm iocfg_rt eint          s                      "                    >        :                                RPI_GPIO0 RPI_GPIO1   RPI_GPIO4  RPI_GPIO6   RPI_GPIO9 RPI_GPIO10 RPI_GPIO11          RPI_GPIO21  RPI_GPIO23       RPI_GPIO30     RPI_GPIO35 RPI_GPIO36                   RPI_GPIO55 RPI_GPIO56   RPI_GPIO59 RPI_GPIO60         RPI_GPIO69   RPI_GPIO72 RPI_GPIO73 RPI_GPIO74     RPI_GPIO79 RPI_GPIO80 RPI_GPIO81 RPI_GPIO82                                       RPI_GPIO121 RPI_GPIO122 RPI_GPIO123 RPI_GPIO124         \   "   i2c1-pins           \   c   pins              :  9                              mmc0-default-pins           \   S   pins-clk                                    f      pins-cmd-dat          $                                                   e      pins-rst                                    e         mmc0-uhs-pins           \   T   pins-clk                                    f      pins-cmd-dat          $                                                   e      pins-ds                                 f      pins-rst                                    e         i2c0-pins           \   X   pins              8  7                              i2c2-pins           \   Y   pins              <  ;                              i2c3-pins           \   Z   pins              >  =                              i2c5-pins           \   e   pins              B  A                              i2c6-pins           \   f   pins              D  C                              uart0-pins          \   A   pins                                   uart1-pins          \   B   pins              V  W                  uart2-pins          \   C   pins              #  $                  pcie-default            \   a   mux           /  0  1                  eth-default-pins            \   Q   pins-cc                                  pins-mdio                                         pins-power                               pins-rxd                                     pins-txd                                        eth-sleep-pins          \   R   pins-cc                           pins-mdio                                         pins-rxd                              pins-txd                                 spi2-pins           \   E   pins-spi              O  P  Q  R                  audio-default-pins          \      pins-cmd-dat              y  z  {  |         usb-default-pins            \   ]   pins-valid            U                     syscon@10006000       )    mediatek,mt8188-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8188-power-controller                         +            )           \   :   power-domain@0                                   +            )           =   #   power-domain@1                     K   $      %           Rmfg alt         ^   &                     +            )           =   '   power-domain@2                     )          power-domain@3                     )          power-domain@4                     )                power-domain@15                    K   %      %      %      %   
   %   3   %   4   %   =   %      %      (      (      (      (      (      (      (      (      (      (      (      (      (      (      (      (      (      (      (            Rtop cam ccu img venc vdec wpe cfgck cfgxo ss-sram-cmn ss-sram-v0l0 ss-sram-v0l1 ss-sram-ve0 ss-sram-ve1 ss-sram-ifa ss-sram-cam ss-sram-v1l5 ss-sram-v1l6 ss-sram-rdr ss-iommu ss-imgcam ss-emi ss-subcmn-rdr ss-rsi ss-cmn-l4 ss-vdec1 ss-wpe ss-cvdo-ve1          ^   &                     +            )      power-domain@16                  H  K   %      %      )      )      )      )      )      )      )         A  Rcfgck cfgxo ss-gals ss-cmn ss-emi ss-iommu ss-larb ss-rsi ss-bus            ^   &                     +            )      power-domain@20                  0  K   %      %      *      *      *      *         8  Rcfgck cfgxo ss-vpp1-g5 ss-vpp1-g6 ss-vpp1-l5 ss-vpp1-l6         ^   &        )          power-domain@22                    K   +            Rss-vdec1-soc-l1         ^   &                     +            )      power-domain@23                    K   ,            Rss-vdec2-l1         ^   &        )             power-domain@29                     K   %      %      %   	   %           Rcam ccu bus cfgck           ^   &                     +            )      power-domain@30                  (  K   -       -      -      -      -         6  Rss-cam-l13 ss-cam-l14 ss-cam-mm0 ss-cam-mm1 ss-camsys           ^   &                     +            )      power-domain@32                     K   -      .       /          $  Rss-camb-sub ss-camb-raw ss-camb-yuv         )          power-domain@31                    K   -      0       1          $  Rss-cama-sub ss-cama-raw ss-cama-yuv         )                power-domain@17                  (  K   %      %      2       2      2         &  Rcfgck cfgxo ss-larb2 ss-larb3 ss-gals           ^   &                     +            )      power-domain@9             	        K   %   @   %   ?      	  Rbus hdcp            ^   &        )          power-domain@18                    ^   &        )          power-domain@19                    ^   &        )             power-domain@24                     K   3       3      3      3         0  Rss-ve1-larb ss-ve1-core ss-ve1-gals ss-ve1-sram         ^   &        )          power-domain@21                    K   4      4           Rss-wpe-l7 ss-wpe-l7pce          ^   &        )                power-domain@5                     ^   &        K   5           Rss-pextp-fmem           )          power-domain@7                     K   %   0   %   1        Rseninf0 seninf1         )          power-domain@6                     )          power-domain@10            
        K   %   E   %   D      	  Rbus main            ^   &                     +            )      power-domain@11                    ^   &                     +            )      power-domain@14                    K   %   F        Rasm         ^   &        )          power-domain@13                    K   %   S   %      6            Ra1sys intbus adspck         ^   &        )          power-domain@12                    ^   &        )                power-domain@8                     K   5         	  Rethermac            ^   &        )                watchdog@10007000             mediatek,mt8188-wdt              p                 p        \           \   ;      syscon@1000c000       "    mediatek,mt8188-apmixedsys syscon                                           \   $      timer@10017000        ,    mediatek,mt8188-timer mediatek,mt6765-timer             p                :      	               K   7      pwrap@10024000        3    mediatek,mt8188-pwrap mediatek,mt8195-pwrap syscon              @                ipwrap           :                      K   &      &          	  Rspi wrap       pmic              mediatek,mt6359          >                                  "        :                 "         adc           mediatek,mt6359-auxadc                   audio-codec           mediatek,mt6359-codec         regulators            mediatek,mt6359-regulator      buck_vs1            vs1          5          !                           buck_vgpu11       
  dvdd_core                     7        .                     C                         buck_vmodem         vmodem                            .  *                 buck_vpu          
  dvdd_adsp                     7        .                     C                         buck_vcore          dvdd_proc_l                            .                     C                         buck_vs2            vs2          5          j                            buck_vpa            vpa_pmu                    /M`          ,      buck_vproc2         vgpu             dp         5         .  L                   C                  [   '        r  j        \   #      buck_vproc1         vproc1                    7        .  L                   C                buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub                      7      ldo_vaud18          vaud18           w@         w@                 ldo_vsim1         
  vsim1_pmu                     /M`                ldo_vibr            vibr             O         2Z      ldo_vrf12           va12_abb2_pmu                                     ldo_vusb            vusb             -         -                           \   I      ldo_vsram_proc2         vsram_proc2                            .  L                          ldo_vio18           vio18                                              ldo_vcamio          vcamio                          ldo_vcn18         
  vcn18_pmu            w@         w@                          ldo_vfe28           vfe28            *         *           x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_bt           *         5g      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@                          ldo_vsram_others          
  vsram_gpu            q         5         .                     [   #        r  j        \   '      ldo_vefuse          vefuse                          ldo_vxo22           vxo22            w@         !               ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *                 ldo_vio28           vio28            *         2Z               ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z        \   U      ldo_vcn33_2_bt          vcn33_2_pmu          *         5g               ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                         ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                               .  *                 ldo_vufs            vufs18_pmu                                     \   V      ldo_vm18            vm18                                     ldo_vbbck           vbbck                     O               ldo_vsram_proc1         vsram_proc1                            .  L                          ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              rtc           mediatek,mt6358-rtc       keys              mediatek,mt6359-keys                              power-key              t                        spmi@10027000         *    mediatek,mt8188-spmi mediatek,mt8195-spmi                p                            ipmif spmimst               %   8           %           K   &      &       %   8      (  Rpmif_sys_ck pmif_tmr_ck spmimst_clk_mux       iommu@10315000            mediatek,mt8188-iommu-infra             1P                :                                \   _      mailbox@10320000              mediatek,mt8188-gce             2        @         :                                 K   &           \   j      mailbox@10330000              mediatek,mt8188-gce             3        @         :                                 K   &           \   l      scp@10720000              mediatek,mt8188-scp-dual                r                 icfg                      +                   P             Wokay       scp@0             mediatek,scp-core                          isram            :                     Wokay               8        \   m      scp@d0000             mediatek,scp-core                        isram            :                   	  Wdisabled             audio-controller@10b10000             mediatek,mt8188-afe                                 %   S           %           K   9   $   	   $   
   %      %      %      %      %      %   S   %      %       %   E   %   Q   %   M   %   N   %   O   %   P   6       %      %      %      %   T   %   R        Rclk26m apll1 apll2 apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 top_a1sys_hp top_aud_intbus top_audio_h top_audio_local_bus top_dptx top_i2so1 top_i2so2 top_i2si1 top_i2si2 adsp_audio_26m apll1_d4 apll2_d4 apll12_div4 top_a2sys top_aud_iec          :      6               &   :           4   ;         	  ;audiosys            ^   &        G   %        Wokay               <        \         adsp@10b80000             mediatek,mt8188-dsp       @                                                             icfg sram sec bus               %   D        K   %   D   %   E        Raudiodsp adsp_bus           Y   =   >        `rx tx           &   :           Wokay               ?   @        \         mailbox@10b86100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox             a                :                                 \   =      mailbox@10b87100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox             q                :                                 \   >      clock-controller@10b91100             mediatek,mt8188-adsp-audio26m                                          \   6      serial@11001100       *    mediatek,mt8188-uart mediatek,mt6577-uart                                :                      K   9   &         	  Rbaud bus            Wokay            ^default         l   A      serial@11001200       *    mediatek,mt8188-uart mediatek,mt6577-uart                                :                      K   9   &         	  Rbaud bus            Wokay            ^default         l   B      serial@11001300       *    mediatek,mt8188-uart mediatek,mt6577-uart                                :                      K   9   &         	  Rbaud bus            Wokay            ^default         l   C      serial@11001400       *    mediatek,mt8188-uart mediatek,mt6577-uart                                :                     K   9   &         	  Rbaud bus          	  Wdisabled          adc@11002000          .    mediatek,mt8188-auxadc mediatek,mt8173-auxadc                                 K   &           Rmain                     	  Wdisabled          syscon@11003000       "    mediatek,mt8188-pericfg-ao syscon                0                           \   5      spi@1100a000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 :                      K   %   y   %      &           Rparent-clk sel-clk spi-clk        	  Wdisabled          thermal-sensor@1100b000           mediatek,mt8188-lvts-ap                              :                      K   &           4   &           k   D        wlvts-calib-data-1                      \         pwm@1100e000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm                                K   %   '   &   /        Rmain mm         :                               	  Wdisabled          pwm@1100f000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm                                K   %   (   &   F        Rmain mm         :                              	  Wdisabled          spi@11010000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 :                      K   %   y   %      &   2        Rparent-clk sel-clk spi-clk        	  Wdisabled          spi@11012000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 :                      K   %   y   %      &   3        Rparent-clk sel-clk spi-clk          Wokay            ^default         l   E                  spi@11013000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                0                :                      K   %   y   %      &   4        Rparent-clk sel-clk spi-clk        	  Wdisabled          spi@11018000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                :                      K   %   y   %      &   8        Rparent-clk sel-clk spi-clk        	  Wdisabled          spi@11019000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                :                      K   %   y   %      &   9        Rparent-clk sel-clk spi-clk        	  Wdisabled          usb@11201000          #    mediatek,mt8188-mtu3 mediatek,mtu3                       -     >              	  imac ippc                                 ?                      +           :                         %   )           %   v        K   5   	   %      5   
        Rsys_ck ref_ck mcu_ck               F      G                       H  h           Wokay            host            super-speed            I   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 imac         :                         %   *           %   v        K   5   
        Rsys_ck          Wokay                         +               I   hub@1             usb451,8027                       J           "                  K        \   L      hub@2             usb451,8025                       L           "                  K        \   J            ethernet@11021000         ;    mediatek,mt8188-gmac mediatek,mt8195-gmac snps,dwmac-5.10a                     @         :                     macirq        0  K   5       5      %   A   %   B   %   C   5         .  Raxi apb mac_main ptp_ref rmii_internal mac_cg              %   A   %   B   %   C           %      %      %           &   :           -   &        >   M        N   N        a   O        t                                  Wokay          	  rgmii-id               P        ^default sleep           l   Q           R                                           * @        	   "         mdio              snps,dwmac-mdio                      +       ethernet-phy@3            ethernet-phy-ieee802.3-c22                        "               	        \   P         stmmac-axi-config           	'                                 	1           	A           \   M      rx-queues-config            	Q            	g        \   N   queue0           	x        	          queue1           	x        	          queue2           	x        	          queue3           	x        	             tx-queues-config            	            	        \   O   queue0           	x        	            	         queue1           	x        	           	         queue2           	x        	           	         queue3           	x        	           	               mmc@11230000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              #                              :                       K   %      &      &      &   M      !  Rsource hclk source_cg crypto_clk            Wokay            ^default state_uhs           l   S           T        	           	          	         
         
         
-         
:         
K         
S        
Y H        
h   U        
t   V         
      mmc@11240000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              $                              :                      K   %      &      &   $        Rsource hclk source_cg              %              %         	  Wdisabled          mmc@11250000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              %                              :                      K   %      &      &   A        Rsource hclk source_cg              %              %         	  Wdisabled          thermal-sensor@11278000           mediatek,mt8188-lvts-mcu                '                :                      K   &           4   &            k   D        wlvts-calib-data-1                      \         i2c@11280000              mediatek,mt8188-i2c              (             "                :                      
           K   W       &   7      	  Rmain dma                         +            Wokay            ^default         l   X               i2c@11281000              mediatek,mt8188-i2c              (            "               :                      
           K   W      &   7      	  Rmain dma                         +            Wokay            ^default         l   Y               i2c@11282000              mediatek,mt8188-i2c              (             "               :                      
           K   W      &   7      	  Rmain dma                         +            Wokay            ^default         l   Z               clock-controller@11283000             mediatek,mt8188-imp-iic-wrap-c              (0                           \   W      usb@112a1000          #    mediatek,mt8188-mtu3 mediatek,mtu3               *       -    *>              	  imac ippc                        *        ?                      +           :                        %   -           %   v        K   5      %      5           Rsys_ck ref_ck mcu_ck               [                       H  p           Wokay            host            high-speed             I   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 imac         :                        %   .           %   v        K   5           Rsys_ck          Wokay                         +               I   hub@1             microchip,usb2513bi                       K            usb@112b1000          #    mediatek,mt8188-mtu3 mediatek,mtu3               +       -    +>              	  imac ippc                        +        ?                      +           :                        %   ,           %   v        K   5      %      5           Rsys_ck ref_ck mcu_ck               \                       H  `           Wokay            peripheral          ^default         l   ]           I   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 imac         :                        %   +           %   v        K   5           Rsys_ck        	  Wdisabled             pcie@112f0000         *    mediatek,mt8188-pcie mediatek,mt8192-pcie               /                	  ipcie-mac                                              
               pci         
                         +         0  K   &   L   &   #   &   &   &   +   &   C   5         /  Rpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                     :                   `  
                  ^                      ^                     ^                     ^           
                       
       _              
               `         	  
pcie-phy            &   :           4   ;           ;mac         Wokay            ^default         l   a   interrupt-controller                                     >        \   ^         spi@1132c000          (    mediatek,mt8188-nor mediatek,mt8186-nor             2                K   %   X   5      5           Rspi sf axi             %   X        :      9                            +          	  Wdisabled          t-phy@11c20700        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                                            +           &   :           Wokay       pcie-phy@0                         K   %           Rref         
           \   `         dsi-phy@11c80000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx                              K   9        mipi_tx0_pll                        
          	  Wdisabled            \         dsi-phy@11c90000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx                              K   9        mipi_tx0_pll                        
          	  Wdisabled            \         i2c@11e00000              mediatek,mt8188-i2c                           "                :                      
           K   b       &   7      	  Rmain dma                         +            Wokay            ^default         l   c               i2c@11e01000              mediatek,mt8188-i2c                          "               :                      
           K   b      &   7      	  Rmain dma                         +          	  Wdisabled          clock-controller@11e02000             mediatek,mt8188-imp-iic-wrap-w                                          \   b      t-phy@11e30000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                Wokay       usb-phy@0                          K   %      $           Rref da_ref          
           \   \         t-phy@11e40000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                Wokay       usb-phy@0                          K   %      $           Rref da_ref          
           \   F      usb-phy@700                       K   $      9        Rref da_ref          
           \   G         t-phy@11e80000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                Wokay       usb-phy@0                          K   %      $           Rref da_ref          
           \   [         i2c@11ec0000              mediatek,mt8188-i2c                           "               :                      
           K   d       &   7      	  Rmain dma                         +            Wokay            ^default         l   e               i2c@11ec1000              mediatek,mt8188-i2c                          "                :                      
           K   d      &   7      	  Rmain dma                         +            Wokay            ^default         l   f               clock-controller@11ec2000              mediatek,mt8188-imp-iic-wrap-en                                         \   d      efuse@11f20000        ,    mediatek,mt8188-efuse mediatek,mt8186-efuse                                           +      dp-calib@1a0                         \         lvts1-calib@1ac              @        \   D      gpu-speedbin@581                                        \   h      socinfo-data1@7a0                      socinfo-data2@7e0                         gpu@13000000          )    mediatek,mt8188-mali arm,mali-valhall-jm                         @         K   g          0  :                   ~             }               job mmu gpu         k   h      
  wspeed-bin              i        &   :      :      :           core0 core1 core2           M           Wokay            /   #        \          clock-controller@13fbf000             mediatek,mt8188-mfgcfg                                         \   g      syscon@14000000           mediatek,mt8188-vppsys0 syscon                                           \   (      dma-controller@14001000           mediatek,mt8188-mdp3-rdma                                ;           K   (         <  Y   j         j         j         j         j              F   k           &   :           M   l                  e              y   m      display@14002000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                               K   (            M   l                 display@14004000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                @                K   (   "        M   l      @          display@14005000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal                P                :      F               K   (   
        &   :           M   l      P          display@14006000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                K   (           M   l      `            e    %      display@14007000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                p                K   (   #        M   l      p          display@14008000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                                :      I               K   (   $        &   :           M   l                display@14009000          2    mediatek,mt8188-mdp3-ovl mediatek,mt8195-mdp3-ovl                                :      J               K   (   %        &   :           M   l                  F   k         display@1400a000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                                K   (           &   :           M   l                display@1400b000          2    mediatek,mt8188-mdp3-tcc mediatek,mt8195-mdp3-tcc                                K   (           M   l                display@1400c000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot                              ;           K   (           F   k           &   :           M   l                  e    +      mutex@1400f000            mediatek,mt8188-vpp-mutex                                :      P               K   (           &   :           M   l                smi@14012000              mediatek,mt8188-smi-common-vpp                               K   (      (           Rapb smi         &   :           \   n      smi@14013000              mediatek,mt8188-smi-larb                0                K   (      (           Rapb smi         &   :                         n        \   q      iommu@14018000            mediatek,mt8188-iommu-vpp                      P         K   (           Rbclk            :      R               &   :                         o   p   q   r   s   t        \   k      dma-controller@14f09000           mediatek,mt8188-mdp3-rdma                               ;           K   *   
        F   u           &   :           M   l   	              e          dma-controller@14f0a000           mediatek,mt8188-mdp3-rdma                               ;           K   *           F   k           &   :           M   l   	              e          display@14f0c000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                             K   *           M   l   	            display@14f0d000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                             K   *           M   l   	            display@14f0f000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                               K   *   "        M   l   	            display@14f10000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                                K   *   $        M   l   
             display@14f12000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal                                :      j               K   *   #        &   :           M   l   
             display@14f13000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal               0                :      k               K   *   %        &   :           M   l   
  0          display@14f15000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz               P                K   *           M   l   
  P            e          display@14f16000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz               `                K   *           M   l   
  `            e          display@14f18000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                               K   *           M   l   
            display@14f19000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                               K   *           M   l   
            display@14f1a000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge                               K   *           &   :           M   l   
            display@14f1b000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge                               K   *           &   :           M   l   
            display@14f1d000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                               :      u               K   *           &   :           M   l   
            display@14f1e000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                               :      v               K   *           &   :           M   l   
            display@14f21000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                               K   *           &   :           M   l               display@14f22000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                                K   *           &   :           M   l                display@14f24000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot             @                ;           K   *           F   u           &   :           M   l     @            e          display@14f25000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot             P                ;           K   *           F   k           &   :           M   l     P            e          clock-controller@14e00000             mediatek,mt8188-wpesys                                          \   4      clock-controller@14e02000             mediatek,mt8188-wpesys-vpp0                                       smi@14e04000              mediatek,mt8188-smi-larb                @                K   4      4           Rapb smi         &   :                         n        \   s      syscon@14f00000           mediatek,mt8188-vppsys1 syscon                                          \   *      mutex@14f01000            mediatek,mt8188-vpp-mutex                               :      {               K   *   &        &   :           M   l   	            smi@14f02000              mediatek,mt8188-smi-larb                                 K   *      *           Rapb smi         &   :                         v        \         smi@14f03000              mediatek,mt8188-smi-larb                0                K   *      *           Rapb smi         &   :                         n        \   r      clock-controller@15000000             mediatek,mt8188-imgsys                                         clock-controller@15110000              mediatek,mt8188-imgsys1-dip-top                                         \         clock-controller@15130000             mediatek,mt8188-imgsys1-dip-nr                                          \         clock-controller@15220000             mediatek,mt8188-imgsys-wpe1             "                            \         clock-controller@15330000             mediatek,mt8188-ipesys              3                            \         clock-controller@15520000             mediatek,mt8188-imgsys-wpe2             R                            \         clock-controller@15620000             mediatek,mt8188-imgsys-wpe3             b                            \         clock-controller@16000000             mediatek,mt8188-camsys                                           \   -      clock-controller@1604f000             mediatek,mt8188-camsys-rawa                                        \           \   0      clock-controller@1606f000             mediatek,mt8188-camsys-yuva                                        \           \   1      clock-controller@1608f000             mediatek,mt8188-camsys-rawb                                        \           \   .      clock-controller@160af000             mediatek,mt8188-camsys-yuvb             
                           \           \   /      clock-controller@17200000             mediatek,mt8188-ccusys                                         video-decoder@18000000            mediatek,mt8188-vcodec-dec                              @                                    `         F   k                       +           y   m   video-codec@10000             mediatek,mtk-vcodec-lat                                  %   4           %   x         K   %   4   +      +      %   x        Rsel vdec lat top            :                   H  F   k     k     k     k     k     k     k     k     k          &   :         video-codec@25000             mediatek,mtk-vcodec-core                 P                   %   4           %   x         K   %   4   ,      ,      %   x        Rsel vdec lat top            :                   X  F   u     u     u     u     u     u     u     u     u     u     u          &   :            smi@1800d000              mediatek,mt8188-smi-larb                                 K   +       +            Rapb smi         &   :                         n        \   t      clock-controller@1800f000             mediatek,mt8188-vdecsys-soc                                         \   +      smi@1802e000              mediatek,mt8188-smi-larb                                K   ,       ,            Rapb smi         &   :                         v        \         clock-controller@1802f000             mediatek,mt8188-vdecsys                                        \   ,      clock-controller@1a000000             mediatek,mt8188-vencsys                                          \   3      smi@1a010000              mediatek,mt8188-smi-larb                                 K   3      3           Rapb smi         &   :                         v        \         video-encoder@1a020000            mediatek,mt8188-vcodec-enc                                            +              %   3           %   p        K   3         	  Rvenc_sel            :      a             X  F   u     u     u     u     u     u     u     u     u     u     u          &   :           y   m      jpeg-encoder@1a030000         +    mediatek,mt8188-jpgenc mediatek,mtk-jpgenc                               K   3           Rjpgenc          :      b                F   u     u     u     u          &   :         jpeg-decoder@1a040000         .    mediatek,mt8188-jpgdec mediatek,mt2701-jpgdec                                K   3       3           Rjpgdec-smi jpgdec           :      c             0  F   u     u     u     u     u     u          &   :         ovl@1c000000          2    mediatek,mt8188-disp-ovl mediatek,mt8195-disp-ovl                                 K   )            :      |               F   u           &   :           M   j             ports                        +       port@0                 endpoint             port@1                endpoint               w        \   x               rdma@1c002000         4    mediatek,mt8188-disp-rdma mediatek,mt8195-disp-rdma                               K   )           :      ~               F   k            &   :           M   j             ports                        +       port@0                 endpoint               x        \   w         port@1                endpoint               y        \   z               color@1c003000        6    mediatek,mt8188-disp-color mediatek,mt8173-disp-color                0                K   )           :                     &   :           M   j     0       ports                        +       port@0                 endpoint               z        \   y         port@1                endpoint               {        \   |               ccorr@1c004000        6    mediatek,mt8188-disp-ccorr mediatek,mt8192-disp-ccorr                @                K   )           :                     &   :           M   j     @       ports                        +       port@0                 endpoint               |        \   {         port@1                endpoint               }        \   ~               aal@1c005000          2    mediatek,mt8188-disp-aal mediatek,mt8183-disp-aal                P                K   )           :                     &   :           M   j     P       ports                        +       port@0                 endpoint               ~        \   }         port@1                endpoint                       \                  gamma@1c006000        6    mediatek,mt8188-disp-gamma mediatek,mt8195-disp-gamma                `                K   )           :                     &   :           M   j     `       ports                        +       port@0                 endpoint                       \            port@1                endpoint                   dither@1c007000       8    mediatek,mt8188-disp-dither mediatek,mt8183-disp-dither              p                K   )           :                     &   :           M   j     p       ports                        +       port@0                 endpoint             port@1                endpoint                   dsi@1c008000              mediatek,mt8188-dsi                              K   )      )              Rengine digital hs           :                                
dphy            &   :           4   )         	  Wdisabled          dsc@1c009000          2    mediatek,mt8188-disp-dsc mediatek,mt8195-disp-dsc                                K   )   
        :                     &   :           M   j               dsi@1c012000              mediatek,mt8188-dsi                              K   )   	   )              Rengine digital hs           :                                
dphy            &   :           4   )   	      	  Wdisabled          merge0@1c014000       6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge               @                K   )      2           Rmerge merge_async           :                     &   :           M   j     @          dp-intf@1c015000              mediatek,mt8188-dp-intf             P                K   )       )      $           Rpixel engine pll            :                     &   :         	  Wdisabled          mutex@1c016000            mediatek,mt8188-disp-mutex              `                K   )           :                     &   :           M   j     `            e  >      postmask@1c01a000         <    mediatek,mt8188-disp-postmask mediatek,mt8192-disp-postmask                             K   )           :                     &   :           M   j            ports                        +       port@0                 endpoint             port@1                endpoint                   syscon@1c01d000           mediatek,mt8188-vdosys0 syscon                                         \           Y   j               M   j                 \   )      smi@1c022000              mediatek,mt8188-smi-larb                                 K   )      )           Rapb smi         &   :                          v        \         smi@1c023000              mediatek,mt8188-smi-larb                0                K   )      )           Rapb smi         &   :                         n        \   o      smi@1c024000              mediatek,mt8188-smi-common-vdo              @                K   )      )           Rapb smi         &   :           \   v      iommu@1c028000            mediatek,mt8188-iommu-vdo                      P         K   )           Rbclk            :                     &   :                                             \   u      syscon@1c100000           mediatek,mt8188-vdosys1 syscon                                          \           Y   j              M   j                  \   2      mutex@1c101000            mediatek,mt8188-disp-mutex                              K   2           :                     &   :           M   j                 e        smi@1c102000              mediatek,mt8188-smi-larb                                 K   2       2            Rapb smi         &   :                         v        \         smi@1c103000              mediatek,mt8188-smi-larb                0                K   2      2           Rapb smi         &   :                         n        \   p      rdma@1c104000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             @                K   2           :                     F   u   @        &   :           ;           M   j     @          rdma@1c105000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             P                K   2           :                     F   k   `        &   :           ;           M   j     P          rdma@1c106000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             `                K   2           :                     F   u   A        &   :           ;           M   j     `          rdma@1c107000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             p                K   2           :                     F   k   a        &   :           ;           M   j     p          rdma@1c108000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             K   2           :                     F   u   B        &   :           ;           M   j               rdma@1c109000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             K   2           :                     F   k   b        &   :           ;           M   j               rdma@1c10a000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             K   2           :                     F   u   C        &   :           ;           M   j               rdma@1c10b000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             K   2           :                     F   k   c        &   :           ;           M   j               merge@1c10c000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               K   2   	   2           Rmerge merge_async           :                     &   :           4   2           M   j                        merge@1c10d000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               K   2   
   2           Rmerge merge_async           :                     &   :           4   2           M   j                        merge@1c10e000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               K   2      2           Rmerge merge_async           :                     &   :           4   2           M   j                        merge@1c10f000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               K   2      2           Rmerge merge_async           :                     &   :           4   2           M   j                        merge@1c110000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                                K   2      2           Rmerge merge_async           :                     &   :           4   2           M   j                         dp-intf@1c113000              mediatek,mt8188-dp-intf             0                K   2   :   2      $           Rpixel engine pll            :                     &   :         	  Wdisabled          ethdr@1c114000        6    mediatek,mt8188-disp-ethdr mediatek,mt8195-disp-ethdr         p      @            P            p                                                              4  imixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       h  K   2   0   2   +   2   .   2   ,   2   /   2   -   2   <   2   1   2   2   2   3   2   4   2   5   %           Rmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          :      6               F   k   d   k   e        &   :         (  4   2   1   2   2   2   3   2   4   2   5      p  M   j     @       j     P       j     p       j            j            j            j               padding@1c11d000              mediatek,mt8188-disp-padding                                K   2           &   :           M   j               padding@1c11e000              mediatek,mt8188-disp-padding                                K   2            &   :           M   j               padding@1c11f000              mediatek,mt8188-disp-padding                                K   2   !        &   :           M   j               padding@1c120000              mediatek,mt8188-disp-padding                                 K   2   "        &   :           M   j                padding@1c121000              mediatek,mt8188-disp-padding                                K   2   #        &   :           M   j               padding@1c122000              mediatek,mt8188-disp-padding                                 K   2   $        &   :           M   j                padding@1c123000              mediatek,mt8188-disp-padding                0                K   2   %        &   :           M   j     0          padding@1c124000              mediatek,mt8188-disp-padding                @                K   2   &        &   :           M   j     @          edp-tx@1c500000           mediatek,mt8188-edp-tx              P                 :                     k           wdp_calibration_data         &   :                   	  Wdisabled          dp-tx@1c600000            mediatek,mt8188-dp-tx               `                 :                     k           wdp_calibration_data         &   :                   	  Wdisabled             chosen          serial0:921600n8          firmware       optee             linaro,optee-tz         smc          reserved-memory                      +               optee@43200000                       C                memory@50000000           shared-dma-pool             P                          \   8      memory@54600000                      T`                memory@55000000           shared-dma-pool             U       @        memory@57000000           shared-dma-pool             W       @        memory@60000000           shared-dma-pool             `                           \   @      memory@60f00000           shared-dma-pool             `                          \   <      memory@61000000           shared-dma-pool             a                           \   ?         regulator-vsys            regulator-fixed         vsys                              \         regulator-0           regulator-fixed       
  fixed-5v0            LK@         LK@         $                 7         regulator-1           regulator-fixed       
  fixed-4v2            @@         @@         $                 7         regulator-2           regulator-fixed       
  fixed-3v3            2Z         2Z         $                 7           \   K      memory@40000000         memory              @                   	compatible interrupt-parent #address-cells #size-cells chassis-type model dp-intf0 dp-intf1 dsc0 ethdr0 gce0 gce1 merge0 merge1 merge2 merge3 merge4 merge5 mutex0 mutex1 padding0 padding1 padding2 padding3 padding4 padding5 padding6 padding7 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c1 mmc0 ethernet0 i2c0 i2c2 i2c3 i2c5 i2c6 serial0 device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-output-names opp-shared opp-hz opp-microvolt opp-supported-hw interrupts mediatek,platform status pinctrl-names pinctrl-0 audio-routing mediatek,adsp polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux bias-pull-up drive-strength-microamp drive-strength bias-pull-down input-enable output-high input-disable bias-disable #power-domain-cells domain-supply clocks clock-names mediatek,infracfg mediatek,disable-extrst #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread mediatek,long-press-mode power-off-time-sec linux,keycodes wakeup-source assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells memory-region power-domains resets reset-names mediatek,topckgen mboxes mbox-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select phys mediatek,syscon-wakeup dr_mode maximum-speed vusb33-supply peer-hub reset-gpios vdd-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,mac-wol mediatek,tx-delay-ps snps,reset-active-low snps,reset-delays-us snps,reset-gpio eee-broken-1000t snps,blen snps,rd_osr_lmt snps,wr_osr_lmt snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,priority snps,weight bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v supports-cqe cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable clock-div bus-range linux,pci-domain interrupt-map interrupt-map-mask iommu-map iommu-map-mask phy-names #phy-cells bits operating-points-v2 power-domain-names mali-supply #dma-cells iommus mediatek,gce-client-reg mediatek,gce-events mediatek,scp mediatek,larb-id mediatek,smi mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz stdout-path no-map regulator-boot-on enable-active-high vin-supply 