    8 x   (            
M @                             $    mediatek,mt8188-evb mediatek,mt8188                                  +         !   7MediaTek MT8188 evaluation board       aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dsc@1c009000            T/soc/ethdr@1c114000          [/soc/mailbox@10320000            `/soc/mailbox@10330000            e/soc/merge0@1c014000             l/soc/merge@1c10c000          s/soc/merge@1c10d000          z/soc/merge@1c10e000          /soc/merge@1c10f000          /soc/merge@1c110000          /soc/mutex@1c016000          /soc/mutex@1c101000          /soc/padding@1c11d000            /soc/padding@1c11e000            /soc/padding@1c11f000            /soc/padding@1c120000            /soc/padding@1c121000            /soc/padding@1c122000            /soc/padding@1c123000            /soc/padding@1c124000            /soc/rdma@1c104000           /soc/rdma@1c105000           /soc/rdma@1c106000          /soc/rdma@1c107000          /soc/rdma@1c108000          /soc/rdma@1c109000          '/soc/rdma@1c10a000          2/soc/rdma@1c10b000          =/soc/serial@11001100            E/soc/i2c@11280000           J/soc/i2c@11e00000           O/soc/i2c@11281000           T/soc/i2c@11282000           Y/soc/i2c@11e01000           ^/soc/i2c@11ec0000           c/soc/i2c@11ec1000           h/soc/mmc@11230000         cpus                         +       cpu@0           mcpu           arm,cortex-a55          y            }psci            w5                                               @                                 @        	                      '               ;           J   	      cpu@100         mcpu           arm,cortex-a55          y           }psci            w5                                               @                                 @        	                      '               ;           J   
      cpu@200         mcpu           arm,cortex-a55          y           }psci            w5                                               @                                 @        	                      '               ;           J         cpu@300         mcpu           arm,cortex-a55          y           }psci            w5                                               @                                 @        	                      '               ;           J         cpu@400         mcpu           arm,cortex-a55          y           }psci            w5                                               @                                 @        	                      '               ;           J         cpu@500         mcpu           arm,cortex-a55          y           }psci            w5                                               @                                 @        	                      '               ;           J         cpu@600         mcpu           arm,cortex-a78          y           }psci                                                            @                                 @        	                      '              ;           J         cpu@700         mcpu           arm,cortex-a78          y           }psci                                                            @                                 @        	                      '              ;           J         cpu-map    cluster0       core0           R   	      core1           R   
      core2           R         core3           R         core4           R         core5           R         core6           R         core7           R               idle-states         Vpsci       cpu-off-l             arm,idle-state          c            z           2           _          D        J         cpu-off-b             arm,idle-state          c            z           -                             J         cluster-off-l             arm,idle-state          c          z           7                     H        J         cluster-off-b             arm,idle-state          c          z           2                             J            l2-cache0             cache                                    @                                       J         l2-cache1             cache                                    @                                       J         l3-cache              cache                                     @                            J            oscillator-13m            fixed-clock                      ]@        clk13m          J   3      oscillator-26m            fixed-clock                             clk26m          J   5      oscillator-32k            fixed-clock                                clk32k        opp-table-gpu             operating-points-v2                  J   [   opp-390000000               >        	                  opp-431000000                       	                  opp-473000000               1h@        	 	'                 opp-515000000               F        	 	X                 opp-556000000               !#         	 	h                 opp-598000000               #        	 	<                 opp-640000000               &%         	 	                 opp-670000000               'c        	 
                 opp-700000000               )'         	 
L                 opp-730000000               +        	 
}                 opp-760000000               -L         	 
`                 opp-790000000               /q        	 
4                 opp-835000000               1        	 (r                 opp-880000000               4s         	 q                 opp-915000000               6        	 X                 opp-915000000-5             6        	            0      opp-915000000-6             6        	 q           p      opp-950000000               8ـ        	 5                  opp-950000000-5             8ـ        	 X           0      opp-950000000-6             8ـ        	 q           p         pmu-a55           arm,cortex-a55-pmu                      (                  pmu-a78           arm,cortex-a78-pmu                      (                  psci              arm,psci-1.0            smc       sound           3         	  Edisabled          thermal-zones      cpu-little0-thermal         L          Z           p          trips      trip-alert0          L                  tpassive         J         trip-alert1          s                  thot       trip-crit                              	  tcritical             cooling-maps       map0                     H     	   
                        cpu-little1-thermal         L          Z           p         trips      trip-alert0          L                  tpassive         J         trip-alert1          s                  thot       trip-crit                              	  tcritical             cooling-maps       map0                     H     	   
                        cpu-little2-thermal         L          Z           p         trips      trip-alert0          L                  tpassive         J         trip-alert1          s                  thot       trip-crit                              	  tcritical             cooling-maps       map0                     H     	   
                        cpu-little3-thermal         L          Z           p         trips      trip-alert0          L                  tpassive         J         trip-alert1          s                  thot       trip-crit                              	  tcritical             cooling-maps       map0                     H     	   
                        cpu-big0-thermal            L          Z   d        p         trips      trip-alert0          L                  tpassive         J         trip-alert1          s                  thot       trip-crit                              	  tcritical             cooling-maps       map0                                         cpu-big1-thermal            L          Z   d        p         trips      trip-alert0          L                  tpassive         J         trip-alert1          s                  thot       trip-crit                              	  tcritical             cooling-maps       map0                                         apu-thermal         L          Z           p          trips      trip-alert0          L                  tpassive       trip-alert1          s                  thot       trip-crit                              	  tcritical                gpu-thermal         L          Z           p         trips      trip-alert0          L                  tpassive         J         trip-alert1          s                  thot       trip-crit                              	  tcritical             cooling-maps       map0                                      gpu1-thermal            L          Z           p         trips      trip-alert0          L                  tpassive         J         trip-alert1          s                  thot       trip-crit                              	  tcritical             cooling-maps       map0                                      adsp-thermal            L          Z           p         trips      trip-alert0          L                  tpassive       trip-alert1          s                  thot       trip-crit                              	  tcritical                vdo-thermal         L          Z           p         trips      trip-alert0          L                  tpassive       trip-alert1          s                  thot       trip-crit                              	  tcritical                infra-thermal           L          Z           p         trips      trip-alert0          L                  tpassive       trip-alert1          s                  thot       trip-crit                              	  tcritical                cam1-thermal            L          Z           p         trips      trip-alert0          L                  tpassive       trip-alert1          s                  thot       trip-crit                              	  tcritical                cam2-thermal            L          Z           p         trips      trip-alert0          L                  tpassive       trip-alert1          s                  thot       trip-crit                              	  tcritical                   timer             arm,armv8-timer                   @  (                                             
                ]@      soc                      +             simple-bus                                             performance-controller@11bc10             mediatek,cpufreq-hw          y                 0                          J         interrupt-controller@c000000              arm,gic-v3                                                      y                                    (      	               J      ppi-partitions     interrupt-partition-0              	   
                    J         interrupt-partition-1                         J               syscon@10000000            mediatek,mt8188-topckgen syscon         y                                 J   "      syscon@10001000       #    mediatek,mt8188-infracfg-ao syscon          y                                           J   #      syscon@10003000           mediatek,mt8188-pericfg syscon          y     0                           J   A      pinctrl@10005000              mediatek,mt8188-pinctrl       `  y     P                                                                               0  #iocfg0 iocfg_rm iocfg_lt iocfg_lm iocfg_rt eint          -        =           I                                (                                 J       adsp-uart-pins     pins-tx-rx          U  #  $         i2c0-pins           J   J   pins-bus            U  8  7        \            i2c1-pins           J   T   pins-bus            U  :  9        \            i2c2-pins           J   K   pins-bus            U  <  ;        \            i2c3-pins           J   L   pins-bus            U  >  =        \            i2c4-pins           J   U   pins-bus            U  @  ?        \            i2c5-pins           J   W   pins-bus            U  B  A        \            i2c6-pins           J   X   pins-bus            U  D  C        \            mmc0-default-pins           J   G   pins-cmd-dat          $  U                           i        v           \   e      pins-clk            U          v              f      pins-rst            U          v           \   e         mmc0-uhs-pins           J   H   pins-cmd-dat          $  U                           i        v           \   e      pins-clk-ds         U            v              f      pins-rst            U          v           \   e         nor-pins            J   R   pins-io-ck          U    }                 pins-io-cs          U  ~             \         spi0-pins           J   ;   pins-spi            U  E  F  G  H                  spi1-pins           J   =   pins-spi            U  K  L  M  N                  spi2-pins           J   >   pins-spi            U  O  P  Q  R                  uart0-pins          J   :   pins-rx-tx          U              \            syscon@10006000       )    mediatek,mt8188-scpsys syscon simple-mfd            y     `           power-controller          !    mediatek,mt8188-power-controller                         +                       J   6   power-domain@0          y                         +                  power-domain@1          y              !      "           mfg alt            #                     +                  power-domain@2          y                     power-domain@3          y                     power-domain@4          y                           power-domain@15         y              "      "      "      "   
   "   3   "   4   "   =   "      "      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $            top cam ccu img venc vdec wpe cfgck cfgxo ss-sram-cmn ss-sram-v0l0 ss-sram-v0l1 ss-sram-ve0 ss-sram-ve1 ss-sram-ifa ss-sram-cam ss-sram-v1l5 ss-sram-v1l6 ss-sram-rdr ss-iommu ss-imgcam ss-emi ss-subcmn-rdr ss-rsi ss-cmn-l4 ss-vdec1 ss-wpe ss-cvdo-ve1             #                     +                  power-domain@16         y         H     "      "      %      %      %      %      %      %      %         A  cfgck cfgxo ss-gals ss-cmn ss-emi ss-iommu ss-larb ss-rsi ss-bus               #                     +                  power-domain@20         y         0     "      "      &      &      &      &         8  cfgck cfgxo ss-vpp1-g5 ss-vpp1-g6 ss-vpp1-l5 ss-vpp1-l6            #                  power-domain@22         y              '            ss-vdec1-soc-l1            #                     +                  power-domain@23         y              (            ss-vdec2-l1            #                     power-domain@29         y               "      "      "   	   "           cam ccu bus cfgck              #                     +                  power-domain@30         y         (     )       )      )      )      )         6  ss-cam-l13 ss-cam-l14 ss-cam-mm0 ss-cam-mm1 ss-camsys              #                     +                  power-domain@32         y               )      *       +          $  ss-camb-sub ss-camb-raw ss-camb-yuv                   power-domain@31         y              )      ,       -          $  ss-cama-sub ss-cama-raw ss-cama-yuv                         power-domain@17         y         (     "      "      .       .      .         &  cfgck cfgxo ss-larb2 ss-larb3 ss-gals              #                     +                  power-domain@9          y   	           "   @   "   ?      	  bus hdcp               #                  power-domain@18         y              #                  power-domain@19         y              #                     power-domain@24         y               /       /      /      /         0  ss-ve1-larb ss-ve1-core ss-ve1-gals ss-ve1-sram            #                  power-domain@21         y              0      0           ss-wpe-l7 ss-wpe-l7pce             #                        power-domain@5          y              #           1           ss-pextp-fmem                     power-domain@7          y              "   0   "   1        seninf0 seninf1                   power-domain@6          y                     power-domain@10         y   
           "   E   "   D      	  bus main               #                     +                  power-domain@11         y              #                     +                  power-domain@14         y              "   F        asm            #                  power-domain@13         y              "   S   "      2            a1sys intbus adspck            #                  power-domain@12         y              #                        power-domain@8          y              1         	  ethermac               #                        watchdog@10007000             mediatek,mt8188-wdt         y     p                                    J   7      syscon@1000c000       "    mediatek,mt8188-apmixedsys syscon           y                                J   !      timer@10017000        ,    mediatek,mt8188-timer mediatek,mt6765-timer         y    p                (      	                  3      pwrap@10024000        3    mediatek,mt8188-pwrap mediatek,mt8195-pwrap syscon          y    @                #pwrap           (                         #      #          	  spi wrap       pmic              mediatek,mt6359                                                     adc           mediatek,mt6359-auxadc                   audio-codec           mediatek,mt6359-codec         regulators            mediatek,mt6359-regulator      buck_vs1            )vs1         8 5         P !        h                   buck_vgpu11         )vgpu11          8         P 7                  h                                    buck_vmodem         )vmodem          8         P           *        h         buck_vpu            )vpu         8         P 7                  h                                    buck_vcore          )vcore           8         P                    h                                    buck_vs2            )vs2         8 5         P j         h                   buck_vpa            )vpa         8          P 7        h  ,      buck_vproc2         )vproc2          8         P 7          L        h                           buck_vproc1         )vproc1          8         P 7          L        h                           buck_vcore_sshub            )vcore_sshub         8         P 7      buck_vgpu11_sshub           )vgpu11_sshub            8         P 7      ldo_vaud18          )vaud18          8 w@        P w@        h         ldo_vsim1           )vsim1           8         P /M`      ldo_vibr            )vibr            8 O        P 2Z      ldo_vrf12           )vrf12           8         P                 ldo_vusb            )vusb            8 -        P -        h                 ldo_vsram_proc2         )vsram_proc2         8          P           L        h                  ldo_vio18           )vio18           8         P         h                 ldo_vcamio          )vcamio          8         P       ldo_vcn18           )vcn18           8 w@        P w@        h         ldo_vfe28           )vfe28           8 *        P *        h   x      ldo_vcn13           )vcn13           8         P        ldo_vcn33_1_bt          )vcn33_1_bt          8 *        P 5g      ldo_vcn33_1_wifi            )vcn33_1_wifi            8 *        P 5g      ldo_vaux18          )vaux18          8 w@        P w@        h                  ldo_vsram_others            )vsram_others            8          P                   h         ldo_vefuse          )vefuse          8         P       ldo_vxo22           )vxo22           8 w@        P !               ldo_vrfck           )vrfck           8 `        P       ldo_vrfck_1         )vrfck           8         P j       ldo_vbif28          )vbif28          8 *        P *        h         ldo_vio28           )vio28           8 *        P 2Z               ldo_vemc            )vemc            8 ,@         P 2Z      ldo_vemc_1          )vemc            8 &%        P 2Z        J   E      ldo_vcn33_2_bt          )vcn33_2_bt          8 *        P 5g      ldo_vcn33_2_wifi            )vcn33_2_wifi            8 *        P 5g      ldo_va12            )va12            8 O        P                 ldo_va09            )va09            8 5         P O      ldo_vrf18           )vrf18           8         P P      ldo_vsram_md          	  )vsram_md            8          P           *        h         ldo_vufs            )vufs            8         P         J   F      ldo_vm18            )vm18            8         P                ldo_vbbck           )vbbck           8         P O      ldo_vsram_proc1         )vsram_proc1         8          P           L        h                  ldo_vsim2           )vsim2           8         P /M`      ldo_vsram_others_sshub          )vsram_others_sshub          8          P          rtc           mediatek,mt6358-rtc             spmi@10027000         *    mediatek,mt8188-spmi mediatek,mt8195-spmi            y    p                            #pmif spmimst               "   8           "              #      #       "   8      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux       iommu@10315000            mediatek,mt8188-iommu-infra         y    1P                (                                J   P      mailbox@10320000              mediatek,mt8188-gce         y    2        @         (                                    #           J   \      mailbox@10330000              mediatek,mt8188-gce         y    3        @         (                                    #           J   ^      scp@10720000              mediatek,mt8188-scp-dual            y    r                 #cfg                      +                   P             Eokay       scp@0             mediatek,scp-core           y               #sram            (                     Eokay               4        J   _      scp@d0000             mediatek,scp-core           y             #sram            (                   	  Edisabled             audio-controller@10b10000             mediatek,mt8188-afe         y                        "   S           "              5   !   	   !   
   "      "      "      "      "      "   S   "      "       "   E   "   Q   "   M   "   N   "   O   "   P   2       "      "      "      "   T   "   R        clk26m apll1 apll2 apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 top_a1sys_hp top_aud_intbus top_audio_h top_audio_local_bus top_dptx top_i2so1 top_i2so2 top_i2si1 top_i2si2 adsp_audio_26m apll1_d4 apll2_d4 apll12_div4 top_a2sys top_aud_iec          (      6                  6           !   7         	  (audiosys               #        4   "      	  Edisabled            J         adsp@10b80000             mediatek,mt8188-dsp       @  y                                                           #cfg sram sec bus               "   D           "   D   "   E        audiodsp adsp_bus           F   8   9        Mrx tx              6         	  Edisabled          mailbox@10b86100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         y    a                (                                 J   8      mailbox@10b87100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         y    q                (                                 J   9      clock-controller@10b91100             mediatek,mt8188-adsp-audio26m           y                               J   2      serial@11001100       *    mediatek,mt8188-uart mediatek,mt6577-uart           y                     (                         5   #         	  baud bus            Eokay            Xdefault         f   :      serial@11001200       *    mediatek,mt8188-uart mediatek,mt6577-uart           y                     (                         5   #         	  baud bus          	  Edisabled          serial@11001300       *    mediatek,mt8188-uart mediatek,mt6577-uart           y                     (                         5   #         	  baud bus          	  Edisabled          serial@11001400       *    mediatek,mt8188-uart mediatek,mt6577-uart           y                     (                        5   #         	  baud bus          	  Edisabled          adc@11002000          .    mediatek,mt8188-auxadc mediatek,mt8173-auxadc           y                         #           main                       Eokay          syscon@11003000       "    mediatek,mt8188-pericfg-ao syscon           y     0                           J   1      spi@1100a000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            y                     (                         "   y   "      #           parent-clk sel-clk spi-clk          Eokay            Xdefault         f   ;      thermal-sensor@1100b000           mediatek,mt8188-lvts-ap         y                     (                         #           !   #           p   <        |lvts-calib-data-1                      J         pwm@1100e000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           y                        "   '   #   /        main mm         (                               	  Edisabled          pwm@1100f000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           y                        "   (   #   F        main mm         (                              	  Edisabled          spi@11010000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            y                     (                         "   y   "      #   2        parent-clk sel-clk spi-clk          Eokay            Xdefault         f   =      spi@11012000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            y                     (                         "   y   "      #   3        parent-clk sel-clk spi-clk          Eokay            Xdefault         f   >      spi@11013000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            y    0                (                         "   y   "      #   4        parent-clk sel-clk spi-clk        	  Edisabled          spi@11018000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            y                    (                         "   y   "      #   8        parent-clk sel-clk spi-clk        	  Edisabled          spi@11019000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            y                    (                         "   y   "      #   9        parent-clk sel-clk spi-clk        	  Edisabled          usb@11201000          #    mediatek,mt8188-mtu3 mediatek,mtu3           y            -     >              	  #mac ippc                                 ?                      +           (                         "   )           "   v           1   	   "      1   
        sys_ck ref_ck mcu_ck               ?      @                       A  h         	  Edisabled       usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          y                       #mac         (                         "   *           "   v           1   
        sys_ck          Eokay             ethernet@11021000         ;    mediatek,mt8188-gmac mediatek,mt8195-gmac snps,dwmac-5.10a          y           @         (                     macirq        0     1       1      "   A   "   B   "   C   1         .  axi apb mac_main ptp_ref rmii_internal mac_cg              "   A   "   B   "   C           "      "      "              6              #           B        	   C           D        /           :           E          	  Edisabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config           R                                 \           l           J   B      rx-queues-config            |                    J   C   queue0                             queue1                             queue2                             queue3                                tx-queues-config                                J   D   queue0                                        queue1                                       queue2                                       queue3                                             mmc@11230000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          y    #                              (                          "      #      #      #   M      !  source hclk source_cg crypto_clk            Eokay                        H        )          7         I         X         g         t                                      E           F        Xdefault state_uhs           f   G           H      mmc@11240000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          y    $                              (                         "      #      #   $        source hclk source_cg              "              "         	  Edisabled          mmc@11250000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          y    %                              (                         "      #      #   A        source hclk source_cg              "              "         	  Edisabled          thermal-sensor@11278000           mediatek,mt8188-lvts-mcu            y    '                (                         #           !   #            p   <        |lvts-calib-data-1                      J         i2c@11280000              mediatek,mt8188-i2c          y    (             "                (                                    I       #   7      	  main dma                         +            Eokay            Xdefault         f   J               i2c@11281000              mediatek,mt8188-i2c          y    (            "               (                                    I      #   7      	  main dma                         +            Eokay            Xdefault         f   K               i2c@11282000              mediatek,mt8188-i2c          y    (             "               (                                    I      #   7      	  main dma                         +            Eokay            Xdefault         f   L               clock-controller@11283000             mediatek,mt8188-imp-iic-wrap-c          y    (0                           J   I      usb@112a1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           y    *       -    *>              	  #mac ippc                        *        ?                      +           (                        "   -           "   v           1      "      1           sys_ck ref_ck mcu_ck               M                       A  p         	  Edisabled       usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          y                       #mac         (                        "   .           "   v           1           sys_ck          Eokay             usb@112b1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           y    +       -    +>              	  #mac ippc                        +        ?                      +           (                        "   ,           "   v           1      "      1           sys_ck ref_ck mcu_ck               N                       A  `         	  Edisabled       usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          y                       #mac         (                        "   +           "   v           1           sys_ck          Eokay             pcie@112f0000         *    mediatek,mt8188-pcie mediatek,mt8192-pcie           y    /                	  #pcie-mac                                                             mpci                                  +         0     #   L   #   #   #   &   #   +   #   C   1         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                     (                   `                    O                      O                     O                     O                                  	
       P              	               Q         	  	#pcie-phy               6           !   7           (mac       	  Edisabled       interrupt-controller                                             J   O         spi@1132c000          (    mediatek,mt8188-nor mediatek,mt8186-nor         y    2                   "   X   1      1           spi sf axi             "   X        (      9                            +            Eokay            Xdefault         f   R   flash@0           jedec,spi-nor           y            	-u          t-phy@11c20700        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                                            +              6         	  Edisabled       pcie-phy@0          y                  "           ref         	?           J   Q         dsi-phy@11c80000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         y                        5        mipi_tx0_pll                        	?          	  Edisabled            J   s      dsi-phy@11c90000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         y                        5        mipi_tx0_pll                        	?          	  Edisabled            J   t      i2c@11e00000              mediatek,mt8188-i2c          y                 "                (                                    S       #   7      	  main dma                         +            Eokay            Xdefault         f   T               i2c@11e01000              mediatek,mt8188-i2c          y                "               (                                    S      #   7      	  main dma                         +            Eokay            Xdefault         f   U               clock-controller@11e02000             mediatek,mt8188-imp-iic-wrap-w          y                                J   S      t-phy@11e30000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                Eokay       usb-phy@0           y                  "      !           ref da_ref          	?           J   N         t-phy@11e40000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                Eokay       usb-phy@0           y                  "      !           ref da_ref          	?           J   ?      usb-phy@700         y                 !      5        ref da_ref          	?           J   @         t-phy@11e80000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                Eokay       usb-phy@0           y                  "      !           ref da_ref          	?           J   M         i2c@11ec0000              mediatek,mt8188-i2c          y                 "               (                                    V       #   7      	  main dma                         +            Eokay            Xdefault         f   W               i2c@11ec1000              mediatek,mt8188-i2c          y                "                (                                    V      #   7      	  main dma                         +            Eokay            Xdefault         f   X               clock-controller@11ec2000              mediatek,mt8188-imp-iic-wrap-en         y                                J   V      efuse@11f20000        ,    mediatek,mt8188-efuse mediatek,mt8186-efuse         y                                  +      dp-calib@1a0            y             J   z      lvts1-calib@1ac         y     @        J   <      gpu-speedbin@581            y             	J               J   Z      socinfo-data1@7a0           y           socinfo-data2@7e0           y              gpu@13000000          )    mediatek,mt8188-mali arm,mali-valhall-jm            y             @            Y          0  (                   ~             }               job mmu gpu         p   Z      
  |speed-bin           	O   [           6      6      6           	ccore0 core1 core2           ;         	  Edisabled            J         clock-controller@13fbf000             mediatek,mt8188-mfgcfg          y                               J   Y      syscon@14000000           mediatek,mt8188-vppsys0 syscon          y                                 J   $      dma-controller@14001000           mediatek,mt8188-mdp3-rdma           y                     	v              $         <  F   \         \         \         \         \              	   ]              6           	   ^                  	              	   _      display@14002000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         y                         $            	   ^                 display@14004000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           y     @                   $   "        	   ^      @          display@14005000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           y     P                (      F                  $   
           6           	   ^      P          display@14006000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           y     `                   $           	   ^      `            	    %      display@14007000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           y     p                   $   #        	   ^      p          display@14008000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           y                     (      I                  $   $           6           	   ^                display@14009000          2    mediatek,mt8188-mdp3-ovl mediatek,mt8195-mdp3-ovl           y                     (      J                  $   %           6           	   ^                  	   ]         display@1400a000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           y                        $              6           	   ^                display@1400b000          2    mediatek,mt8188-mdp3-tcc mediatek,mt8195-mdp3-tcc           y                        $           	   ^                display@1400c000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         y                     	v              $           	   ]              6           	   ^                  	    +      mutex@1400f000            mediatek,mt8188-vpp-mutex           y                     (      P                  $              6           	   ^                smi@14012000              mediatek,mt8188-smi-common-vpp          y                        $      $           apb smi            6           J   `      smi@14013000              mediatek,mt8188-smi-larb            y    0                   $      $           apb smi            6           	           	   `        J   c      iommu@14018000            mediatek,mt8188-iommu-vpp           y           P            $           bclk            (      R                  6                      	   a   b   c   d   e   f        J   ]      dma-controller@14f09000           mediatek,mt8188-mdp3-rdma           y                    	v              &   
        	   g              6           	   ^   	              	          dma-controller@14f0a000           mediatek,mt8188-mdp3-rdma           y                    	v              &           	   ]              6           	   ^   	              	          display@14f0c000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         y                       &           	   ^   	            display@14f0d000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         y                       &           	   ^   	            display@14f0f000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           y                       &   "        	   ^   	            display@14f10000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           y                        &   $        	   ^   
             display@14f12000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           y                     (      j                  &   #           6           	   ^   
             display@14f13000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           y    0                (      k                  &   %           6           	   ^   
  0          display@14f15000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           y    P                   &           	   ^   
  P            	          display@14f16000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           y    `                   &           	   ^   
  `            	          display@14f18000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           y                       &           	   ^   
            display@14f19000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           y                       &           	   ^   
            display@14f1a000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           y                       &              6           	   ^   
            display@14f1b000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           y                       &              6           	   ^   
            display@14f1d000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           y                    (      u                  &              6           	   ^   
            display@14f1e000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           y                    (      v                  &              6           	   ^   
            display@14f21000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           y                       &              6           	   ^               display@14f22000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           y                        &              6           	   ^                display@14f24000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         y    @                	v              &           	   g              6           	   ^     @            	          display@14f25000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         y    P                	v              &           	   ]              6           	   ^     P            	          clock-controller@14e00000             mediatek,mt8188-wpesys          y                                J   0      clock-controller@14e02000             mediatek,mt8188-wpesys-vpp0         y                              smi@14e04000              mediatek,mt8188-smi-larb            y    @                   0      0           apb smi            6           	           	   `        J   e      syscon@14f00000           mediatek,mt8188-vppsys1 syscon          y                                J   &      mutex@14f01000            mediatek,mt8188-vpp-mutex           y                    (      {                  &   &           6           	   ^   	            smi@14f02000              mediatek,mt8188-smi-larb            y                        &      &           apb smi            6           	           	   h        J   w      smi@14f03000              mediatek,mt8188-smi-larb            y    0                   &      &           apb smi            6           	           	   `        J   d      clock-controller@15000000             mediatek,mt8188-imgsys          y                               clock-controller@15110000              mediatek,mt8188-imgsys1-dip-top         y                                         clock-controller@15130000             mediatek,mt8188-imgsys1-dip-nr          y                                         clock-controller@15220000             mediatek,mt8188-imgsys-wpe1         y    "                                     clock-controller@15330000             mediatek,mt8188-ipesys          y    3                                     clock-controller@15520000             mediatek,mt8188-imgsys-wpe2         y    R                                     clock-controller@15620000             mediatek,mt8188-imgsys-wpe3         y    b                                     clock-controller@16000000             mediatek,mt8188-camsys          y                                 J   )      clock-controller@1604f000             mediatek,mt8188-camsys-rawa         y                                          J   ,      clock-controller@1606f000             mediatek,mt8188-camsys-yuva         y                                          J   -      clock-controller@1608f000             mediatek,mt8188-camsys-rawb         y                                          J   *      clock-controller@160af000             mediatek,mt8188-camsys-yuvb         y    
                                      J   +      clock-controller@17200000             mediatek,mt8188-ccusys          y                               video-decoder@18000000            mediatek,mt8188-vcodec-dec           y                   @                                    `         	   ]                       +           	   _   video-codec@10000             mediatek,mtk-vcodec-lat         y                         "   4           "   x            "   4   '      '      "   x        sel vdec lat top            (                   H  	   ]     ]     ]     ]     ]     ]     ]     ]     ]             6         video-codec@25000             mediatek,mtk-vcodec-core            y     P                   "   4           "   x            "   4   (      (      "   x        sel vdec lat top            (                   X  	   g     g     g     g     g     g     g     g     g     g     g             6            smi@1800d000              mediatek,mt8188-smi-larb            y                        '       '            apb smi            6           	           	   `        J   f      clock-controller@1800f000             mediatek,mt8188-vdecsys-soc         y                                J   '      smi@1802e000              mediatek,mt8188-smi-larb            y                       (       (            apb smi            6           	           	   h        J   y      clock-controller@1802f000             mediatek,mt8188-vdecsys         y                               J   (      clock-controller@1a000000             mediatek,mt8188-vencsys         y                                 J   /      smi@1a010000              mediatek,mt8188-smi-larb            y                        /      /           apb smi            6           	           	   h        J   x      video-encoder@1a020000            mediatek,mt8188-vcodec-enc          y                                  +              "   3           "   p           /         	  venc_sel            (      a             X  	   g     g     g     g     g     g     g     g     g     g     g             6           	   _      jpeg-encoder@1a030000         +    mediatek,mt8188-jpgenc mediatek,mtk-jpgenc          y                        /           jpgenc          (      b                	   g     g     g     g             6         jpeg-decoder@1a040000         .    mediatek,mt8188-jpgdec mediatek,mt2701-jpgdec           y                        /       /           jpgdec-smi jpgdec           (      c             0  	   g     g     g     g     g     g             6         ovl@1c000000          2    mediatek,mt8188-disp-ovl mediatek,mt8195-disp-ovl           y                         %            (      |               	   g              6           	   \             ports                        +       port@0          y       endpoint             port@1          y      endpoint            	   i        J   j               rdma@1c002000         4    mediatek,mt8188-disp-rdma mediatek,mt8195-disp-rdma         y                         %           (      ~               	   ]               6           	   \             ports                        +       port@0          y       endpoint            	   j        J   i         port@1          y      endpoint            	   k        J   l               color@1c003000        6    mediatek,mt8188-disp-color mediatek,mt8173-disp-color           y     0                   %           (                        6           	   \     0       ports                        +       port@0          y       endpoint            	   l        J   k         port@1          y      endpoint            	   m        J   n               ccorr@1c004000        6    mediatek,mt8188-disp-ccorr mediatek,mt8192-disp-ccorr           y     @                   %           (                        6           	   \     @       ports                        +       port@0          y       endpoint            	   n        J   m         port@1          y      endpoint            	   o        J   p               aal@1c005000          2    mediatek,mt8188-disp-aal mediatek,mt8183-disp-aal           y     P                   %           (                        6           	   \     P       ports                        +       port@0          y       endpoint            	   p        J   o         port@1          y      endpoint            	   q        J   r               gamma@1c006000        6    mediatek,mt8188-disp-gamma mediatek,mt8195-disp-gamma           y     `                   %           (                        6           	   \     `       ports                        +       port@0          y       endpoint            	   r        J   q         port@1          y      endpoint                   dither@1c007000       8    mediatek,mt8188-disp-dither mediatek,mt8183-disp-dither         y     p                   %           (                        6           	   \     p       ports                        +       port@0          y       endpoint             port@1          y      endpoint                   dsi@1c008000              mediatek,mt8188-dsi         y                        %      %      s        engine digital hs           (                        s        	#dphy               6           !   %         	  Edisabled          dsc@1c009000          2    mediatek,mt8188-disp-dsc mediatek,mt8195-disp-dsc           y                        %   
        (                        6           	   \               dsi@1c012000              mediatek,mt8188-dsi         y                        %   	   %      t        engine digital hs           (                        t        	#dphy               6           !   %   	      	  Edisabled          merge0@1c014000       6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           y    @                   %      .           merge merge_async           (                        6           	   \     @          dp-intf@1c015000              mediatek,mt8188-dp-intf         y    P                   %       %      !           pixel engine pll            (                        6         	  Edisabled          mutex@1c016000            mediatek,mt8188-disp-mutex          y    `                   %           (                        6           	   \     `            	  >      postmask@1c01a000         <    mediatek,mt8188-disp-postmask mediatek,mt8192-disp-postmask         y                       %           (                        6           	   \            ports                        +       port@0          y       endpoint             port@1          y      endpoint                   syscon@1c01d000           mediatek,mt8188-vdosys0 syscon          y                                          F   \               	   \                 J   %      smi@1c022000              mediatek,mt8188-smi-larb            y                        %      %           apb smi            6           	            	   h        J   u      smi@1c023000              mediatek,mt8188-smi-larb            y    0                   %      %           apb smi            6           	           	   `        J   a      smi@1c024000              mediatek,mt8188-smi-common-vdo          y    @                   %      %           apb smi            6           J   h      iommu@1c028000            mediatek,mt8188-iommu-vdo           y           P            %           bclk            (                        6                      	   u   v   w   x   y        J   g      syscon@1c100000           mediatek,mt8188-vdosys1 syscon          y                                           F   \              	   \                  J   .      mutex@1c101000            mediatek,mt8188-disp-mutex          y                       .           (                        6           	   \                 	        smi@1c102000              mediatek,mt8188-smi-larb            y                        .       .            apb smi            6           	           	   h        J   v      smi@1c103000              mediatek,mt8188-smi-larb            y    0                   .      .           apb smi            6           	           	   `        J   b      rdma@1c104000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         y    @                   .           (                     	   g   @           6           	v           	   \     @          rdma@1c105000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         y    P                   .           (                     	   ]   `           6           	v           	   \     P          rdma@1c106000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         y    `                   .           (                     	   g   A           6           	v           	   \     `          rdma@1c107000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         y    p                   .           (                     	   ]   a           6           	v           	   \     p          rdma@1c108000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         y                       .           (                     	   g   B           6           	v           	   \               rdma@1c109000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         y                       .           (                     	   ]   b           6           	v           	   \               rdma@1c10a000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         y                       .           (                     	   g   C           6           	v           	   \               rdma@1c10b000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         y                       .           (                     	   ]   c           6           	v           	   \               merge@1c10c000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           y                       .   	   .           merge merge_async           (                        6           !   .           	   \                  	      merge@1c10d000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           y                       .   
   .           merge merge_async           (                        6           !   .           	   \                  	      merge@1c10e000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           y                       .      .           merge merge_async           (                        6           !   .           	   \                  	      merge@1c10f000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           y                       .      .           merge merge_async           (                        6           !   .           	   \                  	      merge@1c110000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           y                        .      .           merge merge_async           (                        6           !   .           	   \                   
      dp-intf@1c113000              mediatek,mt8188-dp-intf         y    0                   .   :   .      !           pixel engine pll            (                        6         	  Edisabled          ethdr@1c114000        6    mediatek,mt8188-disp-ethdr mediatek,mt8195-disp-ethdr         p  y    @            P            p                                                              4  #mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       h     .   0   .   +   .   .   .   ,   .   /   .   -   .   <   .   1   .   2   .   3   .   4   .   5   "           mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          (      6               	   ]   d   ]   e           6         (  !   .   1   .   2   .   3   .   4   .   5      p  	   \     @       \     P       \     p       \            \            \            \               padding@1c11d000              mediatek,mt8188-disp-padding            y                       .              6           	   \               padding@1c11e000              mediatek,mt8188-disp-padding            y                       .               6           	   \               padding@1c11f000              mediatek,mt8188-disp-padding            y                       .   !           6           	   \               padding@1c120000              mediatek,mt8188-disp-padding            y                        .   "           6           	   \                padding@1c121000              mediatek,mt8188-disp-padding            y                       .   #           6           	   \               padding@1c122000              mediatek,mt8188-disp-padding            y                        .   $           6           	   \                padding@1c123000              mediatek,mt8188-disp-padding            y    0                   .   %           6           	   \     0          padding@1c124000              mediatek,mt8188-disp-padding            y    @                   .   &           6           	   \     @          edp-tx@1c500000           mediatek,mt8188-edp-tx          y    P                 (                     p   z        |dp_calibration_data            6           
)        	  Edisabled          dp-tx@1c600000            mediatek,mt8188-dp-tx           y    `                 (                     p   z        |dp_calibration_data            6           
)        	  Edisabled             chosen          
:serial0:115200n8          memory@40000000         mmemory          y    @                reserved-memory                      +               memory@50000000           shared-dma-pool         y    P                  
F        J   4            	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dsc0 ethdr0 gce0 gce1 merge0 merge1 merge2 merge3 merge4 merge5 mutex0 mutex1 padding0 padding1 padding2 padding3 padding4 padding5 padding6 padding7 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 mmc0 device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-output-names opp-shared opp-hz opp-microvolt opp-supported-hw interrupts mediatek,platform status polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux bias-pull-up input-enable drive-strength bias-pull-down bias-disable #power-domain-cells clocks clock-names mediatek,infracfg mediatek,disable-extrst #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells memory-region power-domains resets reset-names mediatek,topckgen mboxes mbox-names pinctrl-names pinctrl-0 nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells phys wakeup-source mediatek,syscon-wakeup interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,blen snps,rd_osr_lmt snps,wr_osr_lmt snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,priority snps,weight bus-width hs400-ds-delay max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v supports-cqe cap-mmc-hw-reset no-sdio no-sd non-removable vmmc-supply vqmmc-supply pinctrl-1 clock-div bus-range linux,pci-domain interrupt-map interrupt-map-mask iommu-map iommu-map-mask phy-names spi-max-frequency #phy-cells bits operating-points-v2 power-domain-names #dma-cells iommus mediatek,gce-client-reg mediatek,gce-events mediatek,scp mediatek,larb-id mediatek,smi mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz stdout-path no-map 