     8  4   (                                               openwrt,one mediatek,mt7981b                                     +            7OpenWrt One    cpus                         +       cpu@0             arm,cortex-a53           =             Acpu          Mpsci          cpu@1             arm,cortex-a53           =            Acpu          Mpsci             oscillator-40m            fixed-clock          [bZ          kclkxtal          ~          psci              arm,psci-1.0             Tsmc       reserved-memory                      +                secmon@43000000          =    C                             soc           simple-bus                                 +      interrupt-controller@c000000              arm,gic-v3            =                                                       	                                           clock-controller@10001000              mediatek,mt7981-infracfg syscon          =                      ~                     clock-controller@1001b000              mediatek,mt7981-topckgen syscon          =                     ~                     watchdog@1001c000             mediatek,mt7986-wdt          =                            n                                 clock-controller@1001e000             mediatek,mt7981-apmixedsys           =                     ~               	      pwm@10048000              mediatek,mt7981-pwm          =                  (                                          top main pwm1 pwm2 pwm3                      default                    okay                      serial@11002000       *    mediatek,mt7981-uart mediatek,mt6577-uart            =                              {           uart wakeup                            	   baud bus             default                    okay          serial@11003000       *    mediatek,mt7981-uart mediatek,mt6577-uart            =     0                        |           uart wakeup                             	   baud bus          	  disabled          serial@11004000       *    mediatek,mt7981-uart mediatek,mt6577-uart            =     @                        }           uart wakeup                      !      	   baud bus          	  disabled          i2c@11007000              mediatek,mt7981-i2c           =     p            !p                                                      3      4         main dma arb pmic                        +          	  disabled          spi@11009000          )    mediatek,mt7981-spi-ipm mediatek,spi-ipm             =                                                      N      "      #          parent-clk sel-clk spi-clk hclk                      +            okay             default               flash@0           jedec,spi-nor            =            ,bZ                      +      partitions            fixed-partitions                         +      partition@0          =               >bl2-nor       partition@40000          =              >factory          D   nvmem-layout              fixed-layout                         +      eeprom@0             =             macaddr@24           =   $         	    mac-base            N               partition@100000             =              >fip-nor       partition@180000             =            	  >recovery                   spi@1100a000          )    mediatek,mt7981-spi-ipm mediatek,spi-ipm             =                                                      N      '      )          parent-clk sel-clk spi-clk hclk                      +          	  disabled          spi@1100b000          )    mediatek,mt7981-spi-ipm mediatek,spi-ipm             =                                                      N      (      *          parent-clk sel-clk spi-clk hclk                      +          	  disabled          thermal@1100c800          0    mediatek,mt7981-thermal mediatek,mt7986-thermal          =                                                     0         therm auxadc            `           lcalibration-data            }                         	      adc@1100d000          .    mediatek,mt7981-auxadc mediatek,mt7986-auxadc            =                            0         main                     	  disabled                      pinctrl@11d00000              mediatek,mt7981-pinctrl          =                                                                                                                           I  gpio iocfg_rt iocfg_rm iocfg_rb iocfg_lb iocfg_bl iocfg_tm iocfg_tl eint                                                        
           8                                            
   uart0-pins                 mux         uart            uart0            pwm-pins                   mux         pwm         pwm0_0 pwm1_1            spi2-pins                  mux         spi         spi2          conf-pu            g                   'SPI2_CS SPI2_WP       conf-pd         ,   g                   'SPI2_CLK SPI2_MOSI SPI2_MISO                efuse@11f20000        %    mediatek,mt7981-efuse mediatek,efuse             =                                  +      soc-uuid@140             =  @         thermal-calib@274            =  t                        clock-controller@15000000             mediatek,mt7981-ethsys syscon            =                       ~                     wifi@18000000             mediatek,mt7981-wmac          0   =                   0                           0                                                          _      \         mcu ap2conn         ;              Bconsys           timer             arm,armv8-timer                   0                                    
         aliases         N/soc/serial@11002000          chosen          Vserial0:115200n8          memory@40000000          =    @       @            Amemory        pwm-leds          	    pwm-leds       led-0           b            h            status          {                    '      led-1           b           h            status          {                   '         gpio-leds         
    gpio-leds      led-0           b           status             
   	          led-1           b           lan            
   "           netdev        led-2           b           lan            
   #           netdev              	compatible interrupt-parent #address-cells #size-cells model reg device_type enable-method clock-frequency clock-output-names #clock-cells ranges no-map interrupts interrupt-controller #interrupt-cells phandle #reset-cells clocks clock-names #pwm-cells pinctrl-names pinctrl-0 status interrupt-names spi-max-frequency label read-only #nvmem-cell-cells nvmem-cells nvmem-cell-names #thermal-sensor-cells mediatek,auxadc mediatek,apmixedsys #io-channel-cells reg-names gpio-ranges gpio-controller #gpio-cells function groups bias-pull-up drive-strength pins bias-pull-down resets reset-names serial0 stdout-path color default-brightness max-brightness pwms gpios linux,default-trigger 