 G   8 8   (             8                             4    mediatek,mt8370-evk mediatek,mt8370 mediatek,mt8188                                  +            7MediaTek Genio-510 EVK     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dsc@1c009000            T/soc/ethdr@1c114000          [/soc/mailbox@10320000            `/soc/mailbox@10330000            e/soc/merge0@1c014000             l/soc/merge@1c10c000          s/soc/merge@1c10d000          z/soc/merge@1c10e000          /soc/merge@1c10f000          /soc/merge@1c110000          /soc/mutex@1c016000          /soc/mutex@1c101000          /soc/padding@1c11d000            /soc/padding@1c11e000            /soc/padding@1c11f000            /soc/padding@1c120000            /soc/padding@1c121000            /soc/padding@1c122000            /soc/padding@1c123000            /soc/padding@1c124000            /soc/rdma@1c104000           /soc/rdma@1c105000           /soc/rdma@1c106000          /soc/rdma@1c107000          /soc/rdma@1c108000          /soc/rdma@1c109000          '/soc/rdma@1c10a000          2/soc/rdma@1c10b000          =/soc/dsi@1c008000           B/soc/ethernet@11021000          L/soc/i2c@11280000           Q/soc/i2c@11e00000           V/soc/i2c@11281000           [/soc/i2c@11282000           `/soc/i2c@11e01000           e/soc/i2c@11ec0000           j/soc/i2c@11ec1000           o/soc/mmc@11230000           t/soc/mmc@11240000           y/soc/serial@11001100          cpus                         +       cpu@0           cpu           arm,cortex-a55                      psci            w5                                               @                                 @                   *           ;               O           ^   	      cpu@100         cpu           arm,cortex-a55                     psci            w5                                               @                                 @                   *           ;               O           ^   
      cpu@200         cpu           arm,cortex-a55                     psci            w5                                               @                                 @                   *           ;               O           ^         cpu@300         cpu           arm,cortex-a55                     psci            w5                                               @                                 @                   *           ;               O           ^         cpu@600         cpu           arm,cortex-a78                     psci            !V                                                @                                 @                   *           ;              O           ^         cpu@700         cpu           arm,cortex-a78                     psci            !V                                                @                                 @                   *           ;              O           ^         cpu-map    cluster0       core0           f   	      core1           f   
      core2           f         core3           f         core6           f         core7           f               idle-states         jpsci       cpu-off-l             arm,idle-state          w                       2           _          D        ^         cpu-off-b             arm,idle-state          w                       -                             ^         cluster-off-l             arm,idle-state          w                     7                     H        ^         cluster-off-b             arm,idle-state          w                     2                             ^            l2-cache0             cache                                    @                   *                    ^         l2-cache1             cache                                    @                   *                    ^         l3-cache              cache                                     @                            ^            oscillator-13m            fixed-clock                      ]@        clk13m          ^   7      oscillator-26m            fixed-clock                             clk26m          ^   9      oscillator-32k            fixed-clock                                clk32k        opp-table-gpu             operating-points-v2                  ^      opp-390000000               >                 +         opp-431000000                                +         opp-473000000               1h@         	'        +         opp-515000000               F         	X        +         opp-556000000               !#          	h        +         opp-598000000               #         	<        +         opp-640000000               &%          	        +         opp-670000000               'c         
        +         opp-700000000               )'          
L        +         opp-730000000               +         
}        +         opp-760000000               -L          
`        +         opp-790000000               /q         
4        +         opp-835000000               1         (r        +         opp-880000000               4s          q        +         opp-915000000               6         X        +         opp-915000000-5             6                 +   0      opp-915000000-6             6         q        +   p      opp-950000000               8ـ         5         +         opp-950000000-5             8ـ         X        +   0      opp-950000000-6             8ـ         q        +   p         pmu-a55           arm,cortex-a55-pmu                      <                  pmu-a78           arm,cortex-a78-pmu                      <                  psci              arm,psci-1.0            smc       sound           G           Yokay          6    mediatek,mt8390-mt6359-evk mediatek,mt8188-mt6359-evb            7mt8390-evk          `default         n         t  xHeadphone Headphone L Headphone Headphone R DMIC_INPUT AP DMIC AP DMIC AUDGLB AP DMIC MIC_BIAS_0 AP DMIC MIC_BIAS_2               dai-link-0        
  DL_SRC_BE      codec                           dai-link-1          DMIC_BE    codec                          thermal-zones      cpu-little0-thermal                                        trips      trip-alert0          L                  passive         ^         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                     0     	   
                  cpu-little1-thermal                                       trips      trip-alert0          L                  passive         ^         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                     0     	   
                  cpu-little2-thermal                                       trips      trip-alert0          L                  passive         ^         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                     0     	   
                  cpu-little3-thermal                                       trips      trip-alert0          L                  passive         ^         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                     0     	   
                  cpu-big0-thermal                         d                 trips      trip-alert0          L                  passive         ^         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                                         cpu-big1-thermal                         d                 trips      trip-alert0          L                  passive         ^         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                                         apu-thermal                                        trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                gpu-thermal                                       trips      trip-alert0          L                  passive         ^         trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0                                       gpu1-thermal                                          trips      trip-alert0          L                  passive         ^   !      trip-alert1          s                  hot       trip-crit                              	  critical             cooling-maps       map0               !                        adsp-thermal                                          trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                vdo-thermal                                       trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                infra-thermal                                         trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                cam1-thermal                                          trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                cam2-thermal                                          trips      trip-alert0          L                  passive       trip-alert1          s                  hot       trip-crit                              	  critical                   timer             arm,armv8-timer                   @  <                                             
                ]@      soc                      +             simple-bus                                             performance-controller@11bc10             mediatek,cpufreq-hw                           0                          ^         interrupt-controller@c000000              arm,gic-v3          ,           =                        T                                             <      	               ^      ppi-partitions     interrupt-partition-0           i   	   
              ^         interrupt-partition-1           i              ^               syscon@10000000            mediatek,mt8188-topckgen syscon                                          ^   %      syscon@10001000       #    mediatek,mt8188-infracfg-ao syscon                                          r           ^   &      syscon@10003000           mediatek,mt8188-pericfg syscon               0                           ^   I      pinctrl@10005000              mediatek,mt8188-pinctrl       `       P                                                                               0  iocfg0 iocfg_rm iocfg_lt iocfg_lm iocfg_rt eint                                "                    T        <                      ,           ^   "   audio-default-pins          ^      pins-cmd-dat          X    e  f  g  h  i  j  k  l  m  n  r  s  t  u  v  y  z  |  }  ~             disp-pwm1-pins          ^   E   pins-pwm                       dptx-pins      pins-cmd-dat              .                  edp-panel-3v3-en-pins           ^      pins1                                eth-default-pins            ^   U   pins-cc                                  pins-mdio                                         pins-power                               pins-rxd                                     pins-txd                                        eth-sleep-pins          ^   V   pins-cc                           pins-mdio                                         pins-rxd                              pins-txd                                 i2c0-pins           ^   `   pins              8  7                              i2c1-pins           ^   r   pins              :  9                              i2c2-pins           ^   d   pins              <  ;                              i2c3-pins           ^   e   pins              >  =                              i2c4-pins           ^   u   pins              @  ?                              i2c5-pins           ^   |   pins              B  A                              i2c6-pins           ^   }   pins              D  C                              gpio-key-pins      pins              *  +  ,         mmc0-default-pins           ^   W   pins-clk                                     f      pins-cmd-dat          $                                                   e      pins-rst                                    e         mmc0-uhs-pins           ^   X   pins-clk                                     f      pins-cmd-dat          $                                                   e      pins-ds                                  f      pins-rst                                    e         mmc1-default-pins           ^   [   pins-clk                                     f      pins-cmd-dat                                                     e      pins-insert                              mmc1-uhs-pins           ^   \   pins-clk                                     f      pins-cmd-dat                                                     e         mmc2-default-pins      pins-clk                                     f      pins-cmd-dat                                                     e      pins-pcm              {         mmc2-uhs-pins      pins-clk                                     f      pins-cmd-dat                                                     e         mmc2-eint-pins     pins-dat1                                  e         mmc2-dat1-pins     pins-dat1                                            e         dsi0-vreg-en-pins           ^      pins-pwr-en           o          /         panel-default-pins          ^      pins-rst                        /      pins-en           -          /         pcie-default-pins           ^   p   pins              /  0  1                  rt1715-int-pins    pins_cmd0_dat                                         spi0-pins      pins-spi              E  F  G  H                  spi1-pins      pins-spi              K  L  M  N                  spi2-pins           ^   F   pins-spi              O  P  Q  R                  touch-avdd-pins         ^      pins-power            x                   touch-pins          ^   c   pins-irq                                       pins-reset                               tcpci-int-pins          ^   v   pins-int-n                                        uart0-pins          ^   A   pins                                   uart1-pins          ^   B   pins              !  "                  uart2-pins          ^   C   pins              #  $                  usb-default-pins            ^   k   pins-iddig            S                         pins-valid            U               pins-vbus             T                  usb1-default-pins           ^   K   pins-valid            X               pins-usb-hub-3v3-en           p                   usb2-default-pins           ^   g   pins-iddig            Y                            wifi-pwrseq-pins       pins-wifi-enable                        /            syscon@10006000       )    mediatek,mt8188-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8188-power-controller                         +            :           ^   :   power-domain@0                                   +            :           N   #   power-domain@1                     \   $      %           cmfg alt         o   &                     +            :           N   '   power-domain@2                     :          power-domain@3                     :          power-domain@4                     :                power-domain@15                    \   %      %      %      %   
   %   3   %   4   %   =   %      %      (      (      (      (      (      (      (      (      (      (      (      (      (      (      (      (      (      (      (            ctop cam ccu img venc vdec wpe cfgck cfgxo ss-sram-cmn ss-sram-v0l0 ss-sram-v0l1 ss-sram-ve0 ss-sram-ve1 ss-sram-ifa ss-sram-cam ss-sram-v1l5 ss-sram-v1l6 ss-sram-rdr ss-iommu ss-imgcam ss-emi ss-subcmn-rdr ss-rsi ss-cmn-l4 ss-vdec1 ss-wpe ss-cvdo-ve1          o   &                     +            :      power-domain@16                  H  \   %      %      )      )      )      )      )      )      )         A  ccfgck cfgxo ss-gals ss-cmn ss-emi ss-iommu ss-larb ss-rsi ss-bus            o   &                     +            :      power-domain@20                  0  \   %      %      *      *      *      *         8  ccfgck cfgxo ss-vpp1-g5 ss-vpp1-g6 ss-vpp1-l5 ss-vpp1-l6         o   &        :          power-domain@22                    \   +            css-vdec1-soc-l1         o   &                     +            :      power-domain@23                    \   ,            css-vdec2-l1         o   &        :             power-domain@29                     \   %      %      %   	   %           ccam ccu bus cfgck           o   &                     +            :      power-domain@30                  (  \   -       -      -      -      -         6  css-cam-l13 ss-cam-l14 ss-cam-mm0 ss-cam-mm1 ss-camsys           o   &                     +            :      power-domain@32                     \   -      .       /          $  css-camb-sub ss-camb-raw ss-camb-yuv         :          power-domain@31                    \   -      0       1          $  css-cama-sub ss-cama-raw ss-cama-yuv         :                power-domain@17                  (  \   %      %      2       2      2         &  ccfgck cfgxo ss-larb2 ss-larb3 ss-gals           o   &                     +            :      power-domain@9             	        \   %   @   %   ?      	  cbus hdcp            o   &        :          power-domain@18                    o   &        :          power-domain@19                    o   &        :             power-domain@24                     \   3       3      3      3         0  css-ve1-larb ss-ve1-core ss-ve1-gals ss-ve1-sram         o   &        :          power-domain@21                    \   4      4           css-wpe-l7 ss-wpe-l7pce          o   &        :                power-domain@5                     o   &        \   5           css-pextp-fmem           :          power-domain@7                     \   %   0   %   1        cseninf0 seninf1         :          power-domain@6                     :          power-domain@10            
        \   %   E   %   D      	  cbus main            o   &                     +            :      power-domain@11                    o   &                     +            :      power-domain@14                    \   %   F        casm         o   &        :          power-domain@13                    \   %   S   %      6            ca1sys intbus adspck         o   &        :          power-domain@12                    o   &        :                power-domain@8                     \   5         	  cethermac            o   &        :                watchdog@10007000             mediatek,mt8188-wdt              p                         r           ^   ;      syscon@1000c000       "    mediatek,mt8188-apmixedsys syscon                                           ^   $      timer@10017000        ,    mediatek,mt8188-timer mediatek,mt6765-timer             p                <      	               \   7      pwrap@10024000        3    mediatek,mt8188-pwrap mediatek,mt8195-pwrap syscon              @                pwrap           <                      \   &      &          	  cspi wrap       pmic              mediatek,mt6359          T        ,                          "        <              ^      adc           mediatek,mt6359-auxadc                   audio-codec           mediatek,mt6359-codec                               regulators            mediatek,mt6359-regulator      buck_vs1            vs1          5          !        #             ?      buck_vgpu11       
  dvdd_core                     7        S          #           h                   ?      buck_vmodem         vmodem                            S  *        #         buck_vpu          
  dvdd_adsp                     7        S          #           h                   ?      buck_vcore          dvdd_proc_l                            S          #           h                   ?      buck_vs2            vs2          5          j         #             ?      buck_vpa            vpa_pmu                    /M`        #  ,        ^   ]      buck_vproc2         vgpu             dp         5         S  L        #           h                     '          j        ^   #      buck_vproc1         vproc1                    7        S  L        #           h                buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub                      7      ldo_vaud18          vaud18           w@         w@        #         ldo_vsim1         
  vsim1_pmu                     /M`        #          ^   ^      ldo_vibr            vibr             O         2Z      ldo_vrf12           va12_abb2_pmu                               ?      ldo_vusb            vusb             -         -        #           ?        ^   J      ldo_vsram_proc2         vsram_proc2                            S  L        #            ?      ldo_vio18           vio18                             #           ?        ^   b      ldo_vcamio          vcamio                          ldo_vcn18         
  vcn18_pmu            w@         w@        #            ?      ldo_vfe28           vfe28            *         *        #   x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_bt           *         5g        ^   s      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@        #            ?      ldo_vsram_others          
  vsram_gpu            q         5         S          #              #          j        ^   '      ldo_vefuse          vefuse                          ldo_vxo22           vxo22            w@         !         ?      ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *        #         ldo_vio28           vio28            *         2Z         ?      ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z        ^   Y      ldo_vcn33_2_bt          vcn33_2_pmu          *         5g         ?      ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                   ?      ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                               S  *        #         ldo_vufs            vufs18_pmu                             ?        ^   Z      ldo_vm18            vm18                               ?      ldo_vbbck           vbbck                     O         ?      ldo_vsram_proc1         vsram_proc1                            S  L        #            ?      ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              rtc           mediatek,mt6358-rtc       keys              mediatek,mt6359-keys                              power-key              t               home               f               spmi@10027000         *    mediatek,mt8188-spmi mediatek,mt8195-spmi                p                            pmif spmimst               %   8           %           \   &      &       %   8      (  cpmif_sys_ck pmif_tmr_ck spmimst_clk_mux       iommu@10315000            mediatek,mt8188-iommu-infra             1P                <                     $           ^   n      mailbox@10320000              mediatek,mt8188-gce             2        @         <                      1           \   &           ^         mailbox@10330000              mediatek,mt8188-gce             3        @         <                      1           \   &           ^         scp@10720000              mediatek,mt8188-scp-dual                r                 cfg                      +                   P             Yokay       scp@0             mediatek,scp-core                          sram            <                     Yokay            =   8        ^         scp@d0000             mediatek,scp-core                        sram            <                   	  Ydisabled             audio-controller@10b10000             mediatek,mt8188-afe                                 %   S           %           \   9   $   	   $   
   %      %      %      %      %      %   S   %      %       %   E   %   Q   %   M   %   N   %   O   %   P   6       %      %      %      %   T   %   R        cclk26m apll1 apll2 apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 top_a1sys_hp top_aud_intbus top_audio_h top_audio_local_bus top_dptx top_i2so1 top_i2so2 top_i2si1 top_i2si2 adsp_audio_26m apll1_d4 apll2_d4 apll12_div4 top_a2sys top_aud_iec          <      6               K   :           Y   ;         	  `audiosys            o   &        l   %        Yokay            =   <        ^         adsp@10b80000             mediatek,mt8188-dsp       @                                                             cfg sram sec bus               %   D        \   %   D   %   E        caudiodsp adsp_bus           ~   =   >        rx tx           K   :           Yokay            =   ?   @        ^         mailbox@10b86100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox             a                <                     1            ^   =      mailbox@10b87100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox             q                <                     1            ^   >      clock-controller@10b91100             mediatek,mt8188-adsp-audio26m                                          ^   6      serial@11001100       *    mediatek,mt8188-uart mediatek,mt6577-uart                                <                      \   9   &         	  cbaud bus            Yokay            n   A        `default       serial@11001200       *    mediatek,mt8188-uart mediatek,mt6577-uart                                <                      \   9   &         	  cbaud bus            Yokay            n   B        `default       serial@11001300       *    mediatek,mt8188-uart mediatek,mt6577-uart                                <                      \   9   &         	  cbaud bus            Yokay            n   C        `default       serial@11001400       *    mediatek,mt8188-uart mediatek,mt6577-uart                                <                     \   9   &         	  cbaud bus          	  Ydisabled          adc@11002000          .    mediatek,mt8188-auxadc mediatek,mt8173-auxadc                                 \   &           cmain                     	  Ydisabled          syscon@11003000       "    mediatek,mt8188-pericfg-ao syscon                0                           ^   5      spi@1100a000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 <                      \   %   y   %      &           cparent-clk sel-clk spi-clk        	  Ydisabled          thermal-sensor@1100b000           mediatek,mt8188-lvts-ap                              <                      \   &           Y   &              D        lvts-calib-data-1                      ^         pwm@1100e000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm                                \   %   '   &   /        cmain mm         <                               	  Ydisabled          pwm@1100f000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm                                \   %   (   &   F        cmain mm         <                                Yokay            `default         n   E        ^         spi@11010000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 <                      \   %   y   %      &   2        cparent-clk sel-clk spi-clk        	  Ydisabled          spi@11012000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                 <                      \   %   y   %      &   3        cparent-clk sel-clk spi-clk          Yokay            n   F        `default                   spi@11013000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                0                <                      \   %   y   %      &   4        cparent-clk sel-clk spi-clk        	  Ydisabled          spi@11018000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                <                      \   %   y   %      &   8        cparent-clk sel-clk spi-clk        	  Ydisabled          spi@11019000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +                                <                      \   %   y   %      &   9        cparent-clk sel-clk spi-clk        	  Ydisabled          usb@11201000          #    mediatek,mt8188-mtu3 mediatek,mtu3                       -     >              	  mac ippc                                 ?                      +           <                         %   )           %   v        \   5   	   %      5   
        csys_ck ref_ck mcu_ck               G      H                       I  h           Yokay            otg                     J        n   K        `default    usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 mac         <                         %   *           %   v        \   5   
        csys_ck          Yokay               J                     +       hub@1             usb451,8025                    $   L        -   "               9   M        ^   N      hub@2             usb451,8027                    $   N        -   "               9   M        ^   L      port       endpoint            D   O        ^   y            port       endpoint            D   P        ^   x            ethernet@11021000         ;    mediatek,mt8188-gmac mediatek,mt8195-gmac snps,dwmac-5.10a                     @         <                     Tmacirq        0  \   5       5      %   A   %   B   %   C   5         .  caxi apb mac_main ptp_ref rmii_internal mac_cg              %   A   %   B   %   C           %      %      %           K   :           d   &        u   Q           R           S                                          Yokay          	  rgmii-id               T        `default sleep           n   U           V                    "               	      '  '   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916                       ^   T         stmmac-axi-config           	"                                 	,           	<           ^   Q      rx-queues-config            	L            	b        ^   R   queue0           	s        	          queue1           	s        	          queue2           	s        	          queue3           	s        	             tx-queues-config            	            	        ^   S   queue0           	s        	            	         queue1           	s        	           	         queue2           	s        	           	         queue3           	s        	           	               mmc@11230000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              #                              <                       \   %      &      &      &   M      !  csource hclk source_cg crypto_clk            Yokay            `default state_uhs           n   W           X        	           	          	         

         
         
(         
5         
F         
N        
T H        
c   Y        
o   Z         
|      mmc@11240000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              $                              <                      \   %      &      &   $        csource hclk source_cg              %              %           Yokay            `default state_uhs           n   [           \        	           	          
         
         
         
         
F        
   "              
c   ]        
o   ^      mmc@11250000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc              %                              <                      \   %      &      &   A        csource hclk source_cg              %              %         	  Ydisabled          thermal-sensor@11278000           mediatek,mt8188-lvts-mcu                '                <                      \   &           Y   &               D        lvts-calib-data-1                      ^         i2c@11280000              mediatek,mt8188-i2c              (             "                <                      
           \   _       &   7      	  cmain dma                         +            Yokay            `default         n   `            touchscreen@5d            goodix,gt9271              ]            "        
   "              
   "               -   "               
   a        
   b        `default         n   c         i2c@11281000              mediatek,mt8188-i2c              (            "               <                      
           \   _      &   7      	  cmain dma                         +            Yokay            `default         n   d               i2c@11282000              mediatek,mt8188-i2c              (             "               <                      
           \   _      &   7      	  cmain dma                         +            Yokay            `default         n   e               clock-controller@11283000             mediatek,mt8188-imp-iic-wrap-c              (0                           ^   _      usb@112a1000          #    mediatek,mt8188-mtu3 mediatek,mtu3               *       -    *>              	  mac ippc                        *        ?                      +           <                        %   -           %   v        \   5      %      5           csys_ck ref_ck mcu_ck               f                       I  p           Yokay            otg         	high-speed          host                        J        `default         n   g   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 mac         <                        %   .           %   v        \   5           csys_ck          Yokay               J        0   h      connector         %    gpio-usb-b-connector usb-b-connector            micro           <   "   Y           0   i         usb@112b1000          #    mediatek,mt8188-mtu3 mediatek,mtu3               +       -    +>              	  mac ippc                        +        ?                      +           <                        %   ,           %   v        \   5      %      5           csys_ck ref_ck mcu_ck               j                       I  `           Yokay            otg         	high-speed                      J        n   k        `default    usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci                                 mac         <                        %   +           %   v        \   5           csys_ck          Yokay          connector         %    gpio-usb-b-connector usb-b-connector            micro           <   "   S            0   l         pcie@112f0000         *    mediatek,mt8188-pcie mediatek,mt8192-pcie               /                	  pcie-mac                                              E               pci         O                         +         0  \   &   L   &   #   &   &   &   +   &   C   5         /  cpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ,           <                   `  `                  m                      m                     m                     m           n                              n                             o         	  pcie-phy            K   :           Y   ;           `mac         Yokay            `default         n   p   interrupt-controller                         ,            T        ^   m         spi@1132c000          (    mediatek,mt8188-nor mediatek,mt8186-nor             2                \   %   X   5      5           cspi sf axi             %   X        <      9                            +          	  Ydisabled          t-phy@11c20700        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                                            +           K   :           Yokay       pcie-phy@0                         \   %           cref                    ^   o         dsi-phy@11c80000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx                              \   9        mipi_tx0_pll                                    Yokay            ^         dsi-phy@11c90000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx                              \   9        mipi_tx0_pll                                  	  Ydisabled            ^         i2c@11e00000              mediatek,mt8188-i2c                           "                <                      
           \   q       &   7      	  cmain dma                         +            Yokay            `default         n   r            typec-mux@48              ite,it5205             H                             s   port       endpoint            D   t        ^   z               i2c@11e01000              mediatek,mt8188-i2c                          "               <                      
           \   q      &   7      	  cmain dma                         +            Yokay            `default         n   u         B@   rt1715@4e             richtek,rt1715             N        
   "              `default         n   v        0   w   connector             usb-c-connector         USB-C           dual                     dual            sink                     !"        +"   altmodes       displayport         7          < G         ports                        +       port@0                 endpoint            D   x        ^   P         port@1                endpoint            D   y        ^   O         port@2                endpoint            D   z        ^   t                     clock-controller@11e02000             mediatek,mt8188-imp-iic-wrap-w                                          ^   q      t-phy@11e30000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                Yokay       usb-phy@0                          \   %      $           cref da_ref                     ^   j         t-phy@11e40000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                Yokay       usb-phy@0                          \   %      $           cref da_ref                     ^   G      usb-phy@700                       \   $      9        cref da_ref                     ^   H         t-phy@11e80000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                Yokay       usb-phy@0                          \   %      $           cref da_ref                     ^   f         i2c@11ec0000              mediatek,mt8188-i2c                           "               <                      
           \   {       &   7      	  cmain dma                         +            Yokay            `default         n   |               i2c@11ec1000              mediatek,mt8188-i2c                          "                <                      
           \   {      &   7      	  cmain dma                         +            Yokay            `default         n   }               clock-controller@11ec2000              mediatek,mt8188-imp-iic-wrap-en                                         ^   {      efuse@11f20000        ,    mediatek,mt8188-efuse mediatek,mt8186-efuse                                           +      dp-calib@1a0                         ^         lvts1-calib@1ac              @        ^   D      gpu-speedbin@581                         @               ^         socinfo-data1@7a0                      socinfo-data2@7e0                         gpu@13000000          )    mediatek,mt8370-mali arm,mali-valhall-jm                         @         \   ~          0  <                   ~             }               Tjob mmu gpu                  
  speed-bin           E           K   :      :           Ycore0 core1         O           Yokay            l   #        ^          clock-controller@13fbf000             mediatek,mt8188-mfgcfg                                         ^   ~      syscon@14000000           mediatek,mt8188-vppsys0 syscon                                           ^   (      dma-controller@14001000           mediatek,mt8188-mdp3-rdma                                x           \   (         <  ~                                                                   K   :                                                       display@14002000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                               \   (                                display@14004000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                @                \   (   "                 @          display@14005000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal                P                <      F               \   (   
        K   :                    P          display@14006000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                \   (                    `                %      display@14007000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                p                \   (   #                 p          display@14008000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                                <      I               \   (   $        K   :                              display@14009000          2    mediatek,mt8188-mdp3-ovl mediatek,mt8195-mdp3-ovl                                <      J               \   (   %        K   :                                            display@1400a000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                                \   (           K   :                              display@1400b000          2    mediatek,mt8188-mdp3-tcc mediatek,mt8195-mdp3-tcc                                \   (                              display@1400c000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot                              x           \   (                         K   :                                    +      mutex@1400f000            mediatek,mt8188-vpp-mutex                                <      P               \   (           K   :                              smi@14012000              mediatek,mt8188-smi-common-vpp                               \   (      (           capb smi         K   :           ^         smi@14013000              mediatek,mt8188-smi-larb                0                \   (      (           capb smi         K   :                                 ^         iommu@14018000            mediatek,mt8188-iommu-vpp                      P         \   (           cbclk            <      R               K   :           $                                     ^         dma-controller@14f09000           mediatek,mt8188-mdp3-rdma                               x           \   *   
                      K   :                 	                        dma-controller@14f0a000           mediatek,mt8188-mdp3-rdma                               x           \   *                         K   :                 	                        display@14f0c000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                             \   *                 	            display@14f0d000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg                             \   *                 	            display@14f0f000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                               \   *   "              	            display@14f10000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr                                \   *   $              
             display@14f12000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal                                <      j               \   *   #        K   :                 
             display@14f13000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal               0                <      k               \   *   %        K   :                 
  0          display@14f15000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz               P                \   *                 
  P                      display@14f16000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz               `                \   *                 
  `                      display@14f18000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                               \   *                 
            display@14f19000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp                               \   *                 
            display@14f1a000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge                               \   *           K   :                 
            display@14f1b000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge                               \   *           K   :                 
            display@14f1d000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                               <      u               \   *           K   :                 
            display@14f1e000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color                               <      v               \   *           K   :                 
            display@14f21000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                               \   *           K   :                             display@14f22000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding                                \   *           K   :                              display@14f24000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot             @                x           \   *                         K   :                   @                      display@14f25000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot             P                x           \   *                         K   :                   P                      clock-controller@14e00000             mediatek,mt8188-wpesys                                          ^   4      clock-controller@14e02000             mediatek,mt8188-wpesys-vpp0                                       smi@14e04000              mediatek,mt8188-smi-larb                @                \   4      4           capb smi         K   :                                 ^         syscon@14f00000           mediatek,mt8188-vppsys1 syscon                                          ^   *      mutex@14f01000            mediatek,mt8188-vpp-mutex                               <      {               \   *   &        K   :                 	            smi@14f02000              mediatek,mt8188-smi-larb                                 \   *      *           capb smi         K   :                                 ^         smi@14f03000              mediatek,mt8188-smi-larb                0                \   *      *           capb smi         K   :                                 ^         clock-controller@15000000             mediatek,mt8188-imgsys                                         clock-controller@15110000              mediatek,mt8188-imgsys1-dip-top                                         r         clock-controller@15130000             mediatek,mt8188-imgsys1-dip-nr                                          r         clock-controller@15220000             mediatek,mt8188-imgsys-wpe1             "                            r         clock-controller@15330000             mediatek,mt8188-ipesys              3                            r         clock-controller@15520000             mediatek,mt8188-imgsys-wpe2             R                            r         clock-controller@15620000             mediatek,mt8188-imgsys-wpe3             b                            r         clock-controller@16000000             mediatek,mt8188-camsys                                           ^   -      clock-controller@1604f000             mediatek,mt8188-camsys-rawa                                        r           ^   0      clock-controller@1606f000             mediatek,mt8188-camsys-yuva                                        r           ^   1      clock-controller@1608f000             mediatek,mt8188-camsys-rawb                                        r           ^   .      clock-controller@160af000             mediatek,mt8188-camsys-yuvb             
                           r           ^   /      clock-controller@17200000             mediatek,mt8188-ccusys                                         video-decoder@18000000            mediatek,mt8188-vcodec-dec                              @                                    `                                   +                 video-codec@10000             mediatek,mtk-vcodec-lat                                  %   4           %   x         \   %   4   +      +      %   x        csel vdec lat top            <                   H                                                       K   :         video-codec@25000             mediatek,mtk-vcodec-core                 P                   %   4           %   x         \   %   4   ,      ,      %   x        csel vdec lat top            <                   X                                                                 K   :            smi@1800d000              mediatek,mt8188-smi-larb                                 \   +       +            capb smi         K   :                                 ^         clock-controller@1800f000             mediatek,mt8188-vdecsys-soc                                         ^   +      smi@1802e000              mediatek,mt8188-smi-larb                                \   ,       ,            capb smi         K   :                                 ^         clock-controller@1802f000             mediatek,mt8188-vdecsys                                        ^   ,      clock-controller@1a000000             mediatek,mt8188-vencsys                                          ^   3      smi@1a010000              mediatek,mt8188-smi-larb                                 \   3      3           capb smi         K   :                                 ^         video-encoder@1a020000            mediatek,mt8188-vcodec-enc                                            +              %   3           %   p        \   3         	  cvenc_sel            <      a             X                                                                 K   :                    jpeg-encoder@1a030000         +    mediatek,mt8188-jpgenc mediatek,mtk-jpgenc                               \   3           cjpgenc          <      b                                            K   :         jpeg-decoder@1a040000         .    mediatek,mt8188-jpgdec mediatek,mt2701-jpgdec                                \   3       3           cjpgdec-smi jpgdec           <      c             0                                        K   :         ovl@1c000000          2    mediatek,mt8188-disp-ovl mediatek,mt8195-disp-ovl                                 \   )            <      |                             K   :                           ports                        +       port@0                 endpoint            D           ^            port@1                endpoint            D           ^                  rdma@1c002000         4    mediatek,mt8188-disp-rdma mediatek,mt8195-disp-rdma                               \   )           <      ~                              K   :                           ports                        +       port@0                 endpoint            D           ^            port@1                endpoint            D           ^                  color@1c003000        6    mediatek,mt8188-disp-color mediatek,mt8173-disp-color                0                \   )           <                     K   :                   0       ports                        +       port@0                 endpoint            D           ^            port@1                endpoint            D           ^                  ccorr@1c004000        6    mediatek,mt8188-disp-ccorr mediatek,mt8192-disp-ccorr                @                \   )           <                     K   :                   @       ports                        +       port@0                 endpoint            D           ^            port@1                endpoint            D           ^                  aal@1c005000          2    mediatek,mt8188-disp-aal mediatek,mt8183-disp-aal                P                \   )           <                     K   :                   P       ports                        +       port@0                 endpoint            D           ^            port@1                endpoint            D           ^                  gamma@1c006000        6    mediatek,mt8188-disp-gamma mediatek,mt8195-disp-gamma                `                \   )           <                     K   :                   `       ports                        +       port@0                 endpoint            D           ^            port@1                endpoint            D           ^                  dither@1c007000       8    mediatek,mt8188-disp-dither mediatek,mt8183-disp-dither              p                \   )           <                     K   :                   p       ports                        +       port@0                 endpoint            D           ^            port@1                endpoint            D           ^                  dsi@1c008000              mediatek,mt8188-dsi                              \   )      )              cengine digital hs           <                                dphy            K   :           Y   )           Yokay                         +       panel@0       #    startek,kd070fhfid078 himax,hx8279                                    "   -            -   "                          9           `default         n      port       endpoint            D           ^               ports                        +       port@0                 endpoint            D           ^            port@1                endpoint            D           ^                  dsc@1c009000          2    mediatek,mt8188-disp-dsc mediatek,mt8195-disp-dsc                                \   )   
        <                     K   :                             dsi@1c012000              mediatek,mt8188-dsi                              \   )   	   )              cengine digital hs           <                                dphy            K   :           Y   )   	      	  Ydisabled          merge0@1c014000       6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge               @                \   )      2           cmerge merge_async           <                     K   :                   @          dp-intf@1c015000              mediatek,mt8188-dp-intf             P                \   )       )      $           cpixel engine pll            <                     K   :         	  Ydisabled          mutex@1c016000            mediatek,mt8188-disp-mutex              `                \   )           <                     K   :                   `              >      postmask@1c01a000         <    mediatek,mt8188-disp-postmask mediatek,mt8192-disp-postmask                             \   )           <                     K   :                          ports                        +       port@0                 endpoint            D           ^            port@1                endpoint            D           ^                  syscon@1c01d000           mediatek,mt8188-vdosys0 syscon                                         r           ~                                      ^   )   port                         +       endpoint@0                      D           ^               smi@1c022000              mediatek,mt8188-smi-larb                                 \   )      )           capb smi         K   :                                  ^         smi@1c023000              mediatek,mt8188-smi-larb                0                \   )      )           capb smi         K   :                                 ^         smi@1c024000              mediatek,mt8188-smi-common-vdo              @                \   )      )           capb smi         K   :           ^         iommu@1c028000            mediatek,mt8188-iommu-vdo                      P         \   )           cbclk            <                     K   :           $                                  ^         syscon@1c100000           mediatek,mt8188-vdosys1 syscon                                          r           ~                                      ^   2      mutex@1c101000            mediatek,mt8188-disp-mutex                              \   2           <                     K   :                                       smi@1c102000              mediatek,mt8188-smi-larb                                 \   2       2            capb smi         K   :                                 ^         smi@1c103000              mediatek,mt8188-smi-larb                0                \   2      2           capb smi         K   :                                 ^         rdma@1c104000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             @                \   2           <                           @        K   :           x                   @          rdma@1c105000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             P                \   2           <                           `        K   :           x                   P          rdma@1c106000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             `                \   2           <                           A        K   :           x                   `          rdma@1c107000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma             p                \   2           <                           a        K   :           x                   p          rdma@1c108000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             \   2           <                           B        K   :           x                             rdma@1c109000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             \   2           <                           b        K   :           x                             rdma@1c10a000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             \   2           <                           C        K   :           x                             rdma@1c10b000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma                             \   2           <                           c        K   :           x                             merge@1c10c000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               \   2   	   2           cmerge merge_async           <                     K   :           Y   2                                      merge@1c10d000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               \   2   
   2           cmerge merge_async           <                     K   :           Y   2                                      merge@1c10e000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               \   2      2           cmerge merge_async           <                     K   :           Y   2                                      merge@1c10f000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                               \   2      2           cmerge merge_async           <                     K   :           Y   2                                      merge@1c110000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge                                \   2      2           cmerge merge_async           <                     K   :           Y   2                                 (      dp-intf@1c113000              mediatek,mt8188-dp-intf             0                \   2   :   2      $           cpixel engine pll            <                     K   :         	  Ydisabled          ethdr@1c114000        6    mediatek,mt8188-disp-ethdr mediatek,mt8195-disp-ethdr         p      @            P            p                                                              4  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       h  \   2   0   2   +   2   .   2   ,   2   /   2   -   2   <   2   1   2   2   2   3   2   4   2   5   %           cmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          <      6                     d      e        K   :         (  Y   2   1   2   2   2   3   2   4   2   5      p          @            P            p                                                          padding@1c11d000              mediatek,mt8188-disp-padding                                \   2           K   :                             padding@1c11e000              mediatek,mt8188-disp-padding                                \   2            K   :                             padding@1c11f000              mediatek,mt8188-disp-padding                                \   2   !        K   :                             padding@1c120000              mediatek,mt8188-disp-padding                                 \   2   "        K   :                              padding@1c121000              mediatek,mt8188-disp-padding                                \   2   #        K   :                             padding@1c122000              mediatek,mt8188-disp-padding                                 \   2   $        K   :                              padding@1c123000              mediatek,mt8188-disp-padding                0                \   2   %        K   :                   0          padding@1c124000              mediatek,mt8188-disp-padding                @                \   2   &        K   :                   @          edp-tx@1c500000           mediatek,mt8188-edp-tx              P                 <                                dp_calibration_data         K   :           ?        	  Ydisabled          dp-tx@1c600000            mediatek,mt8188-dp-tx               `                 <                                dp_calibration_data         K   :           ?        	  Ydisabled             backlight-lcm1            pwm-backlight           P              b  @        {                                      ^         chosen          serial0:921600n8          dmic-codec                        dmic-codec                                ^         firmware       optee             linaro,optee-tz         smc          reserved-memory                      +               optee@43200000                       C                memory@50000000           shared-dma-pool             P                          ^   8      memory@54600000                      T`                memory@55000000           shared-dma-pool             U       @        memory@57000000           shared-dma-pool             W       @        memory@60000000           shared-dma-pool             `                           ^   @      memory@60f00000           shared-dma-pool             `                          ^   <      memory@61000000           shared-dma-pool             a                           ^   ?         regulator-0           regulator-fixed         vdd_5v           LK@         LK@        	   "   
                      ?                 regulator-1           regulator-fixed       	  vedp_3v3             2Z         2Z                 	   "               `default         n                    regulator-2           regulator-fixed         ext_3v3          2Z         2Z        	   "   	                      ?                 regulator-vsys            regulator-fixed         vsys             ?                 ^         regulator-3           regulator-fixed         vio18_conn           w@         w@                  ?      regulator-4           regulator-fixed       	  wifi_3v3             2Z         2Z        	   "   J                      ?                   ^   h      regulator-5           regulator-fixed       
  vio33_tp1            2Z         2Z        	   "   w                                `default         n           ^   a      regulator-6           regulator-fixed       	  vhub_3v3             2Z         2Z        	   "   p              '                            ^   M      regulator-7           regulator-fixed         vbus_p0          LK@         LK@        	   "   T                                ^   l      regulator-8           regulator-fixed         vbus_p1          LK@         LK@        	   "   W                                ^   w      regulator-9           regulator-fixed         vbus_p2          LK@         LK@                 ^   i      regulator-vio18-lcm1              regulator-fixed         vio18_lcm1           w@         w@                 	   "   o            `default         n                      ^         regulator-vsys-lcm1           regulator-fixed       
  vsys_lcm1            @@         @@         ?                            ^         memory@40000000         memory              @                   	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dsc0 ethdr0 gce0 gce1 merge0 merge1 merge2 merge3 merge4 merge5 mutex0 mutex1 padding0 padding1 padding2 padding3 padding4 padding5 padding6 padding7 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 dsi0 ethernet0 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 mmc0 mmc1 serial0 device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-output-names opp-shared opp-hz opp-microvolt opp-supported-hw interrupts mediatek,platform status pinctrl-names pinctrl-0 audio-routing mediatek,adsp link-name sound-dai polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux bias-pull-up output-high drive-strength input-enable input-disable bias-disable drive-strength-microamp bias-pull-down output-low #power-domain-cells domain-supply clocks clock-names mediatek,infracfg mediatek,disable-extrst #sound-dai-cells #io-channel-cells mediatek,mic-type-0 mediatek,mic-type-1 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread mediatek,long-press-mode power-off-time-sec linux,keycodes wakeup-source assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells memory-region power-domains resets reset-names mediatek,topckgen mboxes mbox-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select phys mediatek,syscon-wakeup dr_mode usb-role-switch vusb33-supply peer-hub reset-gpios vdd-supply remote-endpoint interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,mac-wol snps,reset-gpio snps,reset-delays-us snps,blen snps,rd_osr_lmt snps,wr_osr_lmt snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,priority snps,weight bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v supports-cqe cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc cd-gpios clock-div interrupts-extended irq-gpios AVDD28-supply VDDIO-supply maximum-speed role-switch-default-mode vbus-supply id-gpios bus-range linux,pci-domain interrupt-map interrupt-map-mask iommu-map iommu-map-mask phy-names #phy-cells mode-switch orientation-switch vcc-supply label data-role op-sink-microwatt power-role try-power-role pd-revision sink-pdos source-pdos svid vdo bits operating-points-v2 power-domain-names mali-supply #dma-cells iommus mediatek,gce-client-reg mediatek,gce-events mediatek,scp mediatek,larb-id mediatek,smi mediatek,larbs backlight enable-gpios iovcc-supply mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz brightness-levels default-brightness-level num-interpolated-steps power-supply pwms stdout-path num-channels wakeup-delay-ms no-map enable-active-high vin-supply regulator-boot-on startup-delay-us 