 M@   8 ?   (            0 >                             -    google,ciri-sku3 google,ciri mediatek,mt8188                                     +            7Google Ciri sku3 board     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dsc@1c009000            T/soc/ethdr@1c114000          [/soc/mailbox@10320000            `/soc/mailbox@10330000            e/soc/merge0@1c014000             l/soc/merge@1c10c000          s/soc/merge@1c10d000          z/soc/merge@1c10e000          /soc/merge@1c10f000          /soc/merge@1c110000          /soc/mutex@1c016000          /soc/mutex@1c101000          /soc/padding@1c11d000            /soc/padding@1c11e000            /soc/padding@1c11f000            /soc/padding@1c120000            /soc/padding@1c121000            /soc/padding@1c122000            /soc/padding@1c123000            /soc/padding@1c124000            /soc/rdma@1c104000           /soc/rdma@1c105000           /soc/rdma@1c106000          /soc/rdma@1c107000          /soc/rdma@1c108000          /soc/rdma@1c109000          '/soc/rdma@1c10a000          2/soc/rdma@1c10b000          =/soc/dsi@1c008000           B/soc/i2c@11280000           G/soc/i2c@11e00000           L/soc/i2c@11281000           Q/soc/i2c@11282000           V/soc/i2c@11e01000           [/soc/i2c@11ec0000           `/soc/i2c@11ec1000           e/soc/mmc@11230000           j/soc/serial@11001100          cpus                         +       cpu@0           rcpu           arm,cortex-a55          ~            psci            w5                                               @                                 @                              ,               @           O   	      cpu@100         rcpu           arm,cortex-a55          ~           psci            w5                                               @                                 @                              ,               @           O   
      cpu@200         rcpu           arm,cortex-a55          ~           psci            w5                                               @                                 @                              ,               @           O         cpu@300         rcpu           arm,cortex-a55          ~           psci            w5                                               @                                 @                              ,               @           O         cpu@400         rcpu           arm,cortex-a55          ~           psci            w5                                               @                                 @                              ,               @           O         cpu@500         rcpu           arm,cortex-a55          ~           psci            w5                                               @                                 @                              ,               @           O         cpu@600         rcpu           arm,cortex-a78          ~           psci                                                            @                                 @                              ,              @           O         cpu@700         rcpu           arm,cortex-a78          ~           psci                                                            @                                 @                              ,              @           O         cpu-map    cluster0       core0           W   	      core1           W   
      core2           W         core3           W         core4           W         core5           W         core6           W         core7           W               idle-states         [psci       cpu-off-l             arm,idle-state          h                       2           _          D        O         cpu-off-b             arm,idle-state          h                       -                             O         cluster-off-l             arm,idle-state          h                     7                     H        O         cluster-off-b             arm,idle-state          h                     2                             O            l2-cache0             cache                                    @                                       O         l2-cache1             cache                                    @                                       O         l3-cache              cache                                     @                            O            oscillator-13m            fixed-clock                      ]@        clk13m          O   A      oscillator-26m            fixed-clock                             clk26m          O   D      oscillator-32k            fixed-clock                                clk32k        opp-table-gpu             operating-points-v2                  O   z   opp-390000000               >                          opp-431000000                                         opp-473000000               1h@         	'                 opp-515000000               F         	X                 opp-556000000               !#          	h                 opp-598000000               #         	<                 opp-640000000               &%          	                 opp-670000000               'c         
                 opp-700000000               )'          
L                 opp-730000000               +         
}                 opp-760000000               -L          
`                 opp-790000000               /q         
4                 opp-835000000               1         (r                 opp-880000000               4s          q                 opp-915000000               6         X                 opp-915000000-5             6                    0      opp-915000000-6             6         q           p      opp-950000000               8ـ         5                  opp-950000000-5             8ـ         X           0      opp-950000000-6             8ـ         q           p         pmu-a55           arm,cortex-a55-pmu                      -                  pmu-a78           arm,cortex-a78-pmu                      -                  psci              arm,psci-1.0            smc       sound           8           Jokay          ]  Qaud_etdm_hp_on aud_etdm_hp_off aud_etdm_spk_on aud_etdm_spk_off aud_mtkaif_on aud_mtkaif_off            _           i           s           }                                              mediatek,mt8188-rt5682s          7mt8188_m98390_5682          ETDM1_OUT ETDM_SPK_PIN ETDM2_OUT ETDM_HP_PIN ETDM1_IN ETDM_SPK_PIN ETDM2_IN ETDM_HP_PIN ADDA Capture MTKAIF_PIN Headphone Jack HPOL Headphone Jack HPOR IN1P Headset Mic Left Spk Front Left BE_OUT Right Spk Front Right BE_OUT       dai-link-0          ETDM1_IN_BE         i2s         cpu       dai-link-1          ETDM1_OUT_BE            i2s         cpu    codec                          dai-link-2          ETDM2_IN_BE         cpu    codec                           dai-link-3          ETDM2_OUT_BE            cpu    codec                           dai-link-4          DPTX_BE    codec                          thermal-zones      cpu-little0-thermal                                         trips      trip-alert0           _        ,          ypassive         O   !      trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical             cooling-maps       map0            7   !      H  <   	   
                        cpu-little1-thermal                                        trips      trip-alert0           _        ,          ypassive         O   "      trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical             cooling-maps       map0            7   "      H  <   	   
                        cpu-little2-thermal                                        trips      trip-alert0           _        ,          ypassive         O   #      trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical             cooling-maps       map0            7   #      H  <   	   
                        cpu-little3-thermal                                        trips      trip-alert0           _        ,          ypassive         O   $      trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical             cooling-maps       map0            7   $      H  <   	   
                        cpu-big0-thermal                         d                  trips      trip-alert0           _        ,          ypassive         O   %      trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical             cooling-maps       map0            7   %        <                  cpu-big1-thermal                         d                  trips      trip-alert0           _        ,          ypassive         O   &      trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical             cooling-maps       map0            7   &        <                  apu-thermal                                 '       trips      trip-alert0           L        ,          ypassive       trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical                gpu-thermal                                 '      trips      trip-alert0           L        ,          ypassive         O   (      trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical             cooling-maps       map0            7   (        <   )            gpu1-thermal                                    '      trips      trip-alert0           L        ,          ypassive         O   *      trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical             cooling-maps       map0            7   *        <   )            adsp-thermal                                    '      trips      trip-alert0           L        ,          ypassive       trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical                vdo-thermal                                 '      trips      trip-alert0           L        ,          ypassive       trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical                infra-thermal                                   '      trips      trip-alert0           L        ,          ypassive       trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical                cam1-thermal                                    '      trips      trip-alert0           L        ,          ypassive       trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical                cam2-thermal                                    '      trips      trip-alert0           L        ,          ypassive       trip-alert1           s        ,          yhot       trip-crit                     ,          	  ycritical                   timer             arm,armv8-timer                   @  -                                             
                ]@      soc                      +             simple-bus          K                                O   performance-controller@11bc10             mediatek,cpufreq-hw          ~                 0               V           O         interrupt-controller@c000000              arm,gic-v3          p                                            ~                                    -      	               O      ppi-partitions     interrupt-partition-0              	   
                    O         interrupt-partition-1                         O               syscon@10000000            mediatek,mt8188-topckgen syscon         ~                                 O   .      syscon@10001000       #    mediatek,mt8188-infracfg-ao syscon          ~                                           O   /      syscon@10003000           mediatek,mt8188-pericfg syscon          ~     0                           O   X      pinctrl@10005000              mediatek,mt8188-pinctrl       `  ~     P                                                                               0  iocfg0 iocfg_rm iocfg_lt iocfg_lm iocfg_rt eint                                +                            -                      p        B  GSC_AP_INT_ODL AP_DISP_BKLTEN  EN_PPVAR_MIPI_DISP EN_PPVAR_MIPI_DISP_150MA TCHSCR_RST_1V8_L      I2S_SPKR_DATAOUT EN_PP3300_WLAN_X WIFI_KILL_1V8_L BT_KILL_1V8_L AP_FLASH_WP_L   WCAM_PWDN_L WCAM_RST_L UCAM_PWDM_L UCAM_RST_L WCAM_24M_CLK UCAM_24M_CLK MT6319_INT DISP_RST_1V8_L DSIO_DSI_TE  TP MIPI_BL_PWM_1V8  UART_AP_TX_GSC_RX UART_GSC_TX_AP_RX UART_SSPM_TX_DBGCON_RX UART_DBGCON_TX_SSPM_RX UART_ADSP_TX_DBGCON_RX UART_DBGCON_TX_ADSP_RX JTAG_AP_TMS JTAG_AP_TCK JTAG_AP_TDI JTAG_AP_TDO JTAG_AP_TRST AP_KPCOL0 TP  TP EC_AP_HPD_OD PCIE_WAKE_1V8_ODL PCIE_RST_1V8_L PCIE_CLKREQ_1V8_ODL      AP_I2C_AUD_SCL_1V8 AP_I2C_AUD_SDA_1V8 AP_I2C_TPM_SCL_1V8 AP_I2C_TPM_SDA_1V8 AP_I2C_TCHSCR_SCL_1V8 AP_I2C_TCHSCR_SDA_1V8 AP_I2C_PMIC_SAR_SCL_1V8 AP_I2C_PMIC_SAR_SDA_1V8 AP_I2C_EC_HID_KB_SCL_1V8 AP_I2C_EC_HID_KB_SDA_1V8 AP_I2C_UCAM_SCL_1V8 AP_I2C_UCAM_SDA_1V8 AP_I2C_WCAM_SCL_1V8 AP_I2C_WCAM_SDA_1V8 SPI_AP_CS_EC_L SPI_AP_CLK_EC SPI_AP_DO_EC_DI SPI_AP_DI_EC_DO TP TP SPI_AP_CS_TCHSCR_L SPI_AP_CLK_TCHSCR SPI_AP_DO_TCHSCR_DI SPI_AP_DI_TCHSCR_DO TP TP TP TP    TP      PWRAP_SPI_CS_L PWRAP_SPI_CK PWRAP_SPI_MOSI PWRAP_SPI_MISO SRCLKENA0 SRCLKENA1 SCP_VREQ_VAO AP_RTC_CLK32K AP_PMIC_WDTRST_L AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1  HP_INT_ODL SPKR_INT_ODL I2S_HP_DATAIN EN_SPKR I2S_SPKR_MCLK I2S_SPKR_BCLK I2S_HP_MCLK I2S_HP_BCLK I2S_HP_LRCK I2S_HP_DATAOUT RST_SPKR_L I2S_SPKR_LRCK I2S_SPKR_DATAIN     SPI_AP_CLK_ROM SPI_AP_CS_ROM_L SPI_AP_DO_ROM_DI SPI_AP_DI_ROM_DO TP TP         EN_PP2800A_UCAM_X EN_PP1200_UCAM_X EN_PP2800A_WCAM_X EN_PP1100_WCAM_X TCHSCR_INT_1V8_L  MT7921_PMU_EN_1V8  AP_EC_WARM_RST_REQ EC_AP_HID_INT_ODL EC_AP_INT_ODL AP_XHCI_INIT_DONE EMMC_DAT7 EMMC_DAT6 EMMC_DAT5 EMMC_DAT4 EMMC_RST_L EMMC_CMD EMMC_CLK EMMC_DAT3 EMMC_DAT2 EMMC_DAT1 EMMC_DAT0 EMMC_DSL         USB3_HUB_RST_L EC_AP_RSVD0_ODL   SPMI_SCL SPMI_SDA           O   +   adsp-uart-pins          O   L   pins-bus              #  $         aud-etdm-hp-on-pins         O      pins-bus              n  s  t  u      pins-mclk             r         aud-etdm-hp-off-pins            O      pins-bus              n   s   t   u                         pins-mclk             r                            aud-etdm-spk-on-pins            O      pins-bus                q  w  x        (            aud-etdm-spk-off-pins           O      pins-bus                 q   w   x                            aud-mtkaif-on-pins          O      pins-bus              e  f  g  h  i  j         aud-mtkaif-off-pins         O      pins-bus              e   f   g   h   i   j                            cros-ec-int-pins            O   O   pins-ec-ap-int-odl                               disp-pwm0-pins          O   Q   pins-disp-pwm0                     7         disp-pwm1-pins          O   R   pins-disp-pwm1                     7         dp-tx-hpd-pins          O      pins-dp-tx-hpd            .         gsc-int-pins            O   s   pins-gsc-ap-int-odl                               i2c0-pins           O   c   pins-bus              8  7         i2c1-pins           O   r   pins-bus              :  9         i2c2-pins           O   g   pins-bus              <  ;         C        (            i2c3-pins           O   h   pins-bus              >  =         i2c4-pins           O   t   pins-bus              @  ?         i2c5-pins           O   v   pins-bus              B  A         i2c6-pins           O   w   pins-bus              D  C         mipi-disp-avdd-en-pins          O      pins-en-ppvar-mipi-disp                     P         mipi-disp-avee-en-pins          O      pins-en-ppvar-mipi-disp-150ma                       P         mipi-dsi-pins           O      pins-bus                           P         mmc0-default-pins           O   ^   pins-bus          $                                     (           [   e      pins-clk                      (              f      pins-rst                      (           [   e         mmc0-uhs-pins           O   _   pins-bus          $                                     (           [   e      pins-clk                      (              f      pins-ds                   (              f      pins-rst                      (           [   e         nor-default-pins            O   p   pins-clk                }                 pins-cs           ~         [         pcie-default-pins           O   o   pins-bus              /  0  1         scp-pins            O   B   pins-scp-vreq             b         C         spi0-pins           O   N   pins-bus              E  F  G  H         C         spi1-default-pins           O   S   pins-bus              K  L  M  N         C         spi1-sleep-pins         O   T   pins-bus              K   L   M   N                            spi2-pins           O   U   pins-bus              O  P  Q  R         C         uart0-pins          O   M   pins-bus                          [         wlan-en-pins            O      pins-en-pp3300-wlan                     P         audio-codec-pins            O   d   pins-hp-int-odl           l                   speaker-en-pins         O   f   pins-en-spkr              o             syscon@10006000       )    mediatek,mt8188-scpsys syscon simple-mfd            ~     `           power-controller          !    mediatek,mt8188-power-controller                         +            h           O   E   power-domain@0          ~                         +            h           |   ,   power-domain@1          ~              -      .           mfg alt            /                     +            h           |   0   power-domain@2          ~           h          power-domain@3          ~           h          power-domain@4          ~           h                power-domain@15         ~              .      .      .      .   
   .   3   .   4   .   =   .      .      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1            top cam ccu img venc vdec wpe cfgck cfgxo ss-sram-cmn ss-sram-v0l0 ss-sram-v0l1 ss-sram-ve0 ss-sram-ve1 ss-sram-ifa ss-sram-cam ss-sram-v1l5 ss-sram-v1l6 ss-sram-rdr ss-iommu ss-imgcam ss-emi ss-subcmn-rdr ss-rsi ss-cmn-l4 ss-vdec1 ss-wpe ss-cvdo-ve1             /                     +            h      power-domain@16         ~         H     .      .      2      2      2      2      2      2      2         A  cfgck cfgxo ss-gals ss-cmn ss-emi ss-iommu ss-larb ss-rsi ss-bus               /                     +            h      power-domain@20         ~         0     .      .      3      3      3      3         8  cfgck cfgxo ss-vpp1-g5 ss-vpp1-g6 ss-vpp1-l5 ss-vpp1-l6            /        h          power-domain@22         ~              4            ss-vdec1-soc-l1            /                     +            h      power-domain@23         ~              5            ss-vdec2-l1            /        h             power-domain@29         ~               .      .      .   	   .           cam ccu bus cfgck              /                     +            h           |   6   power-domain@30         ~         (     7       7      7      7      7         6  ss-cam-l13 ss-cam-l14 ss-cam-mm0 ss-cam-mm1 ss-camsys              /                     +            h      power-domain@32         ~               7      8       9          $  ss-camb-sub ss-camb-raw ss-camb-yuv         h          power-domain@31         ~              7      :       ;          $  ss-cama-sub ss-cama-raw ss-cama-yuv         h                power-domain@17         ~         (     .      .      <       <      <         &  cfgck cfgxo ss-larb2 ss-larb3 ss-gals              /                     +            h      power-domain@9          ~   	           .   @   .   ?      	  bus hdcp               /        h          power-domain@18         ~              /        h          power-domain@19         ~              /        h             power-domain@24         ~               =       =      =      =         0  ss-ve1-larb ss-ve1-core ss-ve1-gals ss-ve1-sram            /        h          power-domain@21         ~              >      >           ss-wpe-l7 ss-wpe-l7pce             /        h                power-domain@5          ~              /           ?           ss-pextp-fmem           h          power-domain@7          ~              .   0   .   1        seninf0 seninf1         h          power-domain@6          ~           h          power-domain@10         ~   
           .   E   .   D      	  bus main               /                     +            h      power-domain@11         ~              /                     +            h      power-domain@14         ~              .   F        asm            /        h          power-domain@13         ~              .   S   .      @            a1sys intbus adspck            /        h          power-domain@12         ~              /        h                power-domain@8          ~              ?         	  ethermac               /        h                watchdog@10007000             mediatek,mt8188-wdt         ~     p                                    O   F      syscon@1000c000       "    mediatek,mt8188-apmixedsys syscon           ~                                O   -      timer@10017000        ,    mediatek,mt8188-timer mediatek,mt6765-timer         ~    p                -      	                  A      pwrap@10024000        3    mediatek,mt8188-pwrap mediatek,mt8195-pwrap syscon          ~    @                pwrap           -                         /      /          	  spi wrap       pmic              mediatek,mt6359                  p                         +         adc           mediatek,mt6359-auxadc                   audio-codec           mediatek,mt6359-codec                                 %         regulators            mediatek,mt6359-regulator      buck_vs1            9vs1         H 5         ` !        x                   buck_vgpu11         9vgpu11          H         ` 7                  x                                    buck_vmodem         9vmodem          H X        ` X          *        x         buck_vpu            9vpu         H         ` 7                  x                                    buck_vcore          9vcore           H         `                    x                                    buck_vs2            9vs2         H 5         ` j         x                   buck_vpa            9vpa         H          ` /M`        x  ,      buck_vproc2         9ppvar_dvdd_vgpu         H dp        ` 5           L        x                                0          j        O   ,      buck_vproc1         9vproc1          H         ` 7          L        x                             O   6      buck_vcore_sshub            9vcore_sshub         H         ` 7      buck_vgpu11_sshub           9vgpu11_sshub            H dp        ` dp               ldo_vaud18          9vaud18          H w@        ` w@        x         ldo_vsim1           9vsim1           H         ` /M`      ldo_vibr            9vibr            H O        ` 2Z      ldo_vrf12           9vrf12           H         `                 ldo_vusb            9vusb            H -        ` -        x                 ldo_vsram_proc2         9vsram_proc2         H          `           L        x                  ldo_vio18           9vio18           H         `         x                   O   e      ldo_vcamio          9vcamio          H         `       ldo_vcn18           9vcn18           H w@        ` w@        x         ldo_vfe28           9vfe28           H *        ` *        x   x      ldo_vcn13           9vcn13           H         `        ldo_vcn33_1_bt          9vcn33_1_bt          H *        ` 5g      ldo_vcn33_1_wifi            9vcn33_1_wifi            H *        ` 5g      ldo_vaux18          9vaux18          H w@        ` w@        x                  ldo_vsram_others            9pp0850_dvdd_sram_gpu            H q        ` 5                   x              ,          j        O   0      ldo_vefuse          9vefuse          H         `       ldo_vxo22           9vxo22           H w@        ` !               ldo_vrfck           9vrfck           H `        `       ldo_vrfck_1         9vrfck           H         ` j       ldo_vbif28          9vbif28          H *        ` *        x         ldo_vio28           9vio28           H *        ` 2Z      ldo_vemc            9vemc            H ,@         ` 2Z      ldo_vemc_1          9vemc            H &%        ` 2Z        O   `      ldo_vcn33_2_bt          9vcn33_2_bt          H *        ` 5g      ldo_vcn33_2_wifi            9vcn33_2_wifi            H *        ` 5g      ldo_va12            9va12            H O        `                 ldo_va09            9va09            H 5         ` O      ldo_vrf18           9vrf18           H         ` P      ldo_vsram_md          	  9vsram_md            H 5         ` 5           *        x         ldo_vufs            9vufs            H         `                  O   a      ldo_vm18            9vm18            H w@        `         	         O         ldo_vbbck           9vbbck           H         ` O      ldo_vsram_proc1         9vsram_proc1         H          `           L        x                  ldo_vsim2           9vsim2           H         ` /M`      ldo_vsram_others_sshub          9vsram_others_sshub          H          `          rtc           mediatek,mt6358-rtc             spmi@10027000         *    mediatek,mt8188-spmi mediatek,mt8195-spmi            ~    p                            pmif spmimst            $   .   8        4   .              /      /       .   8      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux       iommu@10315000            mediatek,mt8188-iommu-infra         ~    1P                -                     K           O   m      mailbox@10320000              mediatek,mt8188-gce         ~    2        @         -                      X              /           O   {      mailbox@10330000              mediatek,mt8188-gce         ~    3        @         -                      X              /           O   }      scp@10720000              mediatek,mt8188-scp-dual            ~    r                 cfg                      +           O        P             Jokay       scp@0             mediatek,scp-core           ~               sram            -                     Jokay            Qdefault         _   B        dmediatek/mt8188/scp.img         r   C        O   ~      scp@d0000             mediatek,scp-core           ~             sram            -                   	  Jdisabled             audio-controller@10b10000             mediatek,mt8188-afe         ~                     $   .   S        4   .              D   -   	   -   
   .      .      .      .      .      .   S   .      .       .   E   .   Q   .   M   .   N   .   O   .   P   @       .      .      .      .   T   .   R        clk26m apll1 apll2 apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 top_a1sys_hp top_aud_intbus top_audio_h top_audio_local_bus top_dptx top_i2so1 top_i2so2 top_i2si1 top_i2si2 adsp_audio_26m apll1_d4 apll2_d4 apll12_div4 top_a2sys top_aud_iec          -      6                  E              F         	  audiosys               /           .        Jokay            r   G                               O         adsp@10b80000             mediatek,mt8188-dsp       @  ~                                                           cfg sram sec bus            $   .   D           .   D   .   E        audiodsp adsp_bus              H   I        rx tx              E           Jokay            r   J   K        Qdefault         _   L        O         mailbox@10b86100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         ~    a                -                     X            O   H      mailbox@10b87100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         ~    q                -                     X            O   I      clock-controller@10b91100             mediatek,mt8188-adsp-audio26m           ~                               O   @      serial@11001100       *    mediatek,mt8188-uart mediatek,mt6577-uart           ~                     -                         D   /         	  baud bus            Jokay            Qdefault         _   M      serial@11001200       *    mediatek,mt8188-uart mediatek,mt6577-uart           ~                     -                         D   /         	  baud bus          	  Jdisabled          serial@11001300       *    mediatek,mt8188-uart mediatek,mt6577-uart           ~                     -                         D   /         	  baud bus          	  Jdisabled          serial@11001400       *    mediatek,mt8188-uart mediatek,mt6577-uart           ~                     -                        D   /         	  baud bus          	  Jdisabled          adc@11002000          .    mediatek,mt8188-auxadc mediatek,mt8173-auxadc           ~                         /           main                       Jokay          syscon@11003000       "    mediatek,mt8188-pericfg-ao syscon           ~     0                           O   ?      spi@1100a000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~                     -                         .   y   .      /           parent-clk sel-clk spi-clk          Jokay            Qdefault         _   N   ec@0              google,cros-ec-spi          ~               +              Qdefault         _   O         -   i2c-tunnel            google,cros-ec-i2c-tunnel                                   +       sbs-battery@f             sbs,sbs-battery         ~           *           >            cbas              google,cros-cbas          keyboard-controller           google,cros-ec-keyb         S           c            v     D     t x   	 q	 r  s  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	  + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      (                 	  	                 thermal-sensor@1100b000           mediatek,mt8188-lvts-ap         ~                     -                         /              /              P        lvts-calib-data-1                      O   '      pwm@1100e000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           ~                        .   '   /   /        main mm         -                                 Jokay            Qdefault         _   Q        O         pwm@1100f000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           ~                        .   (   /   F        main mm         -                              	  Jdisabled            Qdefault         _   R      spi@11010000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~                     -                         .   y   .      /   2        parent-clk sel-clk spi-clk          Jokay            Qdefault sleep           _   S        i   T      spi@11012000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~                     -                         .   y   .      /   3        parent-clk sel-clk spi-clk          Jokay            Qdefault         _   U      spi@11013000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~    0                -                         .   y   .      /   4        parent-clk sel-clk spi-clk        	  Jdisabled          spi@11018000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~                    -                         .   y   .      /   8        parent-clk sel-clk spi-clk        	  Jdisabled          spi@11019000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~                    -                         .   y   .      /   9        parent-clk sel-clk spi-clk        	  Jdisabled          usb@11201000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ~            -     >              	  mac ippc            O                     ?                      +           -                      $   .   )        4   .   v           ?   	   .      ?   
        sys_ck ref_ck mcu_ck               V      W                    	   X  h           Jokay            	host            	"   Y   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ~                       mac         -                      $   .   *        4   .   v           ?   
        sys_ck          Jokay            	"   Y        	0   Z         ethernet@11021000         ;    mediatek,mt8188-gmac mediatek,mt8195-gmac snps,dwmac-5.10a          ~           @         -                     	<macirq        0     ?       ?      .   A   .   B   .   C   ?         .  axi apb mac_main ptp_ref rmii_internal mac_cg           $   .   A   .   B   .   C        4   .      .      .              E           	L   /        	]   [        	m   \        	   ]        	           	           	          	  Jdisabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config           	                                 	           	           O   [      rx-queues-config            	            	        O   \   queue0           
        
          queue1           
        
          queue2           
        
          queue3           
        
             tx-queues-config            
2            
H        O   ]   queue0           
        
Z            
h         queue1           
        
Z           
h         queue2           
        
Z           
h         queue3           
        
Z           
h               mmc@11230000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ~    #                              -                          .      /      /      /   M      !  source hclk source_cg crypto_clk            Jokay            
t            
~         
        
 H        
          
         
         
         
         
         
        Qdefault state_uhs           _   ^        i   _                    `           a      mmc@11240000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ~    $                              -                         .      /      /   $        source hclk source_cg           $   .           4   .         	  Jdisabled          mmc@11250000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ~    %                              -                         .      /      /   A        source hclk source_cg           $   .           4   .         	  Jdisabled          thermal-sensor@11278000           mediatek,mt8188-lvts-mcu            ~    '                -                         /              /               P        lvts-calib-data-1                      O          i2c@11280000              mediatek,mt8188-i2c          ~    (             "                -                      *              b       /   7      	  main dma                         +            Jokay            Qdefault         _   c            audio-codec@1a            realtek,rt5682s         ~              +   l           Qdefault         _   d                   4   e        @   e        M   e        \   Y        j           O         amplifier@38              maxim,max98390          ~   8        yFront Right            +   v           Qdefault         _   f                    O         amplifier@39              maxim,max98390          ~   9        yFront Left                      O            i2c@11281000              mediatek,mt8188-i2c          ~    (            "               -                      *              b      /   7      	  main dma                         +            Jokay            Qdefault         _   g               i2c@11282000              mediatek,mt8188-i2c          ~    (             "               -                      *              b      /   7      	  main dma                         +            Jokay            Qdefault         _   h               clock-controller@11283000             mediatek,mt8188-imp-iic-wrap-c          ~    (0                           O   b      usb@112a1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ~    *       -    *>              	  mac ippc            O            *        ?                      +           -                     $   .   -        4   .   v           ?      .      ?           sys_ck ref_ck mcu_ck               i                    	   X  p           Jokay            	host            	"   Y   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ~                       mac         -                     $   .   .        4   .   v           ?           sys_ck          Jokay                      usb@112b1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ~    +       -    +>              	  mac ippc            O            +        ?                      +           -                     $   .   ,        4   .   v           ?      .      ?           sys_ck ref_ck mcu_ck               j                    	   X  `           Jokay            	host            	"   Y   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ~                       mac         -                     $   .   +        4   .   v           ?           sys_ck          Jokay            	0   k         pcie@112f0000         *    mediatek,mt8188-pcie mediatek,mt8192-pcie           ~    /                	  pcie-mac            O                                                 rpci                                  +         0     /   L   /   #   /   &   /   +   /   C   ?         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          p           -                   `                    l                      l                     l                     l                                         m                             n         	  pcie-phy               E              F           mac         Jokay            Qdefault         _   o   interrupt-controller                         p                    O   l         spi@1132c000          (    mediatek,mt8188-nor mediatek,mt8186-nor         ~    2                   .   X   ?      ?           spi sf axi          $   .   X        -      9                            +            Jokay            Qdefault         _   p   flash@0           jedec,spi-nor           ~            u          t-phy@11c20700        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3           O                                 +              E           Jokay       pcie-phy@0          ~                  .           ref                    O   n         dsi-phy@11c80000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         ~                        D        mipi_tx0_pll                                    Jokay              P        O         dsi-phy@11c90000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         ~                        D        mipi_tx0_pll                                  	  Jdisabled            O         i2c@11e00000              mediatek,mt8188-i2c          ~                 "                -                      *              q       /   7      	  main dma                         +            Jokay            Qdefault         _   r            tpm@50            google,cr50         ~   P           +               Qdefault         _   s         i2c@11e01000              mediatek,mt8188-i2c          ~                "               -                      *              q      /   7      	  main dma                         +            Jokay            Qdefault         _   t               clock-controller@11e02000             mediatek,mt8188-imp-iic-wrap-w          ~                                O   q      t-phy@11e30000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           O                     Jokay       usb-phy@0           ~                  .      -           ref da_ref                     O   j         t-phy@11e40000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           O                     Jokay       usb-phy@0           ~                  .      -           ref da_ref                     O   V      usb-phy@700         ~                 -      D        ref da_ref                     O   W         t-phy@11e80000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           O                     Jokay       usb-phy@0           ~                  .      -           ref da_ref                     O   i         i2c@11ec0000              mediatek,mt8188-i2c          ~                 "               -                      *              u       /   7      	  main dma                         +            Jokay            Qdefault         _   v               i2c@11ec1000              mediatek,mt8188-i2c          ~                "                -                      *              u      /   7      	  main dma                         +            Jokay            Qdefault         _   w               clock-controller@11ec2000              mediatek,mt8188-imp-iic-wrap-en         ~                                O   u      efuse@11f20000        ,    mediatek,mt8188-efuse mediatek,mt8186-efuse         ~                                  +      dp-calib@1a0            ~             O         lvts1-calib@1ac         ~     @        O   P      gpu-speedbin@581            ~             *               O   y      socinfo-data1@7a0           ~           socinfo-data2@7e0           ~              gpu@13000000          )    mediatek,mt8188-mali arm,mali-valhall-jm            ~             @            x          0  -                   ~             }               	<job mmu gpu            y      
  speed-bin           /   z           E      E      E           Ccore0 core1 core2           @           Jokay            V   ,        O   )      clock-controller@13fbf000             mediatek,mt8188-mfgcfg          ~                               O   x      syscon@14000000           mediatek,mt8188-vppsys0 syscon          ~                                 O   1      dma-controller@14001000           mediatek,mt8188-mdp3-rdma           ~                     b              1         <     {         {         {         {         {              m   |              E           t   }                                   ~      display@14002000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ~                         1            t   }                 display@14004000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ~     @                   1   "        t   }      @          display@14005000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ~     P                -      F                  1   
           E           t   }      P          display@14006000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ~     `                   1           t   }      `                %      display@14007000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ~     p                   1   #        t   }      p          display@14008000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ~                     -      I                  1   $           E           t   }                display@14009000          2    mediatek,mt8188-mdp3-ovl mediatek,mt8195-mdp3-ovl           ~                     -      J                  1   %           E           t   }                  m   |         display@1400a000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ~                        1              E           t   }                display@1400b000          2    mediatek,mt8188-mdp3-tcc mediatek,mt8195-mdp3-tcc           ~                        1           t   }                display@1400c000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ~                     b              1           m   |              E           t   }                      +      mutex@1400f000            mediatek,mt8188-vpp-mutex           ~                     -      P                  1              E           t   }                smi@14012000              mediatek,mt8188-smi-common-vpp          ~                        1      1           apb smi            E           O         smi@14013000              mediatek,mt8188-smi-larb            ~    0                   1      1           apb smi            E                                 O         iommu@14018000            mediatek,mt8188-iommu-vpp           ~           P            1           bclk            -      R                  E           K                                     O   |      dma-controller@14f09000           mediatek,mt8188-mdp3-rdma           ~                    b              3   
        m                 E           t   }   	                        dma-controller@14f0a000           mediatek,mt8188-mdp3-rdma           ~                    b              3           m   |              E           t   }   	                        display@14f0c000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ~                       3           t   }   	            display@14f0d000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ~                       3           t   }   	            display@14f0f000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ~                       3   "        t   }   	            display@14f10000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ~                        3   $        t   }   
             display@14f12000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ~                     -      j                  3   #           E           t   }   
             display@14f13000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ~    0                -      k                  3   %           E           t   }   
  0          display@14f15000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ~    P                   3           t   }   
  P                      display@14f16000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ~    `                   3           t   }   
  `                      display@14f18000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ~                       3           t   }   
            display@14f19000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ~                       3           t   }   
            display@14f1a000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           ~                       3              E           t   }   
            display@14f1b000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           ~                       3              E           t   }   
            display@14f1d000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ~                    -      u                  3              E           t   }   
            display@14f1e000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ~                    -      v                  3              E           t   }   
            display@14f21000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ~                       3              E           t   }               display@14f22000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ~                        3              E           t   }                display@14f24000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ~    @                b              3           m                 E           t   }     @                      display@14f25000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ~    P                b              3           m   |              E           t   }     P                      clock-controller@14e00000             mediatek,mt8188-wpesys          ~                                O   >      clock-controller@14e02000             mediatek,mt8188-wpesys-vpp0         ~                              smi@14e04000              mediatek,mt8188-smi-larb            ~    @                   >      >           apb smi            E                                 O         syscon@14f00000           mediatek,mt8188-vppsys1 syscon          ~                                O   3      mutex@14f01000            mediatek,mt8188-vpp-mutex           ~                    -      {                  3   &           E           t   }   	            smi@14f02000              mediatek,mt8188-smi-larb            ~                        3      3           apb smi            E                                 O         smi@14f03000              mediatek,mt8188-smi-larb            ~    0                   3      3           apb smi            E                                 O         clock-controller@15000000             mediatek,mt8188-imgsys          ~                               clock-controller@15110000              mediatek,mt8188-imgsys1-dip-top         ~                                         clock-controller@15130000             mediatek,mt8188-imgsys1-dip-nr          ~                                         clock-controller@15220000             mediatek,mt8188-imgsys-wpe1         ~    "                                     clock-controller@15330000             mediatek,mt8188-ipesys          ~    3                                     clock-controller@15520000             mediatek,mt8188-imgsys-wpe2         ~    R                                     clock-controller@15620000             mediatek,mt8188-imgsys-wpe3         ~    b                                     clock-controller@16000000             mediatek,mt8188-camsys          ~                                 O   7      clock-controller@1604f000             mediatek,mt8188-camsys-rawa         ~                                          O   :      clock-controller@1606f000             mediatek,mt8188-camsys-yuva         ~                                          O   ;      clock-controller@1608f000             mediatek,mt8188-camsys-rawb         ~                                          O   8      clock-controller@160af000             mediatek,mt8188-camsys-yuvb         ~    
                                      O   9      clock-controller@17200000             mediatek,mt8188-ccusys          ~                               video-decoder@18000000            mediatek,mt8188-vcodec-dec           ~                   @                O                    `         m   |                       +              ~   video-codec@10000             mediatek,mtk-vcodec-lat         ~                      $   .   4        4   .   x            .   4   4      4      .   x        sel vdec lat top            -                   H  m   |     |     |     |     |     |     |     |     |             E         video-codec@25000             mediatek,mtk-vcodec-core            ~     P                $   .   4        4   .   x            .   4   5      5      .   x        sel vdec lat top            -                   X  m                                                                  E            smi@1800d000              mediatek,mt8188-smi-larb            ~                        4       4            apb smi            E                                 O         clock-controller@1800f000             mediatek,mt8188-vdecsys-soc         ~                                O   4      smi@1802e000              mediatek,mt8188-smi-larb            ~                       5       5            apb smi            E                                 O         clock-controller@1802f000             mediatek,mt8188-vdecsys         ~                               O   5      clock-controller@1a000000             mediatek,mt8188-vencsys         ~                                 O   =      smi@1a010000              mediatek,mt8188-smi-larb            ~                        =      =           apb smi            E                                 O         video-encoder@1a020000            mediatek,mt8188-vcodec-enc          ~                                  +           $   .   3        4   .   p           =         	  venc_sel            -      a             X  m                                                                  E              ~      jpeg-encoder@1a030000         +    mediatek,mt8188-jpgenc mediatek,mtk-jpgenc          ~                        =           jpgenc          -      b                m                               E         jpeg-decoder@1a040000         .    mediatek,mt8188-jpgdec mediatek,mt2701-jpgdec           ~                        =       =           jpgdec-smi jpgdec           -      c             0  m                                         E         ovl@1c000000          2    mediatek,mt8188-disp-ovl mediatek,mt8195-disp-ovl           ~                         2            -      |               m                 E           t   {             ports                        +       port@0          ~       endpoint                       O            port@1          ~      endpoint                       O                  rdma@1c002000         4    mediatek,mt8188-disp-rdma mediatek,mt8195-disp-rdma         ~                         2           -      ~               m   |               E           t   {             ports                        +       port@0          ~       endpoint                       O            port@1          ~      endpoint                       O                  color@1c003000        6    mediatek,mt8188-disp-color mediatek,mt8173-disp-color           ~     0                   2           -                        E           t   {     0       ports                        +       port@0          ~       endpoint                       O            port@1          ~      endpoint                       O                  ccorr@1c004000        6    mediatek,mt8188-disp-ccorr mediatek,mt8192-disp-ccorr           ~     @                   2           -                        E           t   {     @       ports                        +       port@0          ~       endpoint                       O            port@1          ~      endpoint                       O                  aal@1c005000          2    mediatek,mt8188-disp-aal mediatek,mt8183-disp-aal           ~     P                   2           -                        E           t   {     P       ports                        +       port@0          ~       endpoint                       O            port@1          ~      endpoint                       O                  gamma@1c006000        6    mediatek,mt8188-disp-gamma mediatek,mt8195-disp-gamma           ~     `                   2           -                        E           t   {     `       ports                        +       port@0          ~       endpoint                       O            port@1          ~      endpoint                       O                  dither@1c007000       8    mediatek,mt8188-disp-dither mediatek,mt8183-disp-dither         ~     p                   2           -                        E           t   {     p       ports                        +       port@0          ~       endpoint                       O            port@1          ~      endpoint                       O                  dsi@1c008000              mediatek,mt8188-dsi         ~                        2      2              engine digital hs           -                                dphy               E              2           Jokay                         +       panel@0         ~               +               Qdefault         _                                                       '          Jokay              ivo,t109nw41 himax,hx83102     port       endpoint                       O               ports                        +       port@0          ~       endpoint                       O            port@1          ~      endpoint                       O                  dsc@1c009000          2    mediatek,mt8188-disp-dsc mediatek,mt8195-disp-dsc           ~                        2   
        -                        E           t   {               dsi@1c012000              mediatek,mt8188-dsi         ~                        2   	   2              engine digital hs           -                                dphy               E              2   	      	  Jdisabled          merge0@1c014000       6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~    @                   2      <           merge merge_async           -                        E           t   {     @          dp-intf@1c015000              mediatek,mt8188-dp-intf         ~    P                   2       2      -           pixel engine pll            -                        E         	  Jdisabled          mutex@1c016000            mediatek,mt8188-disp-mutex          ~    `                   2           -                        E           t   {     `              >      postmask@1c01a000         <    mediatek,mt8188-disp-postmask mediatek,mt8192-disp-postmask         ~                       2           -                        E           t   {            ports                        +       port@0          ~       endpoint                       O            port@1          ~      endpoint                       O                  syscon@1c01d000           mediatek,mt8188-vdosys0 syscon          ~                                             {               t   {                 O   2   port                         +       endpoint@0          ~                       O               smi@1c022000              mediatek,mt8188-smi-larb            ~                        2      2           apb smi            E                                  O         smi@1c023000              mediatek,mt8188-smi-larb            ~    0                   2      2           apb smi            E                                 O         smi@1c024000              mediatek,mt8188-smi-common-vdo          ~    @                   2      2           apb smi            E           O         iommu@1c028000            mediatek,mt8188-iommu-vdo           ~           P            2           bclk            -                        E           K                                  O         syscon@1c100000           mediatek,mt8188-vdosys1 syscon          ~                                              {              t   {                  O   <   port                         +       endpoint@1          ~                      O               mutex@1c101000            mediatek,mt8188-disp-mutex          ~                       <           -                        E           t   {                         smi@1c102000              mediatek,mt8188-smi-larb            ~                        <       <            apb smi            E                                 O         smi@1c103000              mediatek,mt8188-smi-larb            ~    0                   <      <           apb smi            E                                 O         rdma@1c104000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    @                   <           -                     m      @           E           b           t   {     @          rdma@1c105000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    P                   <           -                     m   |   `           E           b           t   {     P          rdma@1c106000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    `                   <           -                     m      A           E           b           t   {     `          rdma@1c107000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    p                   <           -                     m   |   a           E           b           t   {     p          rdma@1c108000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~                       <           -                     m      B           E           b           t   {               rdma@1c109000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~                       <           -                     m   |   b           E           b           t   {               rdma@1c10a000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~                       <           -                     m      C           E           b           t   {               rdma@1c10b000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~                       <           -                     m   |   c           E           b           t   {               merge@1c10c000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~                       <   	   <           merge merge_async           -                        E              <           t   {                  0      merge@1c10d000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~                       <   
   <           merge merge_async           -                        E              <           t   {                  0      merge@1c10e000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~                       <      <           merge merge_async           -                        E              <           t   {                  0      merge@1c10f000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~                       <      <           merge merge_async           -                        E              <           t   {                  0      merge@1c110000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~                        <      <           merge merge_async           -                        E              <           t   {                   D   ports                        +       port@0                       +            ~       endpoint@1          ~                      O            port@1                       +            ~      endpoint@1          ~                      O                  dp-intf@1c113000              mediatek,mt8188-dp-intf         ~    0                   <   :   <      -           pixel engine pll            -                        E           Jokay       ports                        +       port@0                       +            ~       endpoint@1          ~                      O            port@1                       +            ~      endpoint@1          ~                      O                  ethdr@1c114000        6    mediatek,mt8188-disp-ethdr mediatek,mt8195-disp-ethdr         p  ~    @            P            p                                                              4  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       h     <   0   <   +   <   .   <   ,   <   /   <   -   <   <   <   1   <   2   <   3   <   4   <   5   .           mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          -      6               m   |   d   |   e           E         (     <   1   <   2   <   3   <   4   <   5      p  t   {     @       {     P       {     p       {            {            {            {            ports                        +       port@0                       +            ~       endpoint@1          ~                      O            port@1                       +            ~      endpoint@1          ~                      O                  padding@1c11d000              mediatek,mt8188-disp-padding            ~                       <              E           t   {               padding@1c11e000              mediatek,mt8188-disp-padding            ~                       <               E           t   {               padding@1c11f000              mediatek,mt8188-disp-padding            ~                       <   !           E           t   {               padding@1c120000              mediatek,mt8188-disp-padding            ~                        <   "           E           t   {                padding@1c121000              mediatek,mt8188-disp-padding            ~                       <   #           E           t   {               padding@1c122000              mediatek,mt8188-disp-padding            ~                        <   $           E           t   {                padding@1c123000              mediatek,mt8188-disp-padding            ~    0                   <   %           E           t   {     0          padding@1c124000              mediatek,mt8188-disp-padding            ~    @                   <   &           E           t   {     @          edp-tx@1c500000           mediatek,mt8188-edp-tx          ~    P                 -                                dp_calibration_data            E           [        	  Jdisabled          dp-tx@1c600000            mediatek,mt8188-dp-tx           ~    `                 -                                dp_calibration_data            E           [          Jokay            Qdefault         _                       O      ports                        +       port@0          ~       endpoint                       O            port@1          ~      endpoint            l                               backlight-lcd0            pwm-backlight           w                @           +                                                     O         chosen          serial0:115200n8          dmic-codec            dmic-codec                        d      memory@40000000         rmemory          ~    @                 regulator-pp1800-ldo-z1           regulator-fixed         9pp1800_ldo_z1                             H w@        ` w@           k      regulator-pp3300-s3           regulator-fixed       
  9pp3300_s3                             H 2Z        ` 2Z           k        O   Y      regulator-pp3300-z1           regulator-fixed       
  9pp3300_z1                             H 2Z        ` 2Z                   O   k      regulator-pp3300-wlan             regulator-fixed         9pp3300_wlan                  H 2Z        ` 2Z                 $   +               _           Qdefault            k      regulator-pp4200-s5           regulator-fixed       
  9pp4200_s5                             H @@        ` @@                 regulator-pp5000-z1           regulator-fixed       
  9pp5000_z1                             H LK@        ` LK@                   O         regulator-pp5000-usb-vbus             regulator-fixed         9pp5000_usb_vbus         H LK@        ` LK@                 $   +                          O   Z      regulator-ppvar-sys           regulator-fixed       
  9ppvar_sys                             O         regulator-ppvar-mipi-disp-avdd            regulator-fixed         9ppvar_mipi_disp_avdd                     $   +               Qdefault         _                      O         regulator-ppvar-mipi-disp-avee            regulator-fixed         9ppvar_mipi_disp_avee            x  '                 $   +               Qdefault         _                      O         reserved-memory                      +            O   memory@50000000           shared-dma-pool         ~    P                   )        O   C      memory@55000000           shared-dma-pool         ~    U       @        memory@60000000           shared-dma-pool         ~    `                   )        O   K      memory@60f00000           shared-dma-pool         ~    `                  )        O   G      memory@61000000           shared-dma-pool         ~    a                   )        O   J            	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dsc0 ethdr0 gce0 gce1 merge0 merge1 merge2 merge3 merge4 merge5 mutex0 mutex1 padding0 padding1 padding2 padding3 padding4 padding5 padding6 padding7 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 dsi0 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 mmc0 serial0 device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-output-names opp-shared opp-hz opp-microvolt opp-supported-hw interrupts mediatek,platform status pinctrl-names pinctrl-0 pinctrl-1 pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 mediatek,adsp audio-routing link-name dai-format mediatek,clk-provider sound-dai polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux bias-pull-down input-enable drive-strength output-high bias-disable output-low bias-pull-up #power-domain-cells domain-supply clocks clock-names mediatek,infracfg mediatek,disable-extrst #sound-dai-cells interrupts-extended #io-channel-cells mediatek,dmic-mode mediatek,mic-type-0 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread regulator-microvolt-offset assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells firmware-name memory-region power-domains resets reset-names mediatek,topckgen mediatek,etdm-out1-cowork-source mediatek,etdm-in2-cowork-source mboxes mbox-names spi-max-frequency google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells phys wakeup-source mediatek,syscon-wakeup dr_mode vusb33-supply vbus-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,blen snps,rd_osr_lmt snps,wr_osr_lmt snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,priority snps,weight bus-width cap-mmc-highspeed cap-mmc-hw-reset hs400-ds-delay mmc-hs200-1_8v mmc-hs400-1_8v mmc-hs400-enhanced-strobe no-sd no-sdio non-removable supports-cqe vmmc-supply vqmmc-supply clock-div AVDD-supply DBVDD-supply LDO1-IN-supply MICVDD-supply realtek,jd-src sound-name-prefix reset-gpios usb2-lpm-disable bus-range linux,pci-domain interrupt-map interrupt-map-mask iommu-map iommu-map-mask phy-names #phy-cells drive-strength-microamp bits operating-points-v2 power-domain-names mali-supply #dma-cells iommus mediatek,gce-client-reg mediatek,gce-events mediatek,scp mediatek,larb-id mediatek,smi mediatek,larbs remote-endpoint enable-gpios backlight avdd-supply avee-supply pp1800-supply rotation mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz data-lanes brightness-levels default-brightness-level num-interpolated-steps power-supply pwms stdout-path num-channels wakeup-delay-ms regulator-boot-on vin-supply enable-active-high gpio no-map 