    8     (              H                                 google,tentacruel-sku262147 google,tentacruel-sku262146 google,tentacruel-sku262145 google,tentacruel-sku262144 google,tentacruel mediatek,mt8186                                    +            7Google Tentacruel board          =convertible    aliases          J/soc/ovl@14005000            O/soc/ovl@14006000            W/soc/rdma@14007000           ]/soc/rdma@1401f000           c/soc/i2c@11007000            h/soc/i2c@11008000            m/soc/i2c@11009000            r/soc/i2c@1100f000            w/soc/i2c@11016000            |/soc/mmc@11230000            /soc/mmc@11240000            /soc/serial@11002000             /soc/i2c@11011000         fhctl@1000ce00            mediatek,mt8186-fhctl                                              	   disabled          cci           mediatek,mt8186-cci                               cci intermediate                                        "      opp-table-cci             operating-points-v2                          opp-500000000                e           	'                  opp-560000000                !`           
L                  opp-612000000                $za           
                  opp-682000000                (~          
            	      opp-752000000                ,Ҝ           YF            
      opp-822000000                0                            opp-875000000                4'p                            opp-927000000                7@          5                   opp-980000000                :i           ~>                  opp-1050000000               >                            opp-1120000000               B           )$                  opp-1155000000               D                            opp-1190000000               F          
                  opp-1260000000               K           ~                  opp-1330000000               OF0          )                  opp-1400000000               SrN           R                     opp-table-cluster0            operating-points-v2                          opp-500000000                e           	'                  opp-774000000                ."M          
L                  opp-875000000                4'p          
`                  opp-975000000                :Q                      	      opp-1075000000               @2          q            
      opp-1175000000               F	          X                  opp-1275000000               K          5                   opp-1375000000               Q                            opp-1500000000               Yh/                             opp-1618000000               `p          Y                  opp-1666000000               cM$                            opp-1733000000               gK{@          H                  opp-1800000000               kI           ~                  opp-1866000000               o8                            opp-1933000000               s7=@          Z                  opp-2000000000               w5           R                     opp-table-cluster1            operating-points-v2                       #   opp-774000000                ."M          
L                  opp-835000000                1          
                  opp-919000000                6          
                  opp-1002000000               ;N          YF            	      opp-1085000000               @@          X            
      opp-1169000000               E@          5                   opp-1308000000               M                             opp-1419000000               T8          Y                  opp-1530000000               [1          t                  opp-1670000000               c-          Z                  opp-1733000000               gK{@                            opp-1796000000               k           s                  opp-1860000000               nY           Լ                  opp-1923000000               r          6d                  opp-1986000000               v_          v                  opp-2050000000               z0                               cpus                         +       cpu-map    cluster0       core0                    core1                    core2                    core3                    core4                    core5                    core6                    core7                          cpu@0           cpu           arm,cortex-a55                       psci            %w5                                cpu intermediate                        5   T        O  ~        b               r              @                                 @                      !                      "                              cpu@100         cpu           arm,cortex-a55                      psci            %w5                                cpu intermediate                        5   T        O  ~        b               r              @                                 @                      !                      "                              cpu@200         cpu           arm,cortex-a55                      psci            %w5                                cpu intermediate                        5   T        O  ~        b               r              @                                 @                      !                      "                              cpu@300         cpu           arm,cortex-a55                      psci            %w5                                cpu intermediate                        5   T        O  ~        b               r              @                                 @                      !                      "                              cpu@400         cpu           arm,cortex-a55                      psci            %w5                                cpu intermediate                        5   T        O  ~        b               r              @                                 @                      !                      "                              cpu@500         cpu           arm,cortex-a55                      psci            %w5                                cpu intermediate                        5   T        O  ~        b               r              @                                 @                      !                      "                              cpu@600         cpu           arm,cortex-a76                      psci            %z0                              cpu intermediate                #        5  O        O           b   $   %        r              @                                 @                      &                      "            '                  cpu@700         cpu           arm,cortex-a76                      psci            %z0                              cpu intermediate                #        5  O        O           b   $   %        r              @                                 @                      &                      "            '                  idle-states         psci       cpu-retention-l           arm,idle-state                             ,   2        =   d        M  @                  cpu-retention-b           arm,idle-state                             ,   2        =   d        M  x            $      cpu-off-l             arm,idle-state                            ,   d        =           M  4                   cpu-off-b             arm,idle-state                            ,   d        =           M  l            %         l2-cache0             cache           ^           t              @                      (         j            !      l2-cache1             cache           ^           t              @                      (         j            &      l3-cache              cache           ^           t              @                    j            (         fixed-factor-clock-13m            fixed-factor-clock          x                )                              clk13m              =      oscillator-26m            fixed-clock         x            %        clk26m              )      oscillator-32k            fixed-clock         x            %           clk32k        opp-table-gpu             operating-points-v2             y   opp-299000000                `          	X                 opp-332000000                           	h                 opp-366000000                з          	<                 opp-400000000                ׄ           	Ҧ                 opp-434000000                P          
z                 opp-484000000                A           
4N                 opp-535000000                s          
}                 opp-586000000                "          
`                 opp-637000000                %@          
4                 opp-690000000                )           @                 opp-743000000                ,IG                           opp-796000000                /q                            opp-850000000                2          5                  opp-900000000-3              5           P                 opp-900000000-4              5           |                 opp-900000000-5              5                             opp-950000000-3              8ـ                           opp-950000000-4              8ـ          Y                 opp-950000000-5              8ـ          P                  opp-1000000000-3                 ;           ~                 opp-1000000000-4                 ;           t                 opp-1000000000-5                 ;           Y                     pmu-a55           arm,cortex-a55-pmu                                  *      pmu-a76           arm,cortex-a76-pmu                                  +      psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @                                               
             soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3                                                                                                 	                               ppi-partitions     interrupt-partition-0           1                              *      interrupt-partition-1           1                  +            syscon@c53a000            mediatek,mt8186-mcusys syscon                S                x                     syscon@10000000            mediatek,mt8186-topckgen syscon                                x               -      syscon@10001000       #    mediatek,mt8186-infracfg_ao syscon                                x           :               /      syscon@10003000           mediatek,mt8186-pericfg syscon                0                    k      pinctrl@10005000              mediatek,mt8186-pinctrl               P                           "             $             &             *             ,                           B  Giocfg0 iocfg_lt iocfg_lm iocfg_lb iocfg_bl iocfg_rb iocfg_rt eint            Q        a           m   ,                                                          	  yTP TP TP I2S0_HP_DI I2S3_DP_SPKR_DO SAR_INT_ODL BT_WAKE_AP_ODL WIFI_INT_ODL DPBRDG_INT_ODL EDPBRDG_INT_ODL EC_AP_HPD_OD TCHPAD_INT_ODL TCHSCR_INT_1V8_ODL EC_AP_INT_ODL EC_IN_RW_ODL GSC_AP_INT_ODL AP_FLASH_WP_L HP_INT_ODL PEN_EJECT_OD WCAM_PWDN_L WCAM_RST_L UCAM_SEN_EN UCAM_RST_L LTE_RESET_L LTE_SAR_DETECT_L I2S2_DP_SPK_MCK I2S2_DP_SPKR_BCK I2S2_DP_SPKR_LRCK I2S2_DP_SPKR_DI (TP) EN_PP1000_EDPBRDG EN_PP1800_EDPBRDG EN_PP3300_EDPBRDG UART_GSC_TX_AP_RX UART_AP_TX_GSC_RX UART_DBGCON_TX_ADSP_RX UART_ADSP_TX_DBGCON_RX EN_PP1000_DPBRDG TCHSCR_REPORT_DISABLE EN_PP3300_DPBRDG EN_PP1800_DPBRDG SPI_AP_CLK_EC SPI_AP_CS_EC_L SPI_AP_DO_EC_DI SPI_AP_DI_EC_DO SPI_AP_CLK_GSC SPI_AP_CS_GSC_L SPI_AP_DO_GSC_DI SPI_AP_DI_GSC_DO UART_DBGCON_TX_SCP_RX UART_SCP_TX_DBGCON_RX EN_PP1200_CAM_X EN_PP2800A_VCM_X EN_PP2800A_UCAM_X EN_PP2800A_WCAM_X WLAN_MODULE_RST_L EN_PP1200_UCAM_X I2S1_HP_DO I2S1_HP_BCK I2S1_HP_LRCK I2S1_HP_MCK TCHSCR_RST_1V8_L SPI_AP_CLK_ROM SPI_AP_CS_ROM_L SPI_AP_DO_ROM_DI SPI_AP_DI_ROM_DO NC NC EMMC_STRB EMMC_CLK EMMC_CMD EMMC_RST_L EMMC_DATA0 EMMC_DATA1 EMMC_DATA2 EMMC_DATA3 EMMC_DATA4 EMMC_DATA5 EMMC_DATA6 EMMC_DATA7 AP_KPCOL0 NC NC NC TP SDIO_CLK SDIO_CMD SDIO_DATA0 SDIO_DATA1 SDIO_DATA2 SDIO_DATA3 NC NC NC NC NC NC EDPBRDG_PWREN BL_PWM_1V8 EDPBRDG_RST_L MIPI_DPI_CLK MIPI_DPI_VSYNC MIPI_DPI_HSYNC MIPI_DPI_DE MIPI_DPI_D0 MIPI_DPI_D1 MIPI_DPI_D2 MIPI_DPI_D3 MIPI_DPI_D4 MIPI_DPI_D5 MIPI_DPI_D6 MIPI_DPI_DA7 MIPI_DPI_D8 MIPI_DPI_D9 MIPI_DPI_D10 MIPI_DPI_D11 PCM_BT_CLK PCM_BT_SYNC PCM_BT_DI PCM_BT_DO JTAG_TMS_TP JTAG_TCK_TP JTAG_TDI_TP JTAG_TDO_TP JTAG_TRSTN_TP CLK_24M_WCAM CLK_24M_UCAM UCAM_DET_ODL AP_I2C_EDPBRDG_SCL_1V8 AP_I2C_EDPBRDG_SDA_1V8 AP_I2C_TCHSCR_SCL_1V8 AP_I2C_TCHSCR_SDA_1V8 AP_I2C_TCHPAD_SCL_1V8 AP_I2C_TCHPAD_SDA_1V8 AP_I2C_DPBRDG_SCL_1V8 AP_I2C_DPBRDG_SDA_1V8 AP_I2C_WLAN_SCL_1V8 AP_I2C_WLAN_SDA_1V8 AP_I2C_AUD_SCL_1V8 AP_I2C_AUD_SDA_1V8 AP_I2C_TPM_SCL_1V8 AP_I2C_UCAM_SDA_1V8 AP_I2C_UCAM_SCL_1V8 AP_I2C_UCAM_SDA_1V8 AP_I2C_WCAM_SCL_1V8 AP_I2C_WCAM_SDA_1V8 SCP_I2C_SENSOR_SCL_1V8 SCP_I2C_SENSOR_SDA_1V8 AP_EC_WARM_RST_REQ AP_XHCI_INIT_DONE USB3_HUB_RST_L EN_SPKR BEEP_ON AP_EDP_BKLTEN EN_PP3300_DISP_X EN_PP3300_SDBRDG_X BT_KILL_1V8_L WIFI_KILL_1V8_L PWRAP_SPI0_CSN PWRAP_SPI0_CK PWRAP_SPI0_MO PWRAP_SPI0_MI SRCLKENA0 SRCLKENA1 SCP_VREQ_VAO AP_RTC_CLK32K AP_PMIC_WDTRST_L AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_CLK_MISO AUD_SYNC_MISO AUD_DAT_MISO0 AUD_DAT_MISO1 NC NC DPBRDG_PWREN DPBRDG_RST_L LTE_W_DISABLE_L LTE_SAR_DETECT_L EN_PP3300_LTE_X LTE_PWR_OFF_L LTE_RESET_L TP TP              ,   aud-clk-mosi-off-pins                  pins-clk-sync                                            aud-clk-mosi-on-pins                   pins-clk-sync                        aud-clk-miso-off-pins                  pins-clk-sync                                            aud-clk-miso-on-pins                   pins-clk-sync                        aud-dat-mosi-off-pins                  pins-dat                                             aud-dat-mosi-on-pins                   pins-dat                         aud-dat-miso-off-pins                  pins-dat                                             aud-dat-miso-on-pins                   pins-dat                                           aud-gpio-i2s0-off-pins                 pins-sdata                      aud-gpio-i2s0-on-pins                  pins-sdata                     aud-gpio-i2s-off-pins                  pins-clk-sdata            8   9   :   ;                   aud-gpio-i2s1-on-pins                  pins-clk-sdata            8  9  :  ;         aud-gpio-i2s2-off-pins                 pins-cmd-dat                                    aud-gpio-i2s2-on-pins                  pins-clk                                    aud-gpio-i2s3-off-pins                 pins-sdata                               aud-gpio-i2s3-on-pins                  pins-sdata                                aud-gpio-pcm-off-pins                  pins-clk-sdata            s   t   u   v                   aud-gpio-pcm-on-pins                   pins-clk-sdata            s  t  u  v         aud-gpio-dmic-sec-pins                 pins                                 bt-reset-pins               s   pins-bt-reset                                dpi-sleep-pins              ~   pins-cmd-dat          @    g   h   i   j   k   l   m   n   o   p   q   r   e   d   f   c            
                  dpi-default-pins                }   pins-cmd-dat          @    g  h  i  j  k  l  m  n  o  p  q  r  e  d  f  c           
         cros-ec-int-pins                e   pins-ec-ap-int-odl                               edp-panel-fixed-pins                   pins-vreg-en                                 en-pp1800-dpbrdg-pins                  pins-vreg-en              '                   gsc-int-pins                g   pins-gsc-ap-int-odl                              i2c0-pins               G   pins-bus                                                      i2c1-pins               P   pins-bus                                                      i2c2-pins               S   pins-bus                                                      i2c3-pins               U   pins-bus                                                      i2c5-pins               ^   pins-bus                                                      it6505-pins             V   pins-hpd              
                         pins-int                                       pins-reset                                        mmc0-default-pins               l   pins-clk              D           f      pins-cmd-dat          $    G  H  I  J  K  L  M  N  E                    e      pins-rst              F           e         mmc0-uhs-pins               m   pins-clk              D                      f      pins-cmd-dat          $    G  H  I  J  K  L  M  N  E                               e      pins-ds           C                      f      pins-rst              F           e         mmc1-default-pins               o   pins-clk              T                      f      pins-cmd-dat              V  W  X  Y  U                               e         mmc1-uhs-pins               p   pins-clk              T                      f      pins-cmd-dat              V  W  X  Y  U                               e         mmc1-eint-pins              q   pins-dat1             W                     e         nor-default-pins                E   pins-clk-dat              ?  =  @                          pins-cs-dat           >  A  B                             pen-eject-pins                 pins                                          disp-pwm-pins               c   pins              a                  speaker-codec-default-pins                 pins-sdb                                 scp-default-pins                >   pins-scp-uart             0  1         spi1-pins               d   pins-bus              (  )  *  +                           spi2-pins               f   pins-bus              ,  -   .  /                           spmi-pins      pins-bus                         touchscreen-pins                Q   pins-irq                                       pins-reset            <                pins-report-sw            %                   trackpad-default-pins               T   pins-int-n                                        wifi-enable-pins                   pins-wifi-enable              6          wifi-wakeup-pins                   pins-wifi-wakeup                                 i2c4-pins               [   pins-bus                                                      ps8640-pins             H   pins-pwrdn-rst            `   b                   sar-sensor-pins             \   pins-irq                                             syscon@10006000       )    mediatek,mt8186-scpsys syscon simple-mfd                  `           power-controller          !    mediatek,mt8186-power-controller                         +                           B   power-domain@0                           -            mfg00                        +                          .   power-domain@1                      #   /                     +                          0   power-domain@2                                power-domain@3                                      power-domain@17                         -      -         $   subsys-csirx-top0 subsys-csirx-top1                   power-domain@4                          -      /   =         sys_ck ref_ck                     power-domain@5                          /   B   /   ?         sys_ck ref_ck                     power-domain@18                         -   /   -   >         audioadsp subsys-adsp-bus                        +                  power-domain@19                                  +                  power-domain@20                     #   /                        power-domain@16                     #   /                  power-domain@6                    0      -   *   -   +   1   
   1      1      1         M   disp mdp subsys-smi-infra subsys-smi-common subsys-smi-gals subsys-smi-iommu            #   /                     +                  power-domain@14                         -   )   2             vdec0 larb          #   /                  power-domain@10             
      8      -      -      -      -       3      -   #   -   %      6   cam0 cam1 cam2 cam3 gals subsys-cam-tm subsys-cam-top           #   /                     +                  power-domain@12                               power-domain@11                                  power-domain@7                          4      -   &         gals subsys-img-top         #   /                     +                  power-domain@8                                   power-domain@9              	      (      -   '   5       5      5      5         P   subsys-ipe-top subsys-ipe-larb0 subsys-ipe-larb1 subsys-ipe-smi subsys-ipe-gals         #   /                  power-domain@13                         -   $   6            venc0 subsys-larb           #   /                  power-domain@15                         -   :   7      7         %   wpe0 subsys-larb-ck subsys-larb-pclk            #   /                           watchdog@10007000             mediatek,mt8186-wdt          5              p                :            M            h      syscon@1000c000       "    mediatek,mt8186-apmixedsys syscon                                 x                     pwrap@1000d000            mediatek,mt8186-pwrap syscon                                  Gpwrap                                     /      /          	   spi wrap       pmic               mediatek,mt6366 mediatek,mt6358                  f   ,                    audio-codec       ,    mediatek,mt6366-sound mediatek,mt6358-sound         z   8                 regulators        4    mediatek,mt6366-regulator mediatek,mt6358-regulator            9           9           9           9           9           9           9           9        %   9        9   9        M   9        ]   9        m   :        }   ;           <           <   vcore           pp0750_dvdd_core             dp         5           j                                   5      vdram1          pp1125_emi_vdd2          *         *          0                                    5            ;      vgpu            ppvar_dvdd_vgpu                    ~          j                                  I   .        `             0      vproc11         ppvar_dvdd_proc_bc_mt6366            	'         O          j                                   5            '      vproc12         ppvar_dvdd_proc_lc           	'         O          j                                   5                  vs1         pp2000_vs1                              0                     5            :      vs2         pp1350_vs2           p         p          0                     5            <      va12            pp1200_va12          O         O                   5      vaud28          pp2800_vaud28            *         *                      8      vaux18          pp1840_vaux18            w@                         vbif28          pp2800_vbif28            *         *                vcn18           pp1800_vcn18_x           w@         w@                vcn28           pp2800_vcn28_x           *         *                vefuse          pp1800_vefuse            w@         w@                vfe28           pp2800_vfe28_x           *         *                vemc            pp3000_vemc          -         -           <            n      vibr            pp2800_vibr_x            *         *           <      vio18           pp1800_vio18_s3          w@         w@          
         5            ]      vio28           pp2800_vio28_x           *         *                vm18            pp1800_emi_vdd1          w@                   E         5      vmc         pp3000_vmc           -         -           <      vmddr           pm0750_emi_vmddr             
`         q          E         5      vmch            pp3000_vmch          -         -           <      vcn33           pp3300_vcn33_x           2Z         2Z                      J      vdram2          pp0600_emi_vddq          	'         	'                   5      vrf12           pp1200_vrf12_x           O         O           x            I      vrf18           pp1800_vrf18_x           w@         w@           x      vsim1           pp1860_vsim1_x           w@         a                vsim2           pp2760_vsim2_x           )2         *@                      W      vsram-gpu           pp0900_dvdd_sram_gpu             P                   j                   I   0        `             .      vsram-others            pp0900_dvdd_sram_core                               j                    5      vsram-proc11            pp0900_dvdd_sram_bc          P                    j                    5      vsram-proc12            pp0900_dvdd_sram_lc          P                    j                    5      vusb            pp3070_vusb          -         .0                   5      vxo22           pp2240_vxo22             !         ".            x         5         rtc       (    mediatek,mt6366-rtc mediatek,mt6358-rtc             spmi@10015000         *    mediatek,mt8186-spmi mediatek,mt8195-spmi                 P                            Gpmif spmimst                /      /       -   2      (   pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         }   -   2           -   t                                           	   disabled          timer@10017000        ,    mediatek,mt8186-timer mediatek,mt6765-timer              p                                          =      mailbox@1022c000              mediatek,mt8186-gce              "       @             /            gce                                              z      scp@10500000              mediatek,mt8186-scp               P             \             	  Gsram cfg                                  default            >        mediatek/mt8186/scp.img            ?         okay                   cros-ec-rpmsg             google,cros-ec-rpmsg            cros-ec-rpmsg            adsp@10680000             mediatek,mt8186-dsp       @       h                           h            h                Gcfg sram sec bus                -   /   -   >         audiodsp adsp_bus           }   -   /   -   >           )   -   E        rx tx              @   A        
   B            okay               C   D                  mailbox@10686100              mediatek,mt8186-adsp-mbox                            ha                      i                   @      mailbox@10687100              mediatek,mt8186-adsp-mbox                            hq                      j                   A      spi@11000000              mediatek,mt8186-nor                                     -   3   /   O   /   c   /   d         spi sf axi axi_s            }   -   3           -   P              %                okay            default            E                     +       flash@0           jedec,spi-nor                        S         adc@11001000          .    mediatek,mt8186-auxadc mediatek,mt8173-auxadc                                 *               /   "         main          serial@11002000       *    mediatek,mt8186-uart mediatek,mt6577-uart                                         p                   )   /         	   baud bus             okay          serial@11003000       *    mediatek,mt8186-uart mediatek,mt6577-uart                 0                       q                   )   /         	   baud bus          	   disabled          i2c@11007000              mediatek,mt8186-i2c                p                                    i                   F       /   '      	   main dma                                    +             okay            default            G        %    edp-bridge@8              parade,ps8640                       default            H        <   ,   `           L   ,   b           X   I        e   J   ports                        +       port@0                  endpoint            r   K                     port@1                 endpoint            r   L            O            aux-bus    panel         
    edp-panel              M           N   port       endpoint            r   O            L                     i2c@11008000              mediatek,mt8186-i2c                                                    j                   F      /   '      	   main dma                                    +             okay            default            P        %           '   touchscreen@10            elan,ekth6a12nay                        f   ,              default            Q        L   ,   <              R                  i2c@11009000              mediatek,mt8186-i2c                                                   k                   F      /   '      	   main dma                                    +             okay            default            S        %           '   trackpad@15           elan,ekth3000                       f   ,              default            T           R                  i2c@1100f000              mediatek,mt8186-i2c                                                   l                   F      /   '      	   main dma                                    +             okay            default            U        %    dp-bridge@5c              ite,it6505              \        f   ,              default            V                        W           X        L   ,                 Y               ports                        +       port@0                  endpoint                 р        r   Z                     port@1                             i2c@11011000              mediatek,mt8186-i2c                                                 m                   F      /   '      	   main dma                                    +             okay            default            [        %    proximity@28              semtech,sx9324              (        *           f   ,              default            \        {   ]        1   ]         i2c@11016000              mediatek,mt8186-i2c               `                                   b                   F      /   '      	   main dma                                    +             okay            default            ^   codec@1a              realtek,rt5682s                     f   ,                         =   ]        I   ]        V   ]        e   _        s                        i2c@1100d000              mediatek,mt8186-i2c                                                   c                   F      /   '      	   main dma                                    +          	   disabled          i2c@11004000              mediatek,mt8186-i2c                @             	                      n                   F      /   '      	   main dma                                    +          	   disabled          i2c@11005000              mediatek,mt8186-i2c                P             
                     o                   F      /   '      	   main dma                                    +          	   disabled          spi@1100a000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +                                                            -   K   -      /            parent-clk sel-clk spi-clk        	   disabled          thermal-sensor@1100b000           mediatek,mt8186-lvts                                         c                   /   	           /               `   a      $  lvts-calib-data-1 lvts-calib-data-2                              svs@1100bc00              mediatek,mt8186-svs                                                         /   	         main               b   `      (  svs-calibration-data t-calibration-data            /           svs_rst       pwm@1100e000          2    mediatek,mt8186-disp-pwm mediatek,mt8183-disp-pwm                                                                      -      /   4         main mm          okay            default            c                  spi@11010000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +                                                            -   K   -      /   8         parent-clk sel-clk spi-clk           okay            default            d               ec@0              google,cros-ec-spi                       f   ,              default            e         B@   i2c-tunnel            google,cros-ec-i2c-tunnel                                   +       sbs-battery@b             sbs,sbs-battery                                	            typec             google,cros-ec-typec                         +       connector@0           usb-c-connector                      	"left            	(dual            	3host            	=source        connector@1           usb-c-connector                     	"right           	(dual            	3host            	=source           extcon0           google,extcon-usbc-cros-ec          	L                Y      keyboard-controller           google,cros-ec-keyb         	_           	o            	     D  	   t x c  	 q	 r  s  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	  + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      (  	               	  	                 spi@11012000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +                                                            -   K   -      /   ;         parent-clk sel-clk spi-clk           okay            default            f        	   ,   -                  tpm@0             google,cr50                      f   ,              default            g         B@         spi@11013000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +                 0                                          -   K   -      /   <         parent-clk sel-clk spi-clk        	   disabled          spi@11014000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +                 @                       t                   -   K   -      /   J         parent-clk sel-clk spi-clk        	   disabled          spi@11015000          (    mediatek,mt8186-spi mediatek,mt6765-spi                      +                 P                       u                   -   K   -      /   K         parent-clk sel-clk spi-clk        	   disabled          clock-controller@11017000             mediatek,mt8186-imp_iic_wrap                 p                x               F      serial@11018000       *    mediatek,mt8186-uart mediatek,mt6577-uart                                                          )   /         	   baud bus          	   disabled          i2c@11019000              mediatek,mt8186-i2c                                                 d                   F   	   /   '      	   main dma                                    +          	   disabled          audio-controller@11210000             mediatek,mt8186-sound                !                      /   ,   /   6   -      -      -   F   -            -            -      -   e   -      -   h   -   ?   -   @   -   A   -   B   -   C   -      -      -      -      -      -   ,   )     }   aud_infra_clk mtkaif_26m_clk top_mux_audio top_mux_audio_int top_mainpll_d2_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d8 top_mux_aud_eng2 top_apll2_d8 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s4_m_sel top_tdm_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div4 top_apll12_div_tdm top_mux_audio_h top_clk26m_clk                                  	           #   /        	   -           h         	  audiosys             okay               i                  usb@11201000          #    mediatek,mt8186-mtu3 mediatek,mtu3                        -     >              	  Gmac ippc          (      -      /   =   /   3   /      /   >      $   sys_ck ref_ck mcu_ck dma_ck xhci_ck               /               	   j           
   B                        +                             	   k               okay       usb@11200000          '    mediatek,mt8186-xhci mediatek,mtk-xhci                                 Gmac       (      -      /   =   /   3   /      /   >      $   sys_ck ref_ck mcu_ck dma_ck xhci_ck               &                okay            
	   R         mmc@11230000          (    mediatek,mt8186-mmc mediatek,mt8183-mmc               #                                   -      /      /   U   /            source hclk source_cg crypto                   d               }   -                          okay            default state_uhs              l        
   m        
                     
)         
7         
I         
X         
g         
t         
z         
        
         
           
   n        
   ]      mmc@11240000          (    mediatek,mt8186-mmc mediatek,mt8183-mmc               $                                  -      /      /   V         source hclk source_cg           }   -              -   o         okay            default state_uhs state_eint               o        
   p        
   q        
msdc sdio_wakeup             f          e          ,   W                        +            
                     
         
                                    .         ;         
t        
   R        
   ]        B   r   bluetooth@2           mediatek,mt7921s-bluetooth                      default            s        L   ,               usb@11281000          #    mediatek,mt8186-mtu3 mediatek,mtu3                (       -    (>              	  Gmac ippc          $      /   B   /   ?   /   7   )   /   @      $   sys_ck ref_ck mcu_ck dma_ck xhci_ck               K               	   t      u           
   B                        +                             	   k  $            okay       usb@11280000          '    mediatek,mt8186-xhci mediatek,mtk-xhci               (                 Gmac       $      /   B   /   ?   /   7   )   /   @      $   sys_ck ref_ck mcu_ck dma_ck xhci_ck               D                okay            
	   v         t-phy@11c80000        .    mediatek,mt8186-tphy mediatek,generic-tphy-v2                        +                                 okay       usb-phy@0                               )         ref         M               t      usb-phy@700               	             )         ref         M               u         t-phy@11ca0000        .    mediatek,mt8186-tphy mediatek,generic-tphy-v2                        +                                 okay       usb-phy@0                               )         ref         M           X               j         efuse@11cb0000        %    mediatek,mt8186-efuse mediatek,efuse                                               +      lvts1-calib@1cc                           `      lvts2-calib@2f8                           a      calib@550              P   P            b      gpu-speedbin@59c                          h                   x      socinfo-data1@7a0                          dsi-phy@11cc0000              mediatek,mt8183-mipi-tx                                   )        x            M            mipi_tx0_pll             okay                      clock-controller@13000000             mediatek,mt8186-mfgsys                                 x               w      gpu@13040000          &    mediatek,mt8186-mali arm,mali-bifrost                        @             w          0                                                 
job mmu gpu         
   B      B           mcore0 core1                       x      
  speed-bin               y        5  O         okay               0                  syscon@14000000           mediatek,mt8186-mmsys syscon                                   x           :              z          z                 z                      1      mutex@14001000            mediatek,mt8186-disp-mutex                                    1                  '                  z                             
   B         smi@14002000              mediatek,mt8186-smi-common                                      1      1      1      1            apb smi gals0 gals1         
   B               {      smi@14003000              mediatek,mt8186-smi-larb                  0                    1      1            apb smi                        {        
   B                     smi@14004000              mediatek,mt8186-smi-larb                  @                    1      1            apb smi                       {        
   B                     ovl@14005000          2    mediatek,mt8186-disp-ovl mediatek,mt8192-disp-ovl                 P                    1                 )                  |              z     P            
   B         ovl@14006000          8    mediatek,mt8186-disp-ovl-2l mediatek,mt8192-disp-ovl-2l               `                    1                 *                  |   !           z     `            
   B         rdma@14007000         4    mediatek,mt8186-disp-rdma mediatek,mt8183-disp-rdma               p                    1                 +                  |   "           z     p            
   B         color@14009000        6    mediatek,mt8186-disp-color mediatek,mt8173-disp-color                                     1   	              -                  z                 
   B         dpi@1400a000              mediatek,mt8186-dpi                                   -   ;   1                  pixel engine pll            }   -   ;           -   j              5               
   B         	   disabled            default sleep              }        
   ~   port       endpoint            r               Z            ccorr@1400b000        6    mediatek,mt8186-disp-ccorr mediatek,mt8192-disp-ccorr                                     1                 .                  z                 
   B         aal@1400c000          2    mediatek,mt8186-disp-aal mediatek,mt8183-disp-aal                                     1                 0                  z                 
   B         gamma@1400d000        6    mediatek,mt8186-disp-gamma mediatek,mt8183-disp-gamma                                     1                 1                  z                 
   B         postmask@1400e000         <    mediatek,mt8186-disp-postmask mediatek,mt8192-disp-postmask                                   1                 2                  z                 
   B         dither@1400f000       8    mediatek,mt8186-disp-dither mediatek,mt8183-disp-dither                                   1                 3                  z                 
   B         dsi@14013000              mediatek,mt8186-dsi              0                    1      1               engine digital hs                 7               
   B              1           	           dphy             okay       port       endpoint            r               K            iommu@14016000            mediatek,mt8186-iommu-mm                 `                    1            bclk                  9             8                                                    
   B                          |      rdma@1401f000         4    mediatek,mt8186-disp-rdma mediatek,mt8183-disp-rdma                                  1                 4                  |               z                 
   B         clock-controller@14020000             mediatek,mt8186-wpesys                                x               7      smi@14023000              mediatek,mt8186-smi-larb                 0                    7      7            apb smi                       {        
   B                     clock-controller@15020000             mediatek,mt8186-imgsys1                               x               4      smi@1502e000              mediatek,mt8186-smi-larb                                     4      4             apb smi            	           {        
   B                     clock-controller@15820000             mediatek,mt8186-imgsys2                               x                     smi@1582e000              mediatek,mt8186-smi-larb                                     4                    apb smi                       {        
   B                     video-decoder@16000000            mediatek,mt8186-vcodec-dec                                                       +                      @                    |                 video-codec@16025000              mediatek,mtk-vcodec-core                 P                      W             `     |      |      |      |      |      |      |      |      |      |      |      |                -   )   2      2       -   U      %   vdec-sel vdec-soc-vdec vdec vdec-top            }   -   )           -   U        
   B            smi@1602e000              mediatek,mt8186-smi-larb                                     2       2             apb smi                       {        
   B                     clock-controller@1602f000             mediatek,mt8186-vdecsys                              x               2      clock-controller@17000000             mediatek,mt8186-vencsys                                x               6      smi@17010000              mediatek,mt8186-smi-larb                                      6      6            apb smi                       {        
   B                     video-encoder@17020000        6    mediatek,mt8186-vcodec-enc mediatek,mt8183-vcodec-enc                                                      H     |      |      |      |      |      |      |      |      |               6         	   venc_sel            }   -   $           -   U        
   B                    jpeg-encoder@17030000         +    mediatek,mt8186-jpgenc mediatek,mtk-jpgenc                                                          6            jpgenc              |      |      |      |           
   B         clock-controller@1a000000             mediatek,mt8186-camsys                                 x               3      smi@1a001000              mediatek,mt8186-smi-larb                                      3      3             apb smi                       {        
   B   
                  smi@1a002000              mediatek,mt8186-smi-larb                                       3      3            apb smi                       {        
   B   
                  smi@1a00f000              mediatek,mt8186-smi-larb                                      3                   apb smi                       {        
   B                     smi@1a010000              mediatek,mt8186-smi-larb                                      3                    apb smi                       {        
   B                     clock-controller@1a04f000             mediatek,mt8186-camsys_rawa                              x                     clock-controller@1a06f000             mediatek,mt8186-camsys_rawb                              x                     clock-controller@1b000000             mediatek,mt8186-mdpsys                                 x                     smi@1b002000              mediatek,mt8186-smi-larb                                                         apb smi                       {        
   B                     clock-controller@1c000000             mediatek,mt8186-ipesys                                 x               5      smi@1c00f000              mediatek,mt8186-smi-larb                                      5      5            apb smi                       {        
   B   	                  smi@1c10f000              mediatek,mt8186-smi-larb                                     5       5             apb smi                       {        
   B   	                     thermal-zones      cpu-little0-thermal                              4          trips      trip-alert0         D L        P           Epassive                   trip-alert1         D s        P           Ehot       trip-crit           D         P          	   Ecritical             cooling-maps       map0            [         H  `                              cpu-little1-thermal                              4         trips      trip-alert0         D L        P           Epassive                   trip-alert1         D s        P           Ehot       trip-crit           D         P          	   Ecritical             cooling-maps       map0            [         H  `                              cpu-little2-thermal                              4         trips      trip-alert0         D L        P           Epassive                   trip-alert1         D s        P           Ehot       trip-crit           D         P          	   Ecritical             cooling-maps       map0            [         H  `                              cam-thermal                              4         trips      trip-alert0         D L        P           Epassive       trip-alert1         D s        P           Ehot       trip-crit           D         P          	   Ecritical                nna-thermal                              4         trips      trip-alert0         D L        P           Epassive       trip-alert1         D s        P           Ehot       trip-crit           D         P          	   Ecritical                adsp-thermal                                 4         trips      trip-alert0         D L        P           Epassive       trip-alert1         D s        P           Ehot       trip-crit           D         P          	   Ecritical                gpu-thermal                              4         trips      trip-alert0         D L        P           Epassive                   trip-alert1         D s        P           Ehot       trip-crit           D         P          	   Ecritical             cooling-maps       map0            [           `               cpu-big0-thermal                         d        4         trips      trip-alert0         D L        P           Epassive                   trip-alert1         D s        P           Ehot       trip-crit           D         P          	   Ecritical             cooling-maps       map0            [           `                  cpu-big1-thermal                         d        4         trips      trip-alert0         D L        P           Epassive                   trip-alert1         D s        P           Ehot       trip-crit           D         P          	   Ecritical             cooling-maps       map0            [           `                     chosen          oserial0:115200n8          memory@40000000         memory               @                 backlight-lcd0            pwm-backlight           {                               ,                                         @            N      bt-sco            linux,bt-sco                      dmic-codec            dmic-codec                                    2      gpio-keys         
    gpio-keys           default               pen-insert-switch           	"Pen Insert          F   ,                                                          regulator-pp1800-dpbrdg-dx            regulator-fixed         default                    F   ,   '            pp1800_dpbrdg_dx                     /   ]            X      regulator-pp3300-disp-x           regulator-fixed         default                    F   ,               pp3300_disp_x                     :        /   _            M      regulator-pp3300-ldo-z5           regulator-fixed         pp3300_ldo_z5            5         :         2Z         2Z        /         regulator-pp3300-s3           regulator-fixed       
  pp3300_s3            5         :        /   _            R      regulator-pp3300-z2           regulator-fixed       
  pp3300_z2            5         :         2Z         2Z        /               _      regulator-pp4200-z2           regulator-fixed       
  pp4200_z2            5         :         @@         @@        /               9      regulator-pp5000-z2           regulator-fixed       
  pp5000_z2            5         :         LK@         LK@        /                     regulator-ppvar-sys           regulator-fixed       
  ppvar_sys            5         :                  reserved-memory                      +               audio-dma-pool            shared-dma-pool         z               L                V            i      memory@61000000           shared-dma-pool              a                   V            C      memory@60000000           shared-dma-pool              `                   V            D      memory@50000000           shared-dma-pool              P       
           V            ?         sound         ,    mediatek,mt8186-mt6366-rt1019-rt5682s-sound      C  aud_clk_mosi_off aud_clk_mosi_on aud_clk_miso_off aud_clk_miso_on aud_dat_miso_off aud_dat_miso_on aud_dat_mosi_off aud_dat_mosi_on aud_gpio_i2s0_off aud_gpio_i2s0_on aud_gpio_i2s1_off aud_gpio_i2s1_on aud_gpio_i2s2_off aud_gpio_i2s2_on aud_gpio_i2s3_off aud_gpio_i2s3_on aud_gpio_pcm_off aud_gpio_pcm_on aud_gpio_dmic_sec                     
           
           ]           g           q           {                                                                                                                                                                   I  &Headphone HPOL Headphone HPOR IN1P Headset Mic Speakers Speaker HDMI1 TX       hs-playback-dai-link            4I2S0            >i2s         Icpu    codec           _                hs-capture-dai-link         4I2S1            >i2s         Icpu    codec           _                spk-share-dai-link          4I2S2            Icpu       spk-hdmi-playback-dai-link          4I2S3            >i2s         Icpu    codec           _                  speaker-codec             realtek,rt1019p         default                                i   ,                         regulator-usb-p1-vbus             regulator-fixed         s   ,               vbus1            LK@         LK@                 /               v      wifi-pwrseq           mmc-pwrseq-simple           default                    x   2        L   ,   6               r      wifi-wakeup       
    gpio-keys           default               wowlan-event            	"Wake on WiFi            F   ,                                       	compatible interrupt-parent #address-cells #size-cells model chassis-type ovl0 ovl-2l0 rdma0 rdma1 i2c0 i2c1 i2c2 i2c3 i2c5 mmc0 mmc1 serial0 i2c4 clocks reg status clock-names operating-points-v2 proc-supply phandle opp-shared opp-hz opp-microvolt required-opps cpu device_type enable-method clock-frequency dynamic-power-coefficient capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells mediatek,cci entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-div clock-mult clock-output-names opp-supported-hw interrupts dma-ranges #interrupt-cells #redistributor-regions interrupt-controller mediatek,broken-save-restore-fw affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux input-enable bias-pull-down input-schmitt-enable bias-disable output-low drive-strength output-high bias-pull-up #power-domain-cells domain-supply mediatek,infracfg mediatek,disable-extrst mediatek,reset-by-toprgu interrupts-extended Avdd-supply mediatek,dmic-mode vsys-ldo1-supply vsys-ldo2-supply vsys-ldo3-supply vsys-vcore-supply vsys-vdram1-supply vsys-vgpu-supply vsys-vmodem-supply vsys-vpa-supply vsys-vproc11-supply vsys-vproc12-supply vsys-vs1-supply vsys-vs2-supply vs1-ldo1-supply vs2-ldo1-supply vs2-ldo2-supply vs2-ldo3-supply regulator-name regulator-min-microvolt regulator-max-microvolt regulator-ramp-delay regulator-enable-ramp-delay regulator-allowed-modes regulator-always-on regulator-coupled-with regulator-coupled-max-spread assigned-clocks assigned-clock-parents #mbox-cells pinctrl-names pinctrl-0 firmware-name memory-region mediatek,rpmsg-name mbox-names mboxes power-domains spi-max-frequency #io-channel-cells powerdown-gpios reset-gpios vdd12-supply vdd33-supply remote-endpoint power-supply backlight i2c-scl-internal-delay-ns vcc33-supply no-reset-on-power-off vcc-supply wakeup-source #sound-dai-cells ovdd-supply pwr18-supply extcon link-frequencies svdd-supply AVDD-supply DBVDD-supply LDO1-IN-supply MICVDD-supply realtek,jd-src resets nvmem-cells nvmem-cell-names #thermal-sensor-cells reset-names #pwm-cells mediatek,pad-select google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count label power-role data-role try-power-role google,usb-port-id keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap cs-gpios mediatek,apmixedsys mediatek,topckgen phys mediatek,syscon-wakeup vbus-supply pinctrl-1 bus-width non-removable cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v supports-cqe no-sd no-sdio cap-mmc-hw-reset hs400-ds-delay mediatek,hs400-ds-dly3 vmmc-supply vqmmc-supply pinctrl-2 interrupt-names cap-sd-highspeed sd-uhs-sdr104 sd-uhs-sdr50 keep-power-in-suspend cap-sdio-irq no-mmc mmc-pwrseq #phy-cells mediatek,discth bits power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,larb-id mediatek,smi iommus phy-names mediatek,larbs #iommu-cells mediatek,scp polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path pwms enable-gpios brightness-levels num-interpolated-steps default-brightness-level num-channels wakeup-delay-ms wakeup-event-action linux,code linux,input-type enable-active-high vin-supply regulator-boot-on alignment no-map pinctrl-3 pinctrl-4 pinctrl-5 pinctrl-6 pinctrl-7 pinctrl-8 pinctrl-9 pinctrl-10 pinctrl-11 pinctrl-12 pinctrl-13 pinctrl-14 pinctrl-15 pinctrl-16 pinctrl-17 pinctrl-18 mediatek,adsp mediatek,platform audio-routing link-name dai-format mediatek,clk-provider sound-dai sdb-gpios gpio post-power-on-delay-ms 