    8    (                                                                                   ,Freescale i.MX8QM MEK            2fsl,imx8qm-mek fsl,imx8qm      aliases          =/bus@5b000000/mmc@5b010000           B/bus@5b000000/mmc@5b020000           G/bus@5b000000/mmc@5b030000           L/bus@5a000000/serial@5a060000            T/bus@5a000000/serial@5a070000            \/bus@5a000000/serial@5a080000            d/bus@5a000000/serial@5a090000            l/bus@5a000000/spi@5a000000           q/bus@5a000000/spi@5a010000           v/bus@5a000000/spi@5a020000           {/bus@5a000000/spi@5a030000            /vpu@2c000000/vpu-core@2d080000           /vpu@2c000000/vpu-core@2d090000           /vpu@2c000000/vpu-core@2d0a0000       cpus                                 cpu@0            cpu          2arm,cortex-a53                                               psci                            @                                    @                              ,           @           O   	      cpu@1            cpu          2arm,cortex-a53                                              psci                            @                                    @                              ,           @           O   
      cpu@2            cpu          2arm,cortex-a53                                              psci                            @                                    @                              ,           @           O         cpu@3            cpu          2arm,cortex-a53                                              psci                            @                                    @                              ,           @           O         l2-cache0            2cache           W            c                        @                    O         l2-cache1            2cache           W            c                        @                    O           opp-table-0          2operating-points-v2          q        O      opp-600000000           |    #F                   I      opp-896000000           |    5g          B@         I      opp-1104000000          |    Aʹ                   I      opp-1200000000          |    G                   I                  opp-table-1          2operating-points-v2          q        O     opp-600000000           |    #F          B@         I      opp-1056000000          |    >H          B@         I      opp-1296000000          |    M?d                   I      opp-1596000000          |    _!                   I                  interrupt-controller@51a00000            2arm,gic-v3        P       Q             Q             R               R             R                                                        	                        O         pmu          2arm,armv8-pmuv3                        psci             2arm,psci-1.0             smc       timer            2arm,armv8-timer       0                                   
         iommu@51400000           2arm,mmu-500                           Q@                                                                                                                                                                                                                                                                                                                                                                                                                         O         system-controller            2fsl,imx-scu         tx0 rx0 gip3          $  
                                 power-controller             2fsl,imx8qm-scu-pd fsl,scu-pd                       O         clock-controller             2fsl,imx8qm-clk fsl,scu-clk          %           O         pinctrl          2fsl,imx8qm-iomuxc           2default         @           O      hoggrp          J   s      L   '     L        O         cs42888_resetgrp            J        L        O         i2c-mipi-csi0grp            J   I          J               O        i2c-mipi-csi1grp            J   P          Q               O        i2c0grp         J   R     !   S     !        O         i2c1grp         J        L        L        O         i2c1gpio-grp            J        L        L        O         adc0grp         J         `        O         cm41i2cgrp          J         L         L        O         esai0grp          x  J   h      @   i      @   j      @   k      @   l      @   m      @   n      @   o      @   p      @   q      @        O   "      fec1grp         J                                                                                                                                                    O         lpspi2grp         $  J   z      @   {      @   |      @        O         lpspi2csgrp         J   }      !        O         mipi0_lpi2c0grp       $  J   ?          @          B               O   Y      mipi1_lpi2c0grp       $  J   C          D          F               O   i      flexspi0grp         J         !         !         !         !         !         !         !         !         !         !         !         !         !         !         !         !        O         fec2grp         J                 `          `         `         `         `         `         `         `         `  	       `  
       `         `        O         flexcan0grp         J          !          !        O         flexcan1grp         J          !          !        O         flexcan3grp         J          !          !        O         lpuart0grp          J                            O         lpuart2grp          J                          O         lpuart3grp          J                          O         lvds0lpi2c1grp          J   6      L   7      L        O   a      lvds1lpi2c1grp          J   <      L   =      L        O   p      mipi-csi0grp          $  J   K     A   L     A   H      A        O        mipi-csi1grp          $  J   N     A   O     A   M      A        O        pcieagrp          $  J        !        !   +               O         pcieareggrp         J   ;     !        O         pciebgrp          $  J         !        !        !        O         pwmlvds0grp         J   2               O   ]      pwmlvds1grp         J   8               O   m      sai0grp       0  J   y     L   ~     L        L        l        O   &      sai1grp       0  J         @         @         `         @        O   (      typecgrp            J         !        O         typecmuxgrp         J         `         `        O         usdhc1grp           J         A          !          !          !          !          !          !          !          !          !          A        O         usdhc2grp         T  J         A          !          !          !          !          !          !        O            reset-controller             2fsl,imx-scu-reset           S           O         rtc          2fsl,imx8qxp-sc-rtc          O        ocotp            2fsl,imx8qm-scu-ocotp                                      `        O     mac@1c4                       O        mac@1c6                       O            thermal-sensor        *   2fsl,imx8qxp-sc-thermal fsl,imx-sc-thermal           j           O         watchdog          !   2fsl,imx8qm-sc-wdt fsl,imx-sc-wdt               <         thermal-zones      cpu0-thermal                                           trips      trip0                               passive         O         trip1                            	   critical            O           cooling-maps       map0                     0     	   
                  gpu0-thermal                                          trips      trip0                               passive         O        trip1                            	   critical            O              gpu1-thermal                                          trips      trip0                               passive         O        trip1                            	   critical            O              drc0-thermal                                          trips      trip0                               passive         O        trip1                            	   critical            O                 clock-dummy          2fixed-clock         %                      
  clk_dummy           O         clock-esai1-rx           2fixed-clock         %                        esai1_rx_clk            O   =      clock-esai1-rx-hf            2fixed-clock         %                        esai1_rx_hf_clk         O   >      clock-esai1-tx           2fixed-clock         %                        esai1_tx_clk            O   ?      clock-esai1-tx-hf            2fixed-clock         %                        esai1_tx_hf_clk         O   @      clock-hdmi-rx-mclk           2fixed-clock         %                        hdmi-rx-mclk            O   6      clock-mlb-clk            2fixed-clock         %                        mlb_clk         O   5      clock-sai5-rx-bclk           2fixed-clock         %                        sai5_rx_bclk            O   I      clock-sai5-tx-bclk           2fixed-clock         %                        sai5_tx_bclk            O        clock-sai6-rx-bclk           2fixed-clock         %                        sai6_rx_bclk            O   J      clock-sai6-tx-bclk           2fixed-clock         %                        sai6_tx_bclk            O        clock-spdif1-rx          2fixed-clock         %                      
  spdif1_rx           O        clock-controller-lvds-ipg            2fixed-clock         %            n6         lvds0_ipg_clk           O   [      clock-controller-dsi-ipg             2fixed-clock         %            '         dsi_ipg_clk         O   S      clock-controller-mipi-div2-pll           2fixed-clock         %                     mipi_pll_div2_clk           O         bus@55000000             2simple-bus                                   U       U              O  !   dsp@556e8000             2fsl,imx8qm-hifi4             Un                             ipg ocram core           !                             $  
                                       tx rx rxdb          /imx/dsp/hifi4.bin           =okay            D                    O  "         bus@31400000             2simple-bus                                   1@      1@   	          O  #   crypto@31400000          2fsl,imx8qm-caam fsl,sec-v4.0             1@   	                                                         1@   	          !             R   	        O  $   jr@30000          *   2fsl,imx8qm-job-ring fsl,sec-v4.0-job-ring                                           !             O  %      jr@40000          *   2fsl,imx8qm-job-ring fsl,sec-v4.0-job-ring                                           !             O  &            clock-cm41-ipg           2fixed-clock         %            )         cm41_ipg_clk            O         bus@38000000             2simple-bus                                   8       8                           O  '   i2c@3b230000          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c          ;#                	                                 per ipg         ^     4           nn6         !     4        =okay                                               2default         @           O  (   gpio@20          2ti,tca6416                                           O         audio-codec@48           2cirrus,cs42888              H                        mclk            2default         @                                                                      ,  ^     E        E         E                  n.                O            intmux@3b400000          2fsl,imx-intmux           ;@                        `                                                           '                                                               ipg         !     5        =okay            O         clock-controller@3b630000            2fsl,imx8qxp-lpcg             ;c             %                 4                           (  cm41_lpcg_i2c_clk cm41_lpcg_i2c_ipg_clk         !     4        O            clock-audio-ipg          2fixed-clock         %            '         audio_ipg_clk           O   $      clock-ext-aud-mclk0          2fixed-clock         %                        ext_aud_mclk0           O   7      clock-ext-aud-mclk1          2fixed-clock         %                        ext_aud_mclk1           O   8      clock-esai0-rx           2fixed-clock         %                        esai0_rx_clk            O   9      clock-esai0-rx-hf            2fixed-clock         %                        esai0_rx_hf_clk         O   :      clock-esai0-tx           2fixed-clock         %                        esai0_tx_clk            O   ;      clock-esai0-tx-hf            2fixed-clock         %                        esai0_tx_hf_clk         O   <      clock-spdif0-rx          2fixed-clock         %                      
  spdif0_rx           O   A      clock-sai0-rx-bclk           2fixed-clock         %                        sai0_rx_bclk            O   B      clock-sai0-tx-bclk           2fixed-clock         %                        sai0_tx_bclk            O   C      clock-sai1-rx-bclk           2fixed-clock         %                        sai1_rx_bclk            O   D      clock-sai1-tx-bclk           2fixed-clock         %                        sai1_tx_bclk            O   E      clock-sai2-rx-bclk           2fixed-clock         %                        sai2_rx_bclk            O   F      clock-sai3-rx-bclk           2fixed-clock         %                        sai3_rx_bclk            O   G      clock-sai4-rx-bclk           2fixed-clock         %                        sai4_rx_bclk            O   H      bus@59000000             2simple-bus                                   Y       Y              O  )   asrc@59000000            2fsl,imx8qm-asrc          Y                    t         d                                                                                          mem ipg asrck_0 asrck_1 asrck_2 asrck_3 asrck_4 asrck_5 asrck_6 asrck_7 asrck_8 asrck_9 asrck_a asrck_b asrck_c asrck_d asrck_e asrck_f spba          `                                                                                                  rxa rxb rxc txa txb txc                                           !             =okay            O         esai@59010000         !   2fsl,imx8qm-esai fsl,imx6ull-esai             Y                                  !       !      !               core extal fsys spba                                                  rx tx           !             =okay            2default         @   "      4  ^           E        E         E      !                           n    .                O         spdif@59020000           2fsl,imx8qm-spdif             Y                                     0      #         #               $               :  core rxtx0 rxtx1 rxtx2 rxtx3 rxtx4 rxtx5 rxtx6 rxtx7 spba                                 	               rx tx           !           	  =disabled            O  *      sai@59040000             2fsl,imx8qm-sai           Y                   :               %          %                 bus mclk0 mclk1 mclk2 mclk3         rx tx                                                 !     >        =okay            7          ,  ^     E        E         E      %           n.                2default         @   &        O         sai@59050000             2fsl,imx8qm-sai           Y                   <               '          '                 bus mclk0 mclk1 mclk2 mclk3         rx tx                                                 !     ?        =okay          ,  ^     E        E         E      '           n.                2default         @   (        O         sai@59060000             2fsl,imx8qm-sai           Y                   >               )          )                 bus mclk0 mclk1 mclk2 mclk3         rx                                !     @      	  =disabled            O  +      sai@59070000             2fsl,imx8qm-sai           Y                   C               *          *                 bus mclk0 mclk1 mclk2 mclk3         rx                                !           	  =disabled            O  ,      dma-controller@591f0000          2fsl,imx8qm-edma          Y             H           S           `                  v         w         x         y         z         {                                                               ;         ;         =         =         ?         D         F         H           !                                                                                                               O          clock-controller@59400000            2fsl,imx8qxp-lpcg             Y@             %               $   $                     &  asrc0_lpcg_ipg_clk asrc0_lpcg_mem_clk           !             O         clock-controller@59410000            2fsl,imx8qxp-lpcg             YA             %                     $                     (  esai0_lpcg_extal_clk esai0_lpcg_ipg_clk         !             O   !      clock-controller@59420000            2fsl,imx8qxp-lpcg             YB             %                     $                    %  spdif0_lpcg_tx_clk spdif0_lpcg_gclkw            !             O   #      clock-controller@59440000            2fsl,imx8qxp-lpcg             YD             %                     $                     !  sai0_lpcg_mclk sai0_lpcg_ipg_clk            !     >        O   %      clock-controller@59450000            2fsl,imx8qxp-lpcg             YE             %                     $                     !  sai1_lpcg_mclk sai1_lpcg_ipg_clk            !     ?        O   '      clock-controller@59460000            2fsl,imx8qxp-lpcg             YF             %                     $                     !  sai2_lpcg_mclk sai2_lpcg_ipg_clk            !     @        O   )      clock-controller@59470000            2fsl,imx8qxp-lpcg             YG             %                     $                     !  sai3_lpcg_mclk sai3_lpcg_ipg_clk            !             O   *      clock-controller@59580000            2fsl,imx8qxp-lpcg             YX             %               $   $   $                       4  dsp_lpcg_adb_clk dsp_lpcg_ipg_clk dsp_lpcg_core_clk         !            	  =disabled            O  -      clock-controller@59590000            2fsl,imx8qxp-lpcg             YY             %               $                   dsp_ram_lpcg_ipg_clk            !           	  =disabled            O  .      asrc@59800000            2fsl,imx8qm-asrc          Y                   |         d      +       +                                                                             mem ipg asrck_0 asrck_1 asrck_2 asrck_3 asrck_4 asrck_5 asrck_6 asrck_7 asrck_8 asrck_9 asrck_a asrck_b asrck_c asrck_d asrck_e asrck_f spba          `     ,               ,              ,              ,             ,             ,                  rxa rxb rxc txa txb txc           @                               !           	  =disabled            O  /      sai@59820000             2fsl,imx8qm-sai           Y                   I               -          -                 bus mclk0 mclk1 mclk2 mclk3             ,             ,   	                rx tx           !             =okay          4  ^                                  -                           n    .                 q        O   0      sai@59830000             2fsl,imx8qm-sai           Y                   K               .          .                 bus mclk0 mclk1 mclk2 mclk3            ,   
                tx          !             =okay          4  ^                                  .                           n    .                 q        O   1      amix@59840000            2fsl,imx8qm-audmix            Y                 /            ipg         !                0   1        =okay            O  0      mqs@59850000             2fsl,imx8qm-mqs           Y                 2      2          
  mclk core           !           	  =disabled            O  1      dma-controller@599f0000          2fsl,imx8qm-edma          Y             H           S           `                 ~                                                                            J         J         L         X  !                                                               O   ,      clock-controller@59d00000            2fsl,imx8qxp-lpcg             Y             %                 E                       aud_rec_clk0_lpcg_clk           !     E        O   3      clock-controller@59d10000            2fsl,imx8qxp-lpcg             Y             %                                        aud_rec_clk1_lpcg_clk           !             O   4      clock-controller@59d20000            2fsl,imx8qxp-lpcg             Y             %                 E                        aud_pll_div_clk0_lpcg_clk           !     E        O         clock-controller@59d30000            2fsl,imx8qxp-lpcg             Y             %                                         aud_pll_div_clk1_lpcg_clk           !             O         clock-controller@59d50000            2fsl,imx8qxp-lpcg             Y             %                                      mclkout0_lpcg_clk           !             O         clock-controller@59d60000            2fsl,imx8qxp-lpcg             Y             %                                      mclkout1_lpcg_clk           !             O  2      acm@59e00000             2fsl,imx8qm-acm           Y             %           !                         E                              >     ?     @                                              |      3       4                     5   6   7   8   9   :   ;   <   =   >   ?   @   A   A   B   C   D   E   F   G   H   I   J       aud_rec_clk0_lpcg_clk aud_rec_clk1_lpcg_clk aud_pll_div_clk0_lpcg_clk aud_pll_div_clk1_lpcg_clk mlb_clk hdmi_rx_mclk ext_aud_mclk0 ext_aud_mclk1 esai0_rx_clk esai0_rx_hf_clk esai0_tx_clk esai0_tx_hf_clk esai1_rx_clk esai1_rx_hf_clk esai1_tx_clk esai1_tx_hf_clk spdif0_rx spdif1_rx sai0_rx_bclk sai0_tx_bclk sai1_rx_bclk sai1_tx_bclk sai2_rx_bclk sai3_rx_bclk sai4_rx_bclk sai5_tx_bclk sai6_rx_bclk           O         clock-controller@59c00000            2fsl,imx8qxp-lpcg             Y             %               $   $                     &  asrc1_lpcg_ipg_clk asrc1_lpcg_mem_clk           !             O   +      clock-controller@59c20000            2fsl,imx8qxp-lpcg             Y             %                     $                     !  sai6_lpcg_mclk sai6_lpcg_ipg_clk            !             O   -      clock-controller@59c30000            2fsl,imx8qxp-lpcg             Y             %                     $                     !  sai7_lpcg_mclk sai7_lpcg_ipg_clk            !             O   .      clock-controller@59c40000            2fsl,imx8qxp-lpcg             Y             %               $                    amix_lpcg_ipg_clk           !             O   /      clock-controller@59c50000            2fsl,imx8qxp-lpcg             Y             %                     $                     !  mqs0_lpcg_mclk mqs0_lpcg_ipg_clk            !             O   2      sai@59080000             2fsl,imx8qm-sai           Y                   E               K          K                 bus mclk0 mclk1 mclk2 mclk3         rx                                                   !           	  =disabled            O  3      sai@59090000             2fsl,imx8qm-sai           Y	                   G               L          L                 bus mclk0 mclk1 mclk2 mclk3         tx                                                    !           	  =disabled            O  4      clock-controller@59480000            2fsl,imx8qxp-lpcg             YH             %                     $                     !  sai4_lpcg_mclk sai4_lpcg_ipg_clk            !           	  =disabled            O   K      clock-controller@59490000            2fsl,imx8qxp-lpcg             YI             %                     $                     !  sai5_lpcg_mclk sai5_lpcg_ipg_clk            !           	  =disabled            O   L      esai@59810000         !   2fsl,imx8qm-esai fsl,imx6ull-esai             Y                                  M       M      M               core extal fsys spba                ,             ,                   rx tx           !           	  =disabled            O  5      clock-controller@59c10000            2fsl,imx8qxp-lpcg             Y             %                     $                     (  esai1_lpcg_extal_clk esai1_lpcg_ipg_clk         !             O   M         vpu@2c000000                                     ,       ,                   ,                  !           	  =disabled            O  6   mailbox@2d000000             2fsl,imx6sx-mu            -                                          !           	  =disabled            O   N      mailbox@2d020000             2fsl,imx6sx-mu            -                                         !           	  =disabled            O   O      mailbox@2d040000             2fsl,imx6sx-mu            -                                         !           	  =disabled            O   P      vpu-core@2d080000            -              2nxp,imx8q-vpu-decoder           !             tx0 tx1 rx        $  
   N           N          N             	  =disabled            O  7      vpu-core@2d090000            -	              2nxp,imx8q-vpu-encoder           !             tx0 tx1 rx        $  
   O           O          O             	  =disabled            O  8      vpu-core@2d0a0000            -
              2nxp,imx8q-vpu-encoder           !             tx0 tx1 rx        $  
   P           P          P             	  =disabled            O  9         bus@53000000             2simple-bus                                   S       S              O  :   gpu@53100000             2vivante,gc           S                    @                                      core shader         ^                          n)' 2        !              O  ;         bus@56220000             2simple-bus               Q                                 V"      V"             O  <   interrupt-controller@56220000         &   2fsl,imx8qxp-irqsteer fsl,imx-irqsteer            V"                    ;                                                R            ipg         !                                     O   Q      clock-controller@56223000            2fsl,imx8qxp-lpcg             V"0            %           !                 S                    mipi0_lis_lpcg_ipg_clk          O   R      clock-controller@5622300c            2fsl,imx8qxp-lpcg             V"0           %           !                         S                     *  mipi0_pwm_lpcg_clk mipi0_pwm_lpcg_ipg_clk           O   V      clock-controller@56223014            2fsl,imx8qxp-lpcg             V"0           %               T                        mipi0_i2c0_lpcg_ipg_clk         !             O   X      clock-controller@56223018            2fsl,imx8qxp-lpcg             V"0           %               S                    mipi0_i2c0_lpcg_ipg_s_clk           !             O   T      clock-controller@5622301c            2fsl,imx8qxp-lpcg             V"0           %                                        mipi0_i2c0_lpcg_clk         !             O   W      clock-controller@56223024            2fsl,imx8qxp-lpcg             V"0$           %               U                        mipi0_i2c1_lpcg_ipg_clk         !             O  =      clock-controller@56223028            2fsl,imx8qxp-lpcg             V"0(           %               S                    mipi0_i2c1_lpcg_ipg_s_clk           !             O   U      clock-controller@5622302c            2fsl,imx8qxp-lpcg             V"0,           %                                        mipi0_i2c1_lpcg_clk         !             O  >      pwm@56224000             2fsl,imx8qxp-pwm fsl,imx27-pwm            V"@                V      V            ipg per         ^                nn6                    !           	  =disabled            O  ?      i2c@56226000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           V"`                                                     W       X            per ipg         ^   W            nn6         !             =okay            2default         @   Y                 O  @         bus@56240000             2simple-bus                                   V$      V$                  Z        O  A   clock-controller@56243000            2fsl,imx8qxp-lpcg             V$0            %           lvds0_lis_lpcg_ipg_clk          !                 [                   O   _      clock-controller@5624300c            2fsl,imx8qxp-lpcg             V$0           %         A  lvds0_pwm_lpcg_clk lvds0_pwm_lpcg_ipg_clk lvds0_pwm_lpcg_32k_clk            !                         [                       O   \      clock-controller@56243010            2fsl,imx8qxp-lpcg             V$0           %         ,  lvds0_i2c0_lpcg_clk lvds0_i2c0_lpcg_ipg_clk         !                         [                       O   ^      pwm@56244000             2fsl,imx8qxp-pwm fsl,imx27-pwm            V$@            ipg per         ^                nn6                    !             =okay                \      \            2default         @   ]        O         i2c@56246000          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c          V$`                                                 per ipg         ^                nn6         !           	  =disabled                ^       ^           O  B      interrupt-controller@56240000         %   2fsl,imx8qm-irqsteer fsl,imx-irqsteer             V$                    9                                                _           ipg         !     
                                O   Z      clock-controller@56243014            2fsl,imx8qxp-lpcg             V$0           %                       [                     ,  lvds0_i2c1_lpcg_clk lvds0_i2c1_lpcg_ipg_clk         !             O   `      i2c@56247000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           V$p               	            `       `           per ipg         ^                nn6         !             =okay            2default         @   a                 O  C         bus@57220000             2simple-bus               b                                 W"      W"             O  D   interrupt-controller@57220000         %   2fsl,imx8qm-irqsteer fsl,imx-irqsteer             W"                    <                                                c            ipg         !                                     O   b      clock-controller@57223000            2fsl,imx8qxp-lpcg             W"0            %               S                    mipi1_lis_lpcg_ipg_clk          !             O   c      clock-controller@5722300c            2fsl,imx8qxp-lpcg             W"0           %                       S                     *  mipi1_pwm_lpcg_clk mipi1_pwm_lpcg_ipg_clk           !             O   f      clock-controller@5722301c            2fsl,imx8qxp-lpcg             W"0           %                                        mipi1_i2c0_lpcg_clk         !             O   g      clock-controller@57223014            2fsl,imx8qxp-lpcg             W"0           %               d                        mipi1_i2c0_lpcg_ipg_clk         !             O   h      clock-controller@57223018            2fsl,imx8qxp-lpcg             W"0           %               S                    mipi1_i2c0_lpcg_ipg_s_clk           !             O   d      clock-controller@57223024            2fsl,imx8qxp-lpcg             W"0$           %               e                        mipi1_i2c1_lpcg_ipg_clk         !             O  E      clock-controller@57223028            2fsl,imx8qxp-lpcg             W"0(           %               S                    mipi1_i2c1_lpcg_ipg_s_clk           !             O   e      clock-controller@5722302c            2fsl,imx8qxp-lpcg             W"0,           %                                        mipi1_i2c1_lpcg_clk         !             O  F      pwm@57224000             2fsl,imx8qxp-pwm fsl,imx27-pwm            W"@                f      f            ipg per         ^                nn6                    !           	  =disabled            O  G      i2c@57226000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           W"`                                                      b            g       h            per ipg         ^   g            nn6         !             =okay            2default         @   i                 O  H         bus@57240000             2simple-bus               j                                 W$      W$             O  I   interrupt-controller@57240000         %   2fsl,imx8qm-irqsteer fsl,imx-irqsteer             W$                    :                                                k           ipg         !                                     O   j      clock-controller@57243000            2fsl,imx8qxp-lpcg             W$0            %               [                   lvds1_lis_lpcg_ipg_clk          !             O   k      clock-controller@5724300c            2fsl,imx8qxp-lpcg             W$0           %                       [                     *  lvds1_pwm_lpcg_clk lvds1_pwm_lpcg_ipg_clk           !             O   l      clock-controller@57243010            2fsl,imx8qxp-lpcg             W$0           %                       [                     ,  lvds1_i2c0_lpcg_clk lvds1_i2c0_lpcg_ipg_clk         !             O   n      clock-controller@57243014            2fsl,imx8qxp-lpcg             W$0           %                       [                     ,  lvds1_i2c1_lpcg_clk lvds1_i2c1_lpcg_ipg_clk         !             O   o      pwm@57244000             2fsl,imx8qxp-pwm fsl,imx27-pwm            W$@                l      l            ipg per         ^                nn6                    !             =okay            2default         @   m        O         i2c@57246000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           W$`                                                     n       n           per ipg         ^                nn6         !           	  =disabled            O  J      i2c@57247000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           W$p               	            o       o           per ipg         ^                nn6         !             =okay            2default         @   p                 O  K         clock-img-ipg            2fixed-clock         %                     img_ipg_clk         O   {      clock-img-pxl            2fixed-clock         %            #F         img_pxl_clk         O         bus@58000000             2simple-bus                                   X       X              O  L   isi@58100000             X           `        )         *         +         ,         -         .         /         0         @      q       r       s       t       u       v       w       x          (  per0 per1 per2 per3 per4 per5 per6 per7                    @  !     y     z     {     |     }     ~                  =okay led         2fsl,imx8qm-isi          O  M   ports                                port@2                 endpoint               y        O            port@3                 endpoint               z        O                  irqsteer@58220000           =okay mx8      %   2fsl,imx8qm-irqsteer fsl,imx-irqsteer             X"                                       @               {        ipg                      !                                     O   |      gpio@58222000            2fsl,imx8qm-gpio fsl,imx35-gpio           X"                                                                      |        !             O  N      clock-controller@58223018            2fsl,imx8qxp-lpcg             X"0                            %                      csi0_lpcg_core_clk          !     y        O   }      clock-controller@5822301c            2fsl,imx8qxp-lpcg             X"0                            %                      csi0_lpcg_esc_clk           !     y        O   ~      i2c@58226000            2default         @                                           $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c          X"`                                   {        per ipg         ^                nn6              |        !             =okay led        O  O   camera@3c                                                                            2default         @          xclk                          <         2ovti,ov5640    port       endpoint            O                                                    csi@58227000          +   2fsl,imx8qm-mipi-csi2 fsl,imx8qxp-mipi-csi2           X"p    X"                }      ~                  core esc ui         ^   }      ~           nu* J         !     y                     =okay led        O  P   ports                                port@0                  endpoint            O                                   port@1                 endpoint                       O   y               irqsteer@58240000           =okay mx8      %   2fsl,imx8qm-irqsteer fsl,imx-irqsteer             X$                                       A               {        ipg                      !                                     O         gpio@58242000            2fsl,imx8qm-gpio fsl,imx35-gpio           X$                                                                              !             O  Q      clock-controller@58243018            2fsl,imx8qxp-lpcg             X$0                            %                      csi1_lpcg_core_clk          !     y        O         clock-controller@5824301c            2fsl,imx8qxp-lpcg             X$0                            %                      csi1_lpcg_esc_clk           !     y        O         i2c@58246000            2default         @                                           $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c          X$`                                   {        per ipg         ^                nn6                      !             =okay led        O  R   camera@3c                                                                            2default         @          xclk                          <         2ovti,ov5640    port       endpoint            O                                                    csi@58247000          +   2fsl,imx8qm-mipi-csi2 fsl,imx8qxp-mipi-csi2           X$p    X$                                        core esc ui         ^                    nu* J         !     y                     =okay led        O  S   ports                                port@0                  endpoint            O                                   port@1                 endpoint                       O   z               irqsteer@58260000         %   2fsl,imx8qm-irqsteer fsl,imx-irqsteer             X&                                       B                       ipg                      !     F                              	  =disabled            O         clock-controller@58263004            2fsl,imx8qxp-lpcg             X&0                 F           %                      pi0_lpcg_ipg_clk            !     y      	  =disabled            O  T      clock-controller@58263018            2fsl,imx8qxp-lpcg             X&0                 F           %                       pi0_lpcg_pxl_clk            !     y      	  =disabled            O  U      clock-controller@5826301c            2fsl,imx8qxp-lpcg             X&0                 F            %                       pi0_lpcg_misc_clk           !     y      	  =disabled            O  V      i2c@58266000          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c          X&`                             I      {        per ipg         ^     I           nn6                      !     I      	  =disabled            O  W      jpegdec@58400000             X@                   5                                 ^                     n          !                %   2nxp,imx8qm-jpgdec nxp,imx8qxp-jpgdec            O  X      jpegenc@58450000             XE                   1                                 ^                     n          !                %   2nxp,imx8qm-jpgenc nxp,imx8qxp-jpgenc            O  Y      clock-controller@58500000            2fsl,imx8qxp-lpcg             XP                         %                       pdma0_lpcg_clk          !     y        O   q      clock-controller@58510000            2fsl,imx8qxp-lpcg             XQ                         %                       pdma1_lpcg_clk          !     z        O   r      clock-controller@58520000            2fsl,imx8qxp-lpcg             XR                         %                       pdma2_lpcg_clk          !     {        O   s      clock-controller@58530000            2fsl,imx8qxp-lpcg             XS                         %                       pdma3_lpcg_clk          !     |        O   t      clock-controller@58540000            2fsl,imx8qxp-lpcg             XT                         %                       pdma4_lpcg_clk          !     }        O   u      clock-controller@58550000            2fsl,imx8qxp-lpcg             XU                         %                       pdma5_lpcg_clk          !     ~        O   v      clock-controller@58560000            2fsl,imx8qxp-lpcg             XV                         %                       pdma6_lpcg_clk          !             O   w      clock-controller@58570000            2fsl,imx8qxp-lpcg             XW                         %                       pdma7_lpcg_clk          !             O   x      clock-controller@58580000            2fsl,imx8qxp-lpcg             XX                         %                       csi0_lpcg_pxl_clk           !             O         clock-controller@58590000            2fsl,imx8qxp-lpcg             XY                         %                       csi1_lpcg_pxl_clk           !             O         clock-controller@585a0000            2fsl,imx8qxp-lpcg             XZ                         %                       hdmi_rx_lpcg_pxl_link_clk           !             O  Z      clock-controller@585d0000            2fsl,imx8qxp-lpcg             X]             %               {   {                     0  img_jpeg_dec_lpcg_clk img_jpeg_dec_lpcg_ipg_clk         !             O         clock-controller@585f0000            2fsl,imx8qxp-lpcg             X_             %               {   {                     0  img_jpeg_enc_lpcg_clk img_jpeg_enc_lpcg_ipg_clk         !             O            clock-dma-ipg            2fixed-clock         %            '         dma_ipg_clk         O         bus@5a000000             2simple-bus                                   Z       Z              O  [   spi@5a000000             2fsl,imx7ulp-spi          Z                                              P                                              per ipg         ^      5           n         !      5                                             tx rx         	  =disabled            O  \      spi@5a010000             2fsl,imx7ulp-spi          Z                                             Q                                              per ipg         ^      6           n         !      6                                            tx rx         	  =disabled            O  ]      spi@5a020000             2fsl,imx7ulp-spi          Z                                             R                                              per ipg         ^      7           n         !      7                                            tx rx           =okay            2default         @                    
           O  ^      spi@5a030000             2fsl,imx7ulp-spi          Z                                             S                                              per ipg         ^      8           n         !      8                                            tx rx         	  =disabled            O  _      serial@5a060000          Z                   Y                               	  ipg baud            ^      9           nĴ         !      9        rx tx                                               =okay          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            2default         @           O  `      serial@5a070000          Z                   Z                               	  ipg baud            ^      :           nĴ         !      :        rx tx                                             	  =disabled          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            O  a      serial@5a080000          Z                   [                               	  ipg baud            ^      ;           nĴ         !      ;        rx tx                                               =okay          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            2default         @           O  b      serial@5a090000          Z	                   \                               	  ipg baud            ^      <           nĴ         !      <        rx tx                                               =okay          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            2default         @           O  c      dma-controller@5a1f0000          2fsl,imx8qm-edma          Z             H           S                                                                                                                                                                                                                                !      @      A      B      C      D      E      F      G      H      I      J      K      L      M      N      O      P      Q      R      S      T      U        `           =okay            O         clock-controller@5a400000            2fsl,imx8qxp-lpcg             Z@             %                  5                              spi0_lpcg_clk spi0_lpcg_ipg_clk         !      5        O         clock-controller@5a410000            2fsl,imx8qxp-lpcg             ZA             %                  6                              spi1_lpcg_clk spi1_lpcg_ipg_clk         !      6        O         clock-controller@5a420000            2fsl,imx8qxp-lpcg             ZB             %                  7                              spi2_lpcg_clk spi2_lpcg_ipg_clk         !      7        O         clock-controller@5a430000            2fsl,imx8qxp-lpcg             ZC             %                  8                              spi3_lpcg_clk spi3_lpcg_ipg_clk         !      8        O         clock-controller@5a460000            2fsl,imx8qxp-lpcg             ZF             %                  9                           '  uart0_lpcg_baud_clk uart0_lpcg_ipg_clk          !      9        O         clock-controller@5a470000            2fsl,imx8qxp-lpcg             ZG             %                  :                           '  uart1_lpcg_baud_clk uart1_lpcg_ipg_clk          !      :        O         clock-controller@5a480000            2fsl,imx8qxp-lpcg             ZH             %                  ;                           '  uart2_lpcg_baud_clk uart2_lpcg_ipg_clk          !      ;        O         clock-controller@5a490000            2fsl,imx8qxp-lpcg             ZI             %                  <                           '  uart3_lpcg_baud_clk uart3_lpcg_ipg_clk          !      <        O         i2c@5a800000             Z    @                                                                           per ipg         ^      `           nn6         !      `        =okay          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c                   2default         @           O  d   accelerometer@19             2st,lsm303agr-accel                    gyrometer@20             2nxp,fxas21002c                     light-sensor@44          2isil,isl29023               D                                 pressure-sensor@60           2fsl,mpl3115             `      gpio@68          2maxim,max7322               h                            O         gyrometer@69             2st,l3g4200d-gyro                i      tcpc@51          2nxp,ptn5110 tcpci           2default         @               Q                                   =okay            O  e   connector            2usb-c-connector         USB-C           source          dual            ,        O  f   ports                                port@0                  endpoint                       O            port@1                 endpoint                       O                        i2c@5a810000             Z    @                                                                           per ipg         ^      a           nn6         !      a        =okay          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c                   2default gpio            @                                        #                  O         i2c@5a820000             Z    @                                                                           per ipg         ^      b           nn6         !      b      	  =disabled          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c          O  g      i2c@5a830000             Z    @                                                                           per ipg         ^      c           nn6         !      c      	  =disabled          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c          O  h      adc@5a880000             2nxp,imx8qxp-adc         -            Z                                                                  per ipg         ^      e           nn6         !      e        =okay            2default         @           ?           O  i      adc@5a890000             2nxp,imx8qxp-adc         -            Z                                                                  per ipg         ^      f           nn6         !      f      	  =disabled            O  j      can@5a8d0000             2fsl,imx8qm-flexcan           Z                                                                  ipg per         ^      i           nbZ         !      i        K           Z            =okay            2default         @           h           O  k      can@5a8e0000             2fsl,imx8qm-flexcan           Z                                                                  ipg per         ^      j           nbZ         !      j        K           Z           =okay            2default         @           h           O  l      can@5a8f0000             2fsl,imx8qm-flexcan           Z                                                                  ipg per         ^      k           nbZ         !      k        K           Z           =okay            2default         @           h           O  m      dma-controller@5a9f0000          2fsl,imx8qm-edma          Z   !          H           S   
      x                                                                                                  P  !      l      m      n      o      p      q      r      s      t      u        O  n      clock-controller@5ac00000            2fsl,imx8qxp-lpcg             Z             %                  `                              i2c0_lpcg_clk i2c0_lpcg_ipg_clk         !      `        O         clock-controller@5ac10000            2fsl,imx8qxp-lpcg             Z             %                  a                              i2c1_lpcg_clk i2c1_lpcg_ipg_clk         !      a        O         clock-controller@5ac20000            2fsl,imx8qxp-lpcg             Z             %                  b                              i2c2_lpcg_clk i2c2_lpcg_ipg_clk         !      b        O         clock-controller@5ac30000            2fsl,imx8qxp-lpcg             Z             %                  c                              i2c3_lpcg_clk i2c3_lpcg_ipg_clk         !      c        O         clock-controller@5ac80000            2fsl,imx8qxp-lpcg             Z             %                  e                              adc0_lpcg_clk adc0_lpcg_ipg_clk         !      e        O         clock-controller@5ac90000            2fsl,imx8qxp-lpcg             Z             %                  f                              adc1_lpcg_clk adc1_lpcg_ipg_clk         !      f        O         clock-controller@5acd0000            2fsl,imx8qxp-lpcg             Z             %                  i                                 5  can0_lpcg_pe_clk can0_lpcg_ipg_clk can0_lpcg_chi_clk            !      i        O         clock-controller@5a4a0000            2fsl,imx8qxp-lpcg             ZJ             %                  =                           '  uart4_lpcg_baud_clk uart4_lpcg_ipg_clk          !      =        O  o      i2c@5a840000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           Z    @               X                                              per ipg         ^      d           nn6         !      d      	  =disabled            O  p      clock-controller@5ac40000            2fsl,imx8qxp-lpcg             Z             %                  d                              i2c4_lpcg_clk i2c4_lpcg_ipg_clk         !      d        O         clock-controller@5ace0000            2fsl,imx8qxp-lpcg             Z             %                  j                                 5  can1_lpcg_pe_clk can1_lpcg_ipg_clk can1_lpcg_chi_clk            !      j        O         clock-controller@5acf0000            2fsl,imx8qxp-lpcg             Z             %                  k                                 5  can2_lpcg_pe_clk can2_lpcg_ipg_clk can2_lpcg_chi_clk            !      k        O            clock-conn-axi           2fixed-clock         %            CU        conn_axi_clk            O         clock-conn-ahb           2fixed-clock         %            	!        conn_ahb_clk            O         clock-conn-ipg           2fixed-clock         %                    conn_ipg_clk            O         clock-conn-bch           2fixed-clock         %            ׄ         conn_bch_clk            O  q      bus@5b000000             2simple-bus                                   [       [              O  r   usb@5b0d0000          -   2fsl,imx7ulp-usb fsl,imx6ul-usb fsl,imx27-usb             [                                           w                                                                           !           	  =disabled            O  s      usbmisc@5b0d0200                     8   2fsl,imx7ulp-usbmisc fsl,imx7d-usbmisc fsl,imx6q-usbmisc          [            O         usbphy@5b100000       %   2fsl,imx8qm-usbphy fsl,imx7ulp-usbphy             [                            !           	  =disabled            O         mmc@5b010000                               [                                         ipg ahb per         !              =okay          3   2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc                          2default         @                                                 O  t      mmc@5b020000                               [                                         ipg ahb per         !                                    =okay          3   2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc                          2default         @                      &           2                 ;                  O  u      mmc@5b030000                               [                                         ipg ahb per         !            	  =disabled          3   2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc                          O  v      ethernet@5b040000            [           0                                                                                  ipg ahb enet_clk_ref ptp            ^                          n沀sY@        D           V           !              =okay             2fsl,imx8qm-fec fsl,imx6sx-fec                           2default         @         	  hrgmii-id            q            |        O  w   mdio                                 ethernet-phy@0           2ethernet-phy-ieee802.3-c22                       O         ethernet-phy@1           2ethernet-phy-ieee802.3-c22                      O               ethernet@5b050000            [           0                                                                                 ipg ahb enet_clk_ref ptp            ^                          n沀sY@        D           V           !              =okay             2fsl,imx8qm-fec fsl,imx6sx-fec                           2default         @           hrgmii-txid          q                                 mac-address                    |        O  x      usb@5b110000             2fsl,imx8qm-usb3          [                                             (                                          lpm bus aclk ipg core           ^                n沀        !             =okay            O  y   usb@5b120000          
   2cdns,usb3            [     [     [             otg xhci dev                       0                                              host peripheral otg wakeup                     cdns3,usb3-phy                     =okay            
otg                  O  z   port       endpoint                       O                  usb-phy@5b160000             2nxp,salvo-phy            [                            salvo_phy_clk           !             "            =okay            O         clock-controller@5b200000            2fsl,imx8qxp-lpcg             [              %                                                   9  sdhc0_lpcg_per_clk sdhc0_lpcg_ipg_clk sdhc0_lpcg_ahb_clk            !              O         clock-controller@5b210000            2fsl,imx8qxp-lpcg             [!             %                                                   9  sdhc1_lpcg_per_clk sdhc1_lpcg_ipg_clk sdhc1_lpcg_ahb_clk            !              O         clock-controller@5b220000            2fsl,imx8qxp-lpcg             ["             %                                                   9  sdhc2_lpcg_per_clk sdhc2_lpcg_ipg_clk sdhc2_lpcg_ahb_clk            !              O         clock-controller@5b230000            2fsl,imx8qxp-lpcg             [#             %         0                                                                          enet0_lpcg_timer_clk enet0_lpcg_txc_sampling_clk enet0_lpcg_ahb_clk enet0_lpcg_rgmii_txc_clk enet0_lpcg_ipg_clk enet0_lpcg_ipg_s_clk            !              O         clock-controller@5b240000            2fsl,imx8qxp-lpcg             [$             %         0                                                                          enet1_lpcg_timer_clk enet1_lpcg_txc_sampling_clk enet1_lpcg_ahb_clk enet1_lpcg_rgmii_txc_clk enet1_lpcg_ipg_clk enet1_lpcg_ipg_s_clk            !              O         clock-controller@5b270000            2fsl,imx8qxp-lpcg             ['             %                                      "  usboh3_ahb_clk usboh3_phy_ipg_clk           !             O         clock-controller@5b280000            2fsl,imx8qxp-lpcg             [(             %                                    0                                          M  usb3_app_clk usb3_lpm_clk usb3_ipg_clk usb3_core_pclk usb3_phy_clk usb3_aclk            !             O         clock-controller@5b290000            2fsl,imx8qxp-lpcg             [)             %                  	        	                                    '  gpmi_bch gpmi_io gpmi_apb gpmi_bch_apb          !     	        O         clock-controller@5b290004            2fsl,imx8qxp-lpcg             [)            %                                  apbhdma_hclk            !     	        O         dma-controller@5b810000       (   2fsl,imx8qxp-dma-apbh fsl,imx28-dma-apbh          [            0                                              H           S                           !     	        O         nand-controller@5b812000             2fsl,imx8qxp-gpmi-nand            [      [@             gpmi-nand bch                                                      bch                                          '  gpmi_io gpmi_apb gpmi_bch gpmi_bch_apb                         rx-tx           !     	        ^     	           n      	  =disabled            O  {         clock-lsio-bus           2fixed-clock         %                     lsio_bus_clk            O         bus@5d000000             2simple-bus                                    ]       ]                           O  |   pwm@5d000000             2fsl,imx27-pwm            ]              ipg per                              ^                 nn6                           ^         	  =disabled            O  }      pwm@5d010000             2fsl,imx27-pwm            ]             ipg per                              ^                 nn6                           _         	  =disabled            O  ~      pwm@5d020000             2fsl,imx27-pwm            ]             ipg per                              ^                 nn6                           `         	  =disabled            O        pwm@5d030000             2fsl,imx27-pwm            ]             ipg per                              ^                 nn6                           a         	  =disabled            O        gpio@5d080000            ]                                                                       !               2fsl,imx8qm-gpio fsl,imx35-gpio        0  -                                   $           O         gpio@5d090000            ]	                                                                       !               2fsl,imx8qm-gpio fsl,imx35-gpio        @  -          (            2            ?            H           O         gpio@5d0a0000            ]
                                                                       !               2fsl,imx8qm-gpio fsl,imx35-gpio        0  -          P            U            h   
        O        gpio@5d0b0000            ]                                                                       !               2fsl,imx8qm-gpio fsl,imx35-gpio          -          r            u                                                                                                                                   O         gpio@5d0c0000            ]                                                                       !               2fsl,imx8qm-gpio fsl,imx35-gpio        `  -                                                                                 O         gpio@5d0d0000            ]                                                                       !               2fsl,imx8qm-gpio fsl,imx35-gpio          -                                                                                                         O         gpio@5d0e0000            ]                                                                       !               2fsl,imx8qm-gpio fsl,imx35-gpio           -             
      
              O        gpio@5d0f0000            ]                                                                       !               2fsl,imx8qm-gpio fsl,imx35-gpio          O        spi@5d120000                                       2nxp,imx8qxp-fspi             ]                   fspi_base fspi_mmap                \                                      fspi_en fspi            !              =okay            2default         @           O     flash@0                                                2jedec,spi-nor           9k@        K           \           O           mailbox@5d1b0000             ]                                        	  =disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu         O        mailbox@5d1c0000             ]                                        ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu         O         mailbox@5d1d0000             ]                                        	  =disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu         O        mailbox@5d1e0000             ]                                        	  =disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu         O        mailbox@5d1f0000             ]                                        	  =disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu         O        mailbox@5d200000             ]                                           !              =okay             2fsl,imx8qm-mu fsl,imx6sx-mu         O         mailbox@5d210000             ]!                                          !              =okay             2fsl,imx8qm-mu fsl,imx6sx-mu         O        mailbox@5d280000             ](                                          !               2fsl,imx8qm-mu fsl,imx6sx-mu         O         clock-controller@5d400000            2fsl,imx8qxp-lpcg             ]@             %         4                                                                        h  pwm0_lpcg_ipg_clk pwm0_lpcg_ipg_hf_clk pwm0_lpcg_ipg_s_clk pwm0_lpcg_ipg_slv_clk pwm0_lpcg_ipg_mstr_clk         !              O         clock-controller@5d410000            2fsl,imx8qxp-lpcg             ]A             %         4                                                                        h  pwm1_lpcg_ipg_clk pwm1_lpcg_ipg_hf_clk pwm1_lpcg_ipg_s_clk pwm1_lpcg_ipg_slv_clk pwm1_lpcg_ipg_mstr_clk         !              O         clock-controller@5d420000            2fsl,imx8qxp-lpcg             ]B             %         4                                                                        h  pwm2_lpcg_ipg_clk pwm2_lpcg_ipg_hf_clk pwm2_lpcg_ipg_s_clk pwm2_lpcg_ipg_slv_clk pwm2_lpcg_ipg_mstr_clk         !              O         clock-controller@5d430000            2fsl,imx8qxp-lpcg             ]C             %         4                                                                        h  pwm3_lpcg_ipg_clk pwm3_lpcg_ipg_hf_clk pwm3_lpcg_ipg_s_clk pwm3_lpcg_ipg_slv_clk pwm3_lpcg_ipg_mstr_clk         !              O         clock-controller@5d440000            2fsl,imx8qxp-lpcg             ]D             %         4                                                                        h  pwm4_lpcg_ipg_clk pwm4_lpcg_ipg_hf_clk pwm4_lpcg_ipg_s_clk pwm4_lpcg_ipg_slv_clk pwm4_lpcg_ipg_mstr_clk         !              O        clock-controller@5d450000            2fsl,imx8qxp-lpcg             ]E             %         4                                                                        h  pwm5_lpcg_ipg_clk pwm5_lpcg_ipg_hf_clk pwm5_lpcg_ipg_s_clk pwm5_lpcg_ipg_slv_clk pwm5_lpcg_ipg_mstr_clk         !              O        clock-controller@5d460000            2fsl,imx8qxp-lpcg             ]F             %         4                                                                        h  pwm6_lpcg_ipg_clk pwm6_lpcg_ipg_hf_clk pwm6_lpcg_ipg_s_clk pwm6_lpcg_ipg_slv_clk pwm6_lpcg_ipg_mstr_clk         !              O        clock-controller@5d470000            2fsl,imx8qxp-lpcg             ]G             %         4                                                                        h  pwm7_lpcg_ipg_clk pwm7_lpcg_ipg_hf_clk pwm7_lpcg_ipg_s_clk pwm7_lpcg_ipg_slv_clk pwm7_lpcg_ipg_mstr_clk         !              O           clock-hsio-axi           2fixed-clock         %            ׄ         hsio_axi_clk            O         clock-hsio-per           2fixed-clock         %            U        hsio_per_clk            O         clock-hsio-refa          2gpio-gate-clock                     %            m                 O         clock-hsio-refb          2gpio-gate-clock                     %            m                 O        clock-xtal100m           2fixed-clock         %                     xtal_100MHz         O         bus@5f000000             2simple-bus        0  _       _      @       `             p                                       z                     O     pcie@5f010000            2fsl,imx8q-pcie           _                  dbi config        0                                                                   f          h           msi dma                                                             dbi mstr slv                            pci                                  i                            j                            k                            l                                                        !                       	  =disabled                              	  pcie-phy            @           2default                           O        pcie-ep@5f010000             2fsl,imx8q-pcie-ep            _                   dbi addr_space                            h           dma                                    dbi mstr slv            !                                             	  =disabled            O        clock-controller@5f060000            2fsl,imx8qxp-lpcg             _                               %                          F  hsio_pcieb_mstr_axi_clk hsio_pcieb_slv_axi_clk hsio_pcieb_dbi_axi_clk           !              O         clock-controller@5f0b0000            2fsl,imx8qxp-lpcg             _                         %                      hsio_phyx1_per_clk          !              O         clock-controller@5f0d0000            2fsl,imx8qxp-lpcg             _                         %                      hsio_pcieb_per_clk          !              O         clock-controller@5f0f0000            2fsl,imx8qxp-lpcg             _                         %                      hsio_misc_per_clk           !              O         pcie@5f000000            2fsl,imx8q-pcie           _      O             dbi config        0             O                @   @                                   F           msi                                                             dbi mstr slv                            pci                                  I                            J                            K                            L                                                        !                         =okay                                	  pcie-phy            @           2default                                     O        pcie-ep@5f000000             2fsl,imx8q-pcie-ep            _      @              dbi addr_space                            H           dma                                    dbi mstr slv            !                                             	  =disabled            O        sata@5f020000            2fsl,imx8qm-ahci          _                    X                                sata sata_ref           sata-phy cali-phy0 cali-phy1            !            0                                                 =okay            O        clock-controller@5f050000            2fsl,imx8qxp-lpcg             _                               %                          F  hsio_pciea_mstr_axi_clk hsio_pciea_slv_axi_clk hsio_pciea_dbi_axi_clk           !              O         clock-controller@5f070000            2fsl,imx8qxp-lpcg             _                         %                      hsio_sata_clk           !              O         clock-controller@5f080000            2fsl,imx8qxp-lpcg             _                                  %                              L  hsio_phyx2_pclk_0 hsio_phyx2_pclk_1 hsio_phyx2_apbclk_0 hsio_phyx2_apbclk_1         !              O         clock-controller@5f090000            2fsl,imx8qxp-lpcg             _	                                  %                              Q  hsio_phyx1_pclk hsio_phyx1_epcs_tx_clk hsio_phyx1_epcs_rx_clk hsio_phyx1_apb_clk            !              O         clock-controller@5f0a0000            2fsl,imx8qxp-lpcg             _
                         %                      hsio_phyx2_per_clk          !              O         clock-controller@5f0c0000            2fsl,imx8qxp-lpcg             _                         %                      hsio_pciea_per_clk          !              O         clock-controller@5f0e0000            2fsl,imx8qxp-lpcg             _                         %                      hsio_sata_per_clk           !              O         phy@5f180000             2fsl,imx8qm-hsio           _     _     _     _             reg phy ctrl misc         p                                                                                               v  pclk0 pclk1 apb_pclk0 apb_pclk1 pclk2 epcs_tx epcs_rx apb_pclk2 phy0_crr phy1_crr ctl0_crr ctl1_crr ctl2_crr misc_crr           "           !                    =okay            pciea-pcieb-sata            input           O            chosen          1/bus@5a000000/serial@5a060000         memory@80000000          memory                      @         clock-xtal24m            2fixed-clock         %            n6         xtal_24MHz          O        reserved-memory                                      memory@90000000                                 =        O        memory@90008000                                =        O        memory@90010000                                =        O        memory@90018000                               =        O        memory@900ff000                               =        O        memory@90100000                                =        O        memory@90108000                               =        O  	      memory@90110000                                =        O  
      memory@90118000                               =        O        memory@901ff000                               =        O        memory@90400000          2shared-dma-pool              @                  =        O        memory@92400000              @                  =        O         memory@942f0000              /                  =        O         memory@942f8000              /                 =        O         memory@94300000          2shared-dma-pool              0                  =        O         linux,cma            2shared-dma-pool         D           <                <            Q         c         backlight-lvds0          2pwm-backlight           l                    q       d           d           P        O        backlight-lvds1          2pwm-backlight           l                    q       d           d           P        O        i2c-mux          2i2c-mux-gpio                                                              i2c@0                                             audio-codec@1a           2wlf,wm8960                                      mclk          ,  ^     E        E         E                  n.                                                                              	
           	           	&           O            i2c@1                                            wm8962@1a            2wlf,wm8962                                    ,  ^     E        E         E                  n.                	
                                 	5           	B           	P           	           	&           O               mux-controller           2nxp,cbdtu02043 gpio-sbu-mux         2default         @           	^                  m                  	k   port       endpoint                       O               regulator-1v5            2regulator-fixed         	~1v5         	 `        	 `        O        regulator-1v8            2regulator-fixed         	~1v8         	 w@        	 w@        O        regulator-2v8            2regulator-fixed         	~2v8         	 *        	 *        O        usdhc2-vmmc          2regulator-fixed       	  	~SD1_SPWR            	 -        	 -                           	        	          O         regulator-audio          2regulator-fixed         	~cs42888_supply          	 2Z        	 2Z        O         regulator-fec2-nvcc          2regulator-fixed       
  	~fec2_nvcc           	 w@        	 w@                            	        O         regulator-can01-gen          2regulator-fixed       	  	~can01-en            	 2Z        	 2Z                           	        O         regulator-can2-gen           2regulator-fixed         	~can2-en         	 2Z        	 2Z                           	        O         regulator-can01-stby             2regulator-fixed         	~can01-stby          	 2Z        	 2Z                           	        	           O         regulator-can2-stby          2regulator-fixed       
  	~can2-stby           	 2Z        	 2Z                           	        	           O         regulator-pcie           2regulator-fixed         @           2default         	 2Z        	 2Z      
  	~mpcie_3v3                              	        O         regulator-adc-vref           2regulator-fixed       	  	~vref_1v8            	 w@        	 w@        O         regulator-audio-pwr          2regulator-fixed       	  	~audio-5v            	 LK@        	 LK@         	         	        O         regulator-audio-3v3          2regulator-fixed       
  	~audio-3v3           	 2Z        	 2Z         	         	        O         regulator-audio-1v8          2regulator-fixed       
  	~audio-1v8           	 w@        	 w@         	         	        O         audio-codec-bt           2linux,bt-sco            7           O         sound-bt-sco             2simple-audio-card           
bt-sco-audio            
(dsp_a            
A        
f           
      simple-audio-card,cpu           
           
           
           O         simple-audio-card,codec         
               sound-cs42888            2fsl,imx-audio-cs42888            ,imx-cs42888         
           
           
           
Line Out Jack AOUT1L Line Out Jack AOUT1R Line Out Jack AOUT2L Line Out Jack AOUT2R Line Out Jack AOUT3L Line Out Jack AOUT3R Line Out Jack AOUT4L Line Out Jack AOUT4R AIN1L Line In Jack AIN1R Line In Jack AIN2L Line In Jack AIN2R Line In Jack       sound-wm8960             2fsl,imx-audio-wm8960             ,wm8960-audio            
           
                             
Headphone Jack HP_L Headphone Jack HP_R Ext Spk SPK_LP Ext Spk SPK_LN Ext Spk SPK_RP Ext Spk SPK_RN LINPUT1 Mic Jack Mic Jack MICB        sound-wm8962             2fsl,imx-audio-wm8962             ,wm8962-audio            
           
                           m  
Headphone Jack HPOUTL Headphone Jack HPOUTR Ext Spk SPKOUTL Ext Spk SPKOUTR AMIC MICBIAS IN1R AMIC IN3R AMIC          imx8qm-cm4-0             2fsl,imx8qm-cm4                      tx rx rxdb        $  
                                    D                    !          )                  !4        imx8qm-cm4-1             2fsl,imx8qm-cm4                      tx rx rxdb        $  
                                 D      	  
            !     *     =          *        !8        __symbols__         3/cpus/cpu@0         9/cpus/cpu@1         ?/cpus/cpu@2         E/cpus/cpu@3         K/cpus/l2-cache0         R/cpus/l2-cache1         Y/opp-table-0            g/opp-table-1            u/interrupt-controller@51a00000          y/iommu@51400000       $  ~/system-controller/power-controller       $  /system-controller/clock-controller         /system-controller/pinctrl        "  /system-controller/pinctrl/hoggrp         ,  /system-controller/pinctrl/cs42888_resetgrp       ,  /system-controller/pinctrl/i2c-mipi-csi0grp       ,  /system-controller/pinctrl/i2c-mipi-csi1grp       #  /system-controller/pinctrl/i2c0grp        #  /system-controller/pinctrl/i2c1grp        (  /system-controller/pinctrl/i2c1gpio-grp       #  /system-controller/pinctrl/adc0grp        &  /system-controller/pinctrl/cm41i2cgrp         $   /system-controller/pinctrl/esai0grp       #  ./system-controller/pinctrl/fec1grp        %  ;/system-controller/pinctrl/lpspi2grp          '  J/system-controller/pinctrl/lpspi2csgrp        +  \/system-controller/pinctrl/mipi0_lpi2c0grp        +  q/system-controller/pinctrl/mipi1_lpi2c0grp        '  /system-controller/pinctrl/flexspi0grp        #  /system-controller/pinctrl/fec2grp        '  /system-controller/pinctrl/flexcan0grp        '  /system-controller/pinctrl/flexcan1grp        '  /system-controller/pinctrl/flexcan3grp        &  /system-controller/pinctrl/lpuart0grp         &  /system-controller/pinctrl/lpuart2grp         &  /system-controller/pinctrl/lpuart3grp         *  /system-controller/pinctrl/lvds0lpi2c1grp         *  /system-controller/pinctrl/lvds1lpi2c1grp         (  1/system-controller/pinctrl/mipi-csi0grp       (  C/system-controller/pinctrl/mipi-csi1grp       $  U/system-controller/pinctrl/pcieagrp       '  c/system-controller/pinctrl/pcieareggrp        $  u/system-controller/pinctrl/pciebgrp       '  /system-controller/pinctrl/pwmlvds0grp        '  /system-controller/pinctrl/pwmlvds1grp        #  /system-controller/pinctrl/sai0grp        #  /system-controller/pinctrl/sai1grp        $  /system-controller/pinctrl/typecgrp       '  /system-controller/pinctrl/typecmuxgrp        %  /system-controller/pinctrl/usdhc1grp          %  /system-controller/pinctrl/usdhc2grp          $  /system-controller/reset-controller         	/system-controller/rtc          /system-controller/ocotp          !  /system-controller/ocotp/mac@1c4          !  /system-controller/ocotp/mac@1c6          "  %/system-controller/thermal-sensor         (  +/thermal-zones/cpu0-thermal/trips/trip0       (  6/thermal-zones/cpu0-thermal/trips/trip1       (  @/thermal-zones/gpu0-thermal/trips/trip0       (  K/thermal-zones/gpu0-thermal/trips/trip1       (  U/thermal-zones/gpu1-thermal/trips/trip0       (  `/thermal-zones/gpu1-thermal/trips/trip1       (  j/thermal-zones/drc0-thermal/trips/trip0       (  u/thermal-zones/drc0-thermal/trips/trip1         /clock-dummy            /clock-esai1-rx         /clock-esai1-rx-hf          /clock-esai1-tx         /clock-esai1-tx-hf          /clock-hdmi-rx-mclk         /clock-mlb-clk          /clock-sai5-rx-bclk         /clock-sai5-tx-bclk         /clock-sai6-rx-bclk         #/clock-sai6-tx-bclk         4/clock-spdif1-rx            B/clock-controller-lvds-ipg          O/clock-controller-dsi-ipg            [/clock-controller-mipi-div2-pll         m/bus@55000000           |/bus@55000000/dsp@556e8000          /bus@31400000           /bus@31400000/crypto@31400000         '  /bus@31400000/crypto@31400000/jr@30000        '  /bus@31400000/crypto@31400000/jr@40000          /clock-cm41-ipg         /bus@38000000           /bus@38000000/i2c@3b230000        #  /bus@38000000/i2c@3b230000/gpio@20        *  /bus@38000000/i2c@3b230000/audio-codec@48           /bus@38000000/intmux@3b400000         (  /bus@38000000/clock-controller@3b630000         /clock-audio-ipg            /clock-ext-aud-mclk0            /clock-ext-aud-mclk1             /clock-esai0-rx         1/clock-esai0-rx-hf          E/clock-esai0-tx         V/clock-esai0-tx-hf          j/clock-spdif0-rx            x/clock-sai0-rx-bclk         /clock-sai0-tx-bclk         /clock-sai1-rx-bclk         /clock-sai1-tx-bclk         /clock-sai2-rx-bclk         /clock-sai3-rx-bclk         /clock-sai4-rx-bclk         /bus@59000000           /bus@59000000/asrc@59000000         (/bus@59000000/esai@59010000         /bus@59000000/spdif@59020000            )/bus@59000000/sai@59040000          /bus@59000000/sai@59050000          	/bus@59000000/sai@59060000          /bus@59000000/sai@59070000        &  /bus@59000000/dma-controller@591f0000         (  /bus@59000000/clock-controller@59400000       (  $/bus@59000000/clock-controller@59410000       (  //bus@59000000/clock-controller@59420000       (  %/bus@59000000/clock-controller@59440000       (  ;/bus@59000000/clock-controller@59450000       (  E/bus@59000000/clock-controller@59460000       (  O/bus@59000000/clock-controller@59470000       (  Y/bus@59000000/clock-controller@59580000       (  b/bus@59000000/clock-controller@59590000         o/bus@59000000/asrc@59800000         u/bus@59000000/sai@59820000          z/bus@59000000/sai@59830000          /bus@59000000/amix@59840000         /bus@59000000/mqs@59850000        &  /bus@59000000/dma-controller@599f0000         (  /bus@59000000/clock-controller@59d00000       (  /bus@59000000/clock-controller@59d10000       (  /bus@59000000/clock-controller@59d20000       (  /bus@59000000/clock-controller@59d30000       (  /bus@59000000/clock-controller@59d50000       (  /bus@59000000/clock-controller@59d60000         /bus@59000000/acm@59e00000        (  /bus@59000000/clock-controller@59c00000       (  /bus@59000000/clock-controller@59c20000       (  /bus@59000000/clock-controller@59c30000       (  /bus@59000000/clock-controller@59c40000       (  /bus@59000000/clock-controller@59c50000         !/bus@59000000/sai@59080000          &/bus@59000000/sai@59090000        (  +/bus@59000000/clock-controller@59480000       (  5/bus@59000000/clock-controller@59490000         ?/bus@59000000/esai@59810000       (  E/bus@59000000/clock-controller@59c10000         P/vpu@2c000000           T/vpu@2c000000/mailbox@2d000000          Z/vpu@2c000000/mailbox@2d020000          a/vpu@2c000000/mailbox@2d040000           h/vpu@2c000000/vpu-core@2d080000          r/vpu@2c000000/vpu-core@2d090000          |/vpu@2c000000/vpu-core@2d0a0000         /bus@53000000           /bus@53000000/gpu@53100000          /bus@56220000         ,  /bus@56220000/interrupt-controller@56220000       (  /bus@56220000/clock-controller@56223000       (  /bus@56220000/clock-controller@5622300c       (  /bus@56220000/clock-controller@56223014       (  /bus@56220000/clock-controller@56223018       (  /bus@56220000/clock-controller@5622301c       (  /bus@56220000/clock-controller@56223024       (  2/bus@56220000/clock-controller@56223028       (  L/bus@56220000/clock-controller@5622302c         `/bus@56220000/pwm@56224000          j/bus@56220000/i2c@56226000          u/bus@56240000         (  /bus@56240000/clock-controller@56243000       (  /bus@56240000/clock-controller@56243000       (  /bus@56240000/clock-controller@5624300c       (  /bus@56240000/clock-controller@5624300c       (  /bus@56240000/clock-controller@56243010       (  /bus@56240000/clock-controller@56243010         /bus@56240000/pwm@56244000           /bus@56240000/pwm@56244000          /bus@56240000/i2c@56246000          !/bus@56240000/i2c@56246000        ,  5/bus@56240000/interrupt-controller@56240000       (  D/bus@56240000/clock-controller@56243014         T/bus@56240000/i2c@56247000          _/bus@57220000         ,  l/bus@57220000/interrupt-controller@57220000       (  /bus@57220000/clock-controller@57223000       (  /bus@57220000/clock-controller@5722300c       (  {/bus@57220000/clock-controller@5722301c       (  /bus@57220000/clock-controller@57223014       (  /bus@57220000/clock-controller@57223018       (  /bus@57220000/clock-controller@57223024       (  /bus@57220000/clock-controller@57223028       (  /bus@57220000/clock-controller@5722302c         /bus@57220000/pwm@57224000          /bus@57220000/i2c@57226000          /bus@57240000         ,  )/bus@57240000/interrupt-controller@57240000       (  8/bus@57240000/clock-controller@57243000       (  G/bus@57240000/clock-controller@5724300c       (  V/bus@57240000/clock-controller@57243010       (  f/bus@57240000/clock-controller@57243014         /bus@57240000/pwm@57244000          v/bus@57240000/i2c@57246000          /bus@57240000/i2c@57247000          /clock-img-ipg          /clock-img-pxl          /bus@58000000           /bus@58000000/isi@58100000        1  /bus@58000000/isi@58100000/ports/port@2/endpoint          1  /bus@58000000/isi@58100000/ports/port@3/endpoint             /bus@58000000/irqsteer@58220000         /bus@58000000/gpio@58222000       (  /bus@58000000/clock-controller@58223018       (  /bus@58000000/clock-controller@5822301c         /bus@58000000/i2c@58226000           /bus@58000000/csi@58227000        1  /bus@58000000/csi@58227000/ports/port@1/endpoint             /bus@58000000/irqsteer@58240000         '/bus@58000000/gpio@58242000       (  7/bus@58000000/clock-controller@58243018       (  F/bus@58000000/clock-controller@5824301c         /bus@58000000/i2c@58246000          T/bus@58000000/csi@58247000        1  _/bus@58000000/csi@58247000/ports/port@1/endpoint             m/bus@58000000/irqsteer@58260000       (  /bus@58000000/clock-controller@58263004       (  /bus@58000000/clock-controller@58263018       (  /bus@58000000/clock-controller@5826301c         /bus@58000000/i2c@58266000          /bus@58000000/jpegdec@58400000          /bus@58000000/jpegenc@58450000        (  /bus@58000000/clock-controller@58500000       (  /bus@58000000/clock-controller@58510000       (  /bus@58000000/clock-controller@58520000       (  /bus@58000000/clock-controller@58530000       (  /bus@58000000/clock-controller@58540000       (  /bus@58000000/clock-controller@58550000       (  /bus@58000000/clock-controller@58560000       (  /bus@58000000/clock-controller@58570000       (  /bus@58000000/clock-controller@58580000       (  +/bus@58000000/clock-controller@58590000       (  9/bus@58000000/clock-controller@585a0000       (  O/bus@58000000/clock-controller@585d0000       (  a/bus@58000000/clock-controller@585f0000         s/clock-dma-ipg          /bus@5a000000           /bus@5a000000/spi@5a000000          /bus@5a000000/spi@5a010000          C/bus@5a000000/spi@5a020000          /bus@5a000000/spi@5a030000          /bus@5a000000/serial@5a060000           /bus@5a000000/serial@5a070000           /bus@5a000000/serial@5a080000           /bus@5a000000/serial@5a090000         &  /bus@5a000000/dma-controller@5a1f0000         (  /bus@5a000000/clock-controller@5a400000       (  /bus@5a000000/clock-controller@5a410000       (  /bus@5a000000/clock-controller@5a420000       (  /bus@5a000000/clock-controller@5a430000       (  /bus@5a000000/clock-controller@5a460000       (  /bus@5a000000/clock-controller@5a470000       (  /bus@5a000000/clock-controller@5a480000       (  /bus@5a000000/clock-controller@5a490000         /bus@5a000000/i2c@5a800000        #  /bus@5a000000/i2c@5a800000/gpio@68        #  	/bus@5a000000/i2c@5a800000/tcpc@51        -  /bus@5a000000/i2c@5a800000/tcpc@51/connector          C  /bus@5a000000/i2c@5a800000/tcpc@51/connector/ports/port@0/endpoint        C  &/bus@5a000000/i2c@5a800000/tcpc@51/connector/ports/port@1/endpoint          /bus@5a000000/i2c@5a810000          3/bus@5a000000/i2c@5a820000          8/bus@5a000000/i2c@5a830000          
/bus@5a000000/adc@5a880000          =/bus@5a000000/adc@5a890000          /bus@5a000000/can@5a8d0000          /bus@5a000000/can@5a8e0000          /bus@5a000000/can@5a8f0000        &  B/bus@5a000000/dma-controller@5a9f0000         (  /bus@5a000000/clock-controller@5ac00000       (  J/bus@5a000000/clock-controller@5ac10000       (  H/bus@5a000000/clock-controller@5ac20000       (  R/bus@5a000000/clock-controller@5ac30000       (  \/bus@5a000000/clock-controller@5ac80000       (  f/bus@5a000000/clock-controller@5ac90000       (  p/bus@5a000000/clock-controller@5acd0000       (  z/bus@5a000000/clock-controller@5a4a0000         /bus@5a000000/i2c@5a840000        (  /bus@5a000000/clock-controller@5ac40000       (  /bus@5a000000/clock-controller@5ace0000       (  /bus@5a000000/clock-controller@5acf0000         /clock-conn-axi         /clock-conn-ahb         /clock-conn-ipg         /clock-conn-bch         /bus@5b000000           /bus@5b000000/usb@5b0d0000          /bus@5b000000/usbmisc@5b0d0200          /bus@5b000000/usbphy@5b100000           /bus@5b000000/mmc@5b010000          /bus@5b000000/mmc@5b020000          /bus@5b000000/mmc@5b030000           6/bus@5b000000/ethernet@5b040000       4  /bus@5b000000/ethernet@5b040000/mdio/ethernet-phy@0       4  /bus@5b000000/ethernet@5b040000/mdio/ethernet-phy@1          /bus@5b000000/ethernet@5b050000         /bus@5b000000/usb@5b110000        (   /bus@5b000000/usb@5b110000/usb@5b120000       6  ./bus@5b000000/usb@5b110000/usb@5b120000/port/endpoint           :/bus@5b000000/usb-phy@5b160000        (  C/bus@5b000000/clock-controller@5b200000       (  N/bus@5b000000/clock-controller@5b210000       (  Y/bus@5b000000/clock-controller@5b220000       (  d/bus@5b000000/clock-controller@5b230000       (  o/bus@5b000000/clock-controller@5b240000       (  z/bus@5b000000/clock-controller@5b270000       (  /bus@5b000000/clock-controller@5b280000       (  /bus@5b000000/clock-controller@5b290000       (  /bus@5b000000/clock-controller@5b290004       &  /bus@5b000000/dma-controller@5b810000         '  /bus@5b000000/nand-controller@5b812000          /clock-lsio-bus         /bus@5d000000           /bus@5d000000/pwm@5d000000          /bus@5d000000/pwm@5d010000          /bus@5d000000/pwm@5d020000          /bus@5d000000/pwm@5d030000          /bus@5d000000/gpio@5d080000         /bus@5d000000/gpio@5d090000         /bus@5d000000/gpio@5d0a0000         /bus@5d000000/gpio@5d0b0000         '/bus@5d000000/gpio@5d0c0000         2/bus@5d000000/gpio@5d0d0000         =/bus@5d000000/gpio@5d0e0000         H/bus@5d000000/gpio@5d0f0000         /bus@5d000000/spi@5d120000        #  S/bus@5d000000/spi@5d120000/flash@0          Z/bus@5d000000/mailbox@5d1b0000          c/bus@5d000000/mailbox@5d1c0000          l/bus@5d000000/mailbox@5d1d0000          u/bus@5d000000/mailbox@5d1e0000          ~/bus@5d000000/mailbox@5d1f0000          /bus@5d000000/mailbox@5d200000          /bus@5d000000/mailbox@5d210000          /bus@5d000000/mailbox@5d280000        (  /bus@5d000000/clock-controller@5d400000       (  /bus@5d000000/clock-controller@5d410000       (  /bus@5d000000/clock-controller@5d420000       (  /bus@5d000000/clock-controller@5d430000       (  /bus@5d000000/clock-controller@5d440000       (  /bus@5d000000/clock-controller@5d450000       (  /bus@5d000000/clock-controller@5d460000       (  /bus@5d000000/clock-controller@5d470000         /clock-hsio-axi          /clock-hsio-per         /clock-hsio-refa            /clock-hsio-refb            )/clock-xtal100m         2/bus@5f000000           >/bus@5f000000/pcie@5f010000         }/bus@5f000000/pcie@5f010000         D/bus@5f000000/pcie-ep@5f010000        (  M/bus@5f000000/clock-controller@5f060000       (  X/bus@5f000000/clock-controller@5f0b0000       (  h/bus@5f000000/clock-controller@5f0d0000       (  x/bus@5f000000/clock-controller@5f0f0000         /bus@5f000000/pcie@5f000000         ]/bus@5f000000/pcie@5f000000         /bus@5f000000/pcie-ep@5f000000          /bus@5f000000/pcie-ep@5f000000          /bus@5f000000/sata@5f020000       (  /bus@5f000000/clock-controller@5f050000       (  /bus@5f000000/clock-controller@5f070000       (  /bus@5f000000/clock-controller@5f080000       (  /bus@5f000000/clock-controller@5f090000       (  /bus@5f000000/clock-controller@5f0a0000       (  /bus@5f000000/clock-controller@5f0c0000       (  /bus@5f000000/clock-controller@5f0e0000         /bus@5f000000/phy@5f180000          /clock-xtal24m        !  /reserved-memory/memory@90000000          !  /reserved-memory/memory@90008000          !  '/reserved-memory/memory@90010000          !  3/reserved-memory/memory@90018000          !  ?/reserved-memory/memory@900ff000          !  J/reserved-memory/memory@90100000          !  V/reserved-memory/memory@90108000          !  b/reserved-memory/memory@90110000          !  n/reserved-memory/memory@90118000          !  z/reserved-memory/memory@901ff000          !  /reserved-memory/memory@90400000          !  /reserved-memory/memory@92400000          !  /reserved-memory/memory@942f0000          !  /reserved-memory/memory@942f8000          !  /reserved-memory/memory@94300000            /backlight-lvds0            /backlight-lvds1            /i2c-mux/i2c@0/audio-codec@1a           /i2c-mux/i2c@1/wm8962@1a            /mux-controller/port/endpoint           /regulator-1v5          /regulator-1v8          /regulator-2v8           /usdhc2-vmmc            0/regulator-audio            :/regulator-fec2-nvcc            J/regulator-can01-gen            W/regulator-can2-gen         c/regulator-can01-stby           r/regulator-can2-stby            /regulator-pcie         /regulator-adc-vref         /regulator-audio-pwr            /regulator-audio-3v3            /regulator-audio-1v8            /audio-codec-bt       $  /sound-bt-sco/simple-audio-card,cpu          	interrupt-parent #address-cells #size-cells model compatible mmc0 mmc1 mmc2 serial0 serial1 serial2 serial3 spi0 spi1 spi2 spi3 vpu-core0 vpu-core1 vpu-core2 device_type reg clocks enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache operating-points-v2 #cooling-cells phandle cache-level cache-unified opp-shared opp-hz opp-microvolt clock-latency-ns opp-suspend #interrupt-cells interrupt-controller interrupts #global-interrupts #iommu-cells mbox-names mboxes #power-domain-cells #clock-cells pinctrl-names pinctrl-0 fsl,pins #reset-cells read-only #thermal-sensor-cells timeout-sec polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device clock-frequency clock-output-names ranges clock-names power-domains firmware-name status memory-region fsl,sec-era assigned-clocks assigned-clock-rates gpio-controller #gpio-cells VA-supply VD-supply VLS-supply VLC-supply reset-gpios clock-indices dmas dma-names fsl,asrc-rate fsl,asrc-width fsl,asrc-clk-map assigned-clock-parents #sound-dai-cells #dma-cells dma-channels dma-channel-mask fsl,sai-asynchronous dais fsl,dataline #mbox-cells fsl,channel fsl,num-irqs #pwm-cells remote-endpoint resets cs-gpios label power-role data-role source-pdos pinctrl-1 scl-gpios sda-gpios #io-channel-cells vref-supply fsl,clk-source fsl,scu-index xceiver-supply fsl,usbphy fsl,usbmisc ahb-burst-config tx-burst-size-dword rx-burst-size-dword #index-cells iommus bus-width no-sd no-sdio non-removable fsl,tuning-start-tap fsl,tuning-step vmmc-supply cd-gpios wp-gpios fsl,num-tx-queues fsl,num-rx-queues phy-mode phy-handle fsl,magic-packet phy-supply nvmem-cells nvmem-cell-names rx-internal-delay-ps reg-names interrupt-names phys phy-names cdns,on-chip-buff-size dr_mode usb-role-switch #phy-cells gpio-ranges spi-max-frequency spi-tx-bus-width spi-rx-bus-width enable-gpios dma-ranges bus-range interrupt-map interrupt-map-mask num-lanes num-viewport fsl,max-link-speed reset-gpio num-ib-windows num-ob-windows vpcie-supply fsl,hsio-cfg fsl,refclk-pad-mode stdout-path no-map alloc-ranges linux,cma-default reusable pwms brightness-levels num-interpolated-steps default-brightness-level mux-gpios i2c-parent wlf,shared-lrclk wlf,hp-cfg wlf,gpio-cfg AVDD-supply DBVDD-supply DCVDD-supply SPKVDD1-supply SPKVDD2-supply CPVDD-supply MICVDD-supply PLLVDD-supply select-gpios orientation-switch regulator-name regulator-min-microvolt regulator-max-microvolt enable-active-high off-on-delay-us vin-supply regulator-always-on regulator-boot-on simple-audio-card,name simple-audio-card,format simple-audio-card,bitclock-inversion simple-audio-card,frame-master simple-audio-card,bitclock-master sound-dai dai-tdm-slot-num dai-tdm-slot-width audio-cpu audio-codec audio-asrc audio-routing hp-det-gpios fsl,resource-id fsl,entry-address A53_0 A53_1 A53_2 A53_3 A53_L2 A72_L2 a53_opp_table a72_opp_table gic smmu pd iomuxc pinctrl_hog pinctrl_cs42888_reset pinctrl_i2c_mipi_csi0 pinctrl_i2c_mipi_csi1 pinctrl_i2c0 pinctrl_i2c1 pinctrl_i2c1_gpio pinctrl_adc0 pinctrl_cm41_i2c pinctrl_esai0 pinctrl_fec1 pinctrl_lpspi2 pinctrl_lpspi2_cs pinctrl_mipi0_lpi2c0 pinctrl_mipi1_lpi2c0 pinctrl_flexspi0 pinctrl_fec2 pinctrl_flexcan1 pinctrl_flexcan2 pinctrl_flexcan3 pinctrl_lpuart0 pinctrl_lpuart2 pinctrl_lpuart3 pinctrl_lvds0_lpi2c1 pinctrl_lvds1_lpi2c1 pinctrl_mipi_csi0 pinctrl_mipi_csi1 pinctrl_pciea pinctrl_pciea_reg pinctrl_pcieb pinctrl_pwm_lvds0 pinctrl_pwm_lvds1 pinctrl_sai0 pinctrl_sai1 pinctrl_typec pinctrl_typec_mux pinctrl_usdhc1 pinctrl_usdhc2 scu_reset rtc ocotp fec_mac0 fec_mac1 tsens cpu_alert0 cpu_crit0 gpu_alert0 gpu_crit0 gpu_alert1 gpu_crit1 drc_alert0 drc_crit0 clk_dummy clk_esai1_rx_clk clk_esai1_rx_hf_clk clk_esai1_tx_clk clk_esai1_tx_hf_clk clk_hdmi_rx_mclk clk_mlb_clk clk_sai5_rx_bclk clk_sai5_tx_bclk clk_sai6_rx_bclk clk_sai6_tx_bclk clk_spdif1_rx lvds_ipg_clk dsi_ipg_clk mipi_pll_div2_clk vpu_subsys_dsp vpu_dsp security_subsys crypto sec_jr2 sec_jr3 cm41_ipg_clk cm41_subsys pca6416 cs42888 cm41_intmux cm41_i2c_lpcg audio_ipg_clk clk_ext_aud_mclk0 clk_ext_aud_mclk1 clk_esai0_rx_clk clk_esai0_rx_hf_clk clk_esai0_tx_clk clk_esai0_tx_hf_clk clk_spdif0_rx clk_sai0_rx_bclk clk_sai0_tx_bclk clk_sai1_rx_bclk clk_sai1_tx_bclk clk_sai2_rx_bclk clk_sai3_rx_bclk clk_sai4_rx_bclk audio_subsys asrc0 spdif0 sai2 sai3 edma0 asrc0_lpcg esai0_lpcg spdif0_lpcg sai1_lpcg sai2_lpcg sai3_lpcg dsp_lpcg dsp_ram_lpcg asrc1 sai6 sai7 amix mqs edma1 aud_rec0_lpcg aud_rec1_lpcg aud_pll_div0_lpcg aud_pll_div1_lpcg mclkout0_lpcg mclkout1_lpcg acm asrc1_lpcg sai6_lpcg sai7_lpcg amix_lpcg mqs0_lpcg sai4 sai5 sai4_lpcg sai5_lpcg esai1 esai1_lpcg vpu mu_m0 mu1_m0 mu2_m0 vpu_core0 vpu_core1 vpu_core2 gpu0_subsys gpu_3d0 mipi0_subsys irqsteer_mipi0 mipi0_lis_lpcg mipi0_pwm_lpcg mipi0_i2c0_lpcg_ipg_clk mipi0_i2c0_lpcg_ipg_s_clk mipi0_i2c0_lpcg_clk mipi0_i2c1_lpcg_ipg_clk mipi0_i2c1_lpcg_ipg_s_clk mipi0_i2c1_lpcg_clk pwm_mipi0 i2c0_mipi0 lvds0_subsys qm_lvds0_lis_lpcg qxp_mipi1_lis_lpcg qm_lvds0_pwm_lpcg qxp_mipi1_pwm_lpcg qm_lvds0_i2c0_lpcg qxp_mipi1_i2c0_lpcg qm_pwm_lvds0 qxp_pwm_mipi_lvds1 qm_i2c0_lvds0 qxp_i2c0_mipi_lvds1 irqsteer_lvds0 lvds0_i2c1_lpcg i2c1_lvds0 mipi1_subsys irqsteer_mipi1 mipi1_i2c0_lpcg_clk mipi1_i2c0_lpcg_ipg_clk mipi1_i2c0_lpcg_ipg_s_clk mipi1_i2c1_lpcg_ipg_clk mipi1_i2c1_lpcg_ipg_s_clk mipi1_i2c1_lpcg_clk pwm_mipi1 i2c0_mipi1 lvds1_subsys irqsteer_lvds1 lvds1_lis_lpcg lvds1_pwm_lpcg lvds1_i2c0_lpcg lvds1_i2c1_lpcg i2c0_lvds1 i2c1_lvds1 img_ipg_clk img_pxl_clk img_subsys isi isi_in_2 isi_in_3 irqsteer_csi0 gpio0_mipi_csi0 csi0_core_lpcg csi0_esc_lpcg mipi_csi_0 mipi_csi0_out irqsteer_csi1 gpio0_mipi_csi1 csi1_core_lpcg csi1_esc_lpcg mipi_csi_1 mipi_csi1_out irqsteer_parallel pi0_ipg_lpcg pi0_pxl_lpcg pi0_misc_lpcg i2c0_parallel jpegdec jpegenc pdma0_lpcg pdma1_lpcg pdma2_lpcg pdma3_lpcg pdma4_lpcg pdma5_lpcg pdma6_lpcg pdma7_lpcg csi0_pxl_lpcg csi1_pxl_lpcg hdmi_rx_pxl_link_lpcg img_jpeg_dec_lpcg img_jpeg_enc_lpcg dma_ipg_clk dma_subsys lpspi0 lpspi1 lpspi3 lpuart1 edma2 spi0_lpcg spi1_lpcg spi2_lpcg spi3_lpcg uart0_lpcg uart1_lpcg uart2_lpcg uart3_lpcg max7322 ptn5110 usb_con1 typec_dr_sw typec_con_ss i2c2 i2c3 adc1 edma3 i2c2_lpcg i2c3_lpcg adc0_lpcg adc1_lpcg can0_lpcg uart4_lpcg i2c4 i2c4_lpcg can1_lpcg can2_lpcg conn_axi_clk conn_ahb_clk conn_ipg_clk conn_bch_clk conn_subsys usbotg1 usbmisc1 usbphy1 usdhc3 ethphy0 ethphy1 usbotg3 usbotg3_cdns3 usb3_drd_sw usb3_phy sdhc0_lpcg sdhc1_lpcg sdhc2_lpcg enet0_lpcg enet1_lpcg usb2_lpcg usb3_lpcg rawnand_0_lpcg rawnand_4_lpcg dma_apbh gpmi lsio_bus_clk lsio_subsys lsio_pwm0 lsio_pwm1 lsio_pwm2 lsio_pwm3 lsio_gpio0 lsio_gpio1 lsio_gpio2 lsio_gpio3 lsio_gpio4 lsio_gpio5 lsio_gpio6 lsio_gpio7 flash0 lsio_mu0 lsio_mu1 lsio_mu2 lsio_mu3 lsio_mu4 lsio_mu5 lsio_mu6 lsio_mu13 pwm0_lpcg pwm1_lpcg pwm2_lpcg pwm3_lpcg pwm4_lpcg pwm5_lpcg pwm6_lpcg pwm7_lpcg hsio_axi_clk hsio_per_clk hsio_refa_clk hsio_refb_clk xtal100m hsio_subsys pcie1 pcieb_ep pcieb_lpcg phyx1_crr1_lpcg pcieb_crr3_lpcg misc_crr5_lpcg pcie0 pcie0_ep pciea_ep sata pciea_lpcg sata_lpcg phyx2_lpcg phyx1_lpcg phyx2_crr0_lpcg pciea_crr2_lpcg sata_crr4_lpcg hsio_phy xtal24m vdev0vring0 vdev0vring1 vdev1vring0 vdev1vring1 rsc_table0 vdev2vring0 vdev2vring1 vdev3vring0 vdev3vring1 rsc_table1 vdevbuffer dsp_reserved dsp_vdev0vring0 dsp_vdev0vring1 dsp_vdev0buffer lvds_backlight0 lvds_backlight1 wm8960 wm8962 usb3_data_ss reg_1v5 reg_1v8 reg_2v8 reg_usdhc2_vmmc reg_audio reg_fec2_supply reg_can01_en reg_can2_en reg_can01_stby reg_can2_stby reg_pciea reg_vref_1v8 reg_audio_5v reg_audio_3v3 reg_audio_1v8 bt_sco_codec btcpu powerdown-gpios DVDD-supply DOVDD-supply bus-type data-lanes 