  +   8  (D   (            |  (                             "    amd,seattle-overdrive amd,seattle                                    +         3   7AMD Seattle (Rev.B1) Development Board (Overdrive)     clock-100000000           fixed-clock          =             J          Zadl3clk_100mhz           m         clock-375000000           fixed-clock          =             JZ         Zccpclk_375mhz         clock-333000000           fixed-clock          =             J-@         Zsataclk_333mhz           m         clock-500000000           fixed-clock          =             Je          Zpcieclk_500mhz        clock-250000000           fixed-clock          =             J沀         Zmiscclk_250mhz           m         interrupt-controller@e1101000             arm,gic-400 arm,cortex-a15-gic            u                                 +         @                                                                        	                                         m      v2m@e0080000              arm,gic-v2m-frame                                             m            timer             arm,armv8-timer       0                                 
        bus           simple-bus                       +                                                sata@e0300000             snps,dwc-ahci                0                        c                                                  sata@e0d00000            okay              snps,dwc-ahci                                        b                                                          iommu@e0200000            arm,mmu-401                                                   L         L                                  m         iommu@e0c00000            arm,mmu-401                                                  K         K                                  m         i2c@e1000000             okay              snps,designware-i2c                                       e                     i2c@e0050000             okay              snps,designware-i2c                                      T                     serial@e1010000           arm,pl011 arm,primecell                                      H                          uartclk apb_pclk          spi@e1020000             okay              arm,pl022 arm,primecell                                      J                          sspclk apb_pclk       spi@e1030000             okay              arm,pl022 arm,primecell                                      I                          sspclk apb_pclk                                 +       mmc@0             mmc-spi-slot                          1-         2    H        A            Q            `            t             gpio@e1040000         	   disabled              arm,pl061 arm,primecell                                                          g             u                              	  apb_pclk          gpio@e1050000            okay              arm,pl061 arm,primecell                                                     u                           f                     	  apb_pclk          gpio@e0020000            okay              arm,pl061 arm,primecell                                                     u                           n                     	  apb_pclk          gpio@e0030000            okay              arm,pl061 arm,primecell                                                     u                           m                     	  apb_pclk          gpio@e0080000            okay              arm,pl061 arm,primecell                                                     u                           i                     	  apb_pclk          ccp@e0100000             okay              amd,ccp-seattle-v1a                                                                                 @      B      pcie@f0000000             pci-host-ecam-generic                        +                       pci                                                                                                                                                 !                                  "                                  #                                  $                                  %                                  &                                  '                                  (                                  )                                  *                                  +                      C                                T                                  @       @                                                                 okay          iommu@e0a00000            arm,mmu-401                                                  M         M                                  m         ccn@e8000000              arm,ccn-504                                       |         kcs@e0010000             okay          	    ipmi-kcs            ipmi                                                                        ethernet@e0700000             amd,xgbe-seattle-v1a          P       p             x             $            %         `    %              H         E         Z         [         \         ]         C                                -                  =                 Q   
   
           d                    v                                                             dma_clk ptp_clk         xgmii               	                       ethernet@e0900000             amd,xgbe-seattle-v1a          P                                 $            %        `    %              H         D         U         V         W         X         B                                -                  =                 Q   
   
           d                    v                                                             dma_clk ptp_clk         xgmii               
                       iommu@e0600000            arm,mmu-401              `                                    P         P                                  m   	      iommu@e0800000            arm,mmu-401                                                  O         O                                  m   
         cpus                         +       cpu-map    cluster0       core0                    core1                       cluster1       core0                    core1                       cluster2       core0                    core1                       cluster3       core0                    core1                          cpu@0           cpu           arm,cortex-a57                       psci                          @                              
   @                   )            m         cpu@1           cpu           arm,cortex-a57                      psci                          @                              
   @                   )            m         cpu@100         cpu           arm,cortex-a57                      psci                          @                              
   @                   )            m         cpu@101         cpu           arm,cortex-a57                     psci                          @                              
   @                   )            m         cpu@200         cpu           arm,cortex-a57                      psci                          @                              
   @                   )            m         cpu@201         cpu           arm,cortex-a57                     psci                          @                              
   @                   )            m         cpu@300         cpu           arm,cortex-a57                      psci                          @                              
   @                   )            m         cpu@301         cpu           arm,cortex-a57                     psci                          @                              
   @                   )            m            l2-cache0                         @                    2        @            m         l2-cache1                         @                    2        @            m         l2-cache2                         @                    2        @            m         l2-cache3                         @                    2        @            m         l3-cache            Q                         @                     2         m         pmu           arm,cortex-a57-pmu        `                              	          
                                                    ]                              chosen          p/bus/serial@e1010000          psci              arm,psci-0.2            smc          	compatible interrupt-parent #address-cells #size-cells model #clock-cells clock-frequency clock-output-names phandle interrupt-controller #interrupt-cells reg interrupts ranges msi-controller dma-ranges clocks iommus dma-coherent status #global-interrupts #iommu-cells clock-names num-cs spi-max-frequency voltage-ranges pl022,interface pl022,com-mode pl022,rx-level-trig pl022,tx-level-trig #gpio-cells gpio-controller device_type bus-range msi-parent interrupt-map-mask interrupt-map iommu-map reg-size reg-spacing amd,per-channel-interrupt amd,speed-set amd,serdes-blwc amd,serdes-cdr-rate amd,serdes-pq-skew amd,serdes-tx-amp amd,serdes-dfe-tap-config amd,serdes-dfe-tap-enable mac-address phy-mode cpu enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets l2-cache cache-unified next-level-cache cache-level interrupt-affinity stdout-path 