    8    (            i l                             .    radxa,nio-12l mediatek,mt8395 mediatek,mt8195                                    +            7Radxa NIO 12L         	   =embedded       aliases          J/soc/dp-intf@1c015000            S/soc/dp-intf@1c113000            \/soc/mailbox@10320000            a/soc/mailbox@10330000            f/soc/hdr-engine@1c114000             m/soc/mutex@1c016000          t/soc/mutex@1c101000          {/soc/vpp-merge@1c10c000          /soc/vpp-merge@1c10d000          /soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000             /soc/i2c@11e02000            /soc/i2c@11e03000            /soc/i2c@11e04000           /soc/i2c@11e00000           
/soc/i2c@11e01000           /soc/ethernet@11021000          /soc/serial@11001100            !/soc/serial@11001200            )/soc/spi@11010000           ./soc/spi@11012000         cpus                         +       cpu@0           3cpu           arm,cortex-a55          ?            Cpsci            Q               eec3@        u  4                                    @                                 @                                                             cpu@100         3cpu           arm,cortex-a55          ?           Cpsci            Q               eec3@        u  4                                    @                                 @                                                             cpu@200         3cpu           arm,cortex-a55          ?           Cpsci            Q               eec3@        u  4                                    @                                 @                                                             cpu@300         3cpu           arm,cortex-a55          ?           Cpsci            Q               eec3@        u  4                                    @                                 @                                                             cpu@400         3cpu           arm,cortex-a78          ?           Cpsci            Q              ef        u                                       @                                 @                      	                      
                 cpu@500         3cpu           arm,cortex-a78          ?           Cpsci            Q              ef        u                                       @                                 @                      	                      
                 cpu@600         3cpu           arm,cortex-a78          ?           Cpsci            Q              ef        u                                       @                                 @                      	                      
                 cpu@700         3cpu           arm,cortex-a78          ?           Cpsci            Q              ef        u                                       @                                 @                      	                      
                 cpu-map    cluster0       core0           #         core1           #         core2           #         core3           #         core4           #         core5           #         core6           #         core7           #               idle-states         'psci       cpu-retention-l           arm,idle-state          4           K        \   2        m   _        }  D                 cpu-retention-b           arm,idle-state          4           K        \   -        m           }                   cpu-off-l             arm,idle-state          4          K        \   7        m           }  H                 cpu-off-b             arm,idle-state          4          K        \   2        m           }                      l2-cache0             cache                                    @                                                l2-cache1             cache                                    @                                          	      l3-cache              cache                                     @                                        dsu-pmu           arm,dsu-pmu                                                                fail          dmic-codec            dmic-codec                        2                 mt8195-sound                       okay              mediatek,mt8195_mt6359           7mt8395-evk          default                  ,  Headphone Headphone L Headphone Headphone R                          headphone-dai-link        
  "DL_SRC_BE      codec           ,                   fixed-factor-clock-13m            fixed-factor-clock          6            C           J           T           _clk13m             /      oscillator-26m            fixed-clock         6            e        _clk26m                   oscillator-32k            fixed-clock         6            e           _clk32k                   performance-controller@11bc10             mediatek,cpufreq-hw          ?                 0               r                    opp-table-gpu             operating-points-v2                     |   opp-390000000               >         	h      opp-410000000               p         	      opp-431000000                        	      opp-473000000               1h@         	<      opp-515000000               F         	<      opp-556000000               !#          	Ҧ      opp-598000000               #         	      opp-640000000               &%          	      opp-670000000               'c         
      opp-700000000               )'          
L      opp-730000000               +         
}      opp-760000000               -L          
`      opp-790000000               /q         
4      opp-820000000               05                opp-850000000               2         @      opp-880000000               4s          q         pmu-a55           arm,cortex-a55-pmu                                        pmu-a78           arm,cortex-a78-pmu                                        psci              arm,psci-1.0            Jsmc       timer             arm,armv8-timer                   @                                               
                        soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3                                                      ?                                          	                     ppi-partitions     interrupt-partition-0                                        interrupt-partition-1                                              syscon@10000000            mediatek,mt8195-topckgen syscon         ?                      6                    syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          ?                     6                               syscon@10003000           mediatek,mt8195-pericfg syscon          ?     0                6              H      pinctrl@10005000              mediatek,mt8195-pinctrl         ?     P                                                                                                         B  iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint                    +           7                                                                 C              audio-default-pins                pins-cmd-dat            g  F  E  G  H  I  J  K         dsi0-backlight-pins               pins-backlight-en           g  k          n         eth-default-pins               D   pins-cc         g  U  V  W  X        z         pins-mdio           g  Y  Z               pins-power          g  [   \          n      pins-rst            g  ]       pins-rxd            g  Q  R  S  T      pins-txd            g  M  N  O  P        z            eth-sleep-pins             E   pins-cc         g  U   V   W   X       pins-mdio           g  Y   Z                         pins-rxd            g  Q   R   S   T       pins-txd            g  M   N   O   P          gpio-keys-pins                pins            g  j                            i2c2-pins              j   pins-bus            g                      z                      i2c4-pins              m   pins-bus            g                                 i2c6-pins              c   pins            g                      mmc0-default-pins              M   pins-clk            g  z           f        z         pins-cmd-dat          $  g  ~  }  |  {  w  v  u  t  y           e        z                  pins-rst            g  x           e        z            mmc0-uhs-pins              N   pins-clk            g  z           f        z         pins-cmd-dat          $  g  ~  }  |  {  w  v  u  t  y           e        z                  pins-ds         g             f        z         pins-rst            g  x           e        z            mmc1-default-pins              Q   pins-clk            g  o           f        z         pins-cmd-dat            g  n  p  q  r  s           e        z                     mmc1-detect-pins               R   pins-insert         g                     mt6360-pins            d   pins-irq            g  d   e                            panel-pins                pins-rst            g  l                   pcie0-default-pins             ^   pins-bus            g                        pcie1-default-pins             a   pins-bus            g                         pwm0-pins                 pins-disp-pwm           g  a         spi1-default-pins              >   pins-bus            g                          spi2-default-pins              ?   pins-bus            g                          touch-pins                pins-touch-int          g                           pins-touch-rst          g            n         uart0-pins             9   pins-bus            g  b  c         uart1-pins             :   pins-bus            g  f  g         usb3p0-default-pins            I   pins-vbus           g  ?                  usb2p0-default-pins            Y   pins-iddig          g                          pins-vbus           g                    wifi-vreg-pins                pins-wifi-pmu-en            g  A          n      pins-wifi-vreg-en           g  C             syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            ?     `                      power-controller          !    mediatek,mt8195-power-controller                         +                          2   power-domain@8          ?                        +                                        power-domain@9          ?   	        C                    mfg alt                                 +                                         power-domain@10         ?   
                  power-domain@11         ?                     power-domain@12         ?                     power-domain@13         ?                     power-domain@14         ?                           power-domain@15         ?           C                        	      @      A      K         !      !      !      !      !      !      !      !      !      !      !      !      !      !      !      !      !      !      !           vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18                                   +                  power-domain@16         ?         8  C         "   $   "   %   "   &   "   '   "   (   "   )      D  vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5                                 +                  power-domain@17         ?           C         #      #           vppsys1 vppsys1-0 vppsys1-1                              power-domain@22         ?            C   $      $      $      $         $  wepsys-0 wepsys-1 wepsys-2 wepsys-3                              power-domain@23         ?           C   %            vdec0-0                                 +                   power-domain@24         ?           C   &            vdec1-0                              power-domain@25         ?           C   '            vdec2-0                                 power-domain@26         ?           C   (            venc0-larb                                  +                   power-domain@27         ?           C   )            venc1-larb                                  power-domain@18         ?            C         *       *      *         &  vdosys1 vdosys1-0 vdosys1-1 vdosys1-2                                   +                  power-domain@19         ?                                power-domain@20         ?                                power-domain@21         ?           C      Q        hdmi_tx                      power-domain@28         ?           C   +       +   
        img-0 img-1                                 +                  power-domain@29         ?                     power-domain@30         ?           C         +      ,           ipe ipe-0 ipe-1                                 power-domain@31         ?         (  C   -       -      -      -      -           cam-0 cam-1 cam-2 cam-3 cam-4                                   +                  power-domain@32         ?                      power-domain@33         ?   !                  power-domain@34         ?   "                           power-domain@0          ?                                 power-domain@1          ?                                power-domain@2          ?                     power-domain@3          ?                     power-domain@4          ?           C      5      7        csi_rx_top csi_rx_top1                    power-domain@5          ?           C   .           ether                     power-domain@6          ?           C      X      n        adsp adsp1                       +                             power-domain@7          ?            C      g      "      n      2        audio audio1 audio2 audio3                                        watchdog@10007000             mediatek,mt8195-wdt          0        ?     p                              7      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           ?                     6                    timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         ?    p                      	               C   /                 pwrap@10024000            mediatek,mt8195-pwrap syscon            ?    @                pwrap                                 C                   	  spi wrap            H      $        X                    pmic              mediatek,mt6359                             o                                  adc           mediatek,mt6359-auxadc                              audio-codec           mediatek,mt6359-codec                    regulators            mediatek,mt6359-regulator      buck_vs1            vs1          5          !                                      buck_vgpu11         vgpu11                    7                             *                                    buck_vmodem         vmodem                              *                            buck_vpu            vpu                   7                             *                                    buck_vcore          vcore                                                   *                                    buck_vs2            vs2          5          j                                       buck_vpa            vpa                    7          ,                 buck_vproc2         vproc2                    7          L                   *                                    buck_vproc1         vproc1                    7          L                   *                                    buck_vcore_sshub            vcore_sshub                   7                 buck_vgpu11_sshub           vgpu11_sshub                      7                 ldo_vaud18          vaud18           w@         w@                                     ldo_vsim1           vsim1                     /M`                 ldo_vibr            vibr             O         2Z           k      ldo_vrf12           vrf12                                                ldo_vusb            vusb             -         -                              J      ldo_vsram_proc2         vsram_proc2                              L                                     ldo_vio18           vio18                                                         ldo_vcamio          vcamio                                              ldo_vcn18           vcn18            w@         w@                            ldo_vfe28           vfe28            *         *           x                 ldo_vcn13           vcn13                                       ldo_vcn33_1_bt          vcn33_1_bt           *         5g                 ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g                 ldo_vaux18          vaux18           w@         w@                                     ldo_vsram_others            vsram_others             q         q                                       ldo_vefuse          vefuse                                     ldo_vxo22           vxo22            w@         !                          ldo_vrfck           vrfck            `                          ldo_vrfck_1         vrfck                     j                  ldo_vbif28          vbif28           *         *                            ldo_vio28           vio28            *         2Z                          ldo_vemc            vemc             ,@          2Z                 ldo_vemc_1          vemc             &%         2Z           O      ldo_vcn33_2_bt          vcn33_2_bt           2Z         2Z                 ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g                 ldo_va12            va12             O                                    ldo_va09            va09             5          O                 ldo_vrf18           vrf18                     P                 ldo_vsram_md          	  vsram_md                                 *                                     ldo_vufs            vufs                                 P      ldo_vm18            vm18                                                ldo_vbbck           vbbck                     O                          ldo_vsram_proc1         vsram_proc1                              L                                    ldo_vsim2           vsim2                     /M`                ldo_vsram_others_sshub          vsram_others_sshub                                        rtc           mediatek,mt6358-rtc                 keys              mediatek,mt6359-keys            B           [                 power-key           n   t         }      home            n   f               spmi@10027000             mediatek,mt8195-spmi             ?    p                            pmif spmimst            C                   E      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         H      $        X                           +                 pmic@6            mediatek,mt6315-regulator           ?                    regulators     vbuck1          Vbcpu                     7                   *                              
            pmic@7            mediatek,mt6315-regulator           ?                    regulators     vbuck1          Vgpu                      7                   *                                    infra-iommu@10315000              mediatek,mt8195-iommu-infra         ?    1P       P       P                                                                                         [      mailbox@10320000              mediatek,mt8195-gce         ?    2        @                                          C                       mailbox@10330000              mediatek,mt8195-gce         ?    3        @                                          C                 }      scp@10500000              mediatek,mt8195-scp       0  ?    P             r             p                 sram cfg l1tcm                               okay               0        mediatek/mt8195/scp.img            ~      clock-controller@10720000             mediatek,mt8195-scp_adsp            ?    r                 6              1      dsp@10803000              mediatek,mt8195-dsp          ?    0                           	  cfg sram          ,  C      X         n         1          #      K  adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             2           rx tx              3   4        okay               5   6                 mailbox@10816000              mediatek,mt8195-adsp-mbox                       ?    `                                        3      mailbox@10817000              mediatek,mt8195-adsp-mbox                       ?    p                                        4      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           ?                                   2                 6                  7         	  audiosys            C                                                   g      "      #      n      e      a      b      c      d      2   1            clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp          okay               8                 serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                           C               	  baud bus            okay               9        default           	      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                           C               	  baud bus            okay               :        default           
      serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                           C               	  baud bus          	  disabled                    serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                          C               	  baud bus          	  disabled                    serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                          C               	  baud bus          	  disabled                    serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                                          C               	  baud bus          	  disabled                    auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           ?                      C              main                     	  disabled                    syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           ?     0                6              .      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                           C                          parent-clk sel-clk spi-clk        	  disabled                    thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         ?                                           C                                ;   <      $  lvts-calib-data-1 lvts-calib-data-2         "                    svs@1100bc00              mediatek,mt8195-svs         ?                                           C              main               =   ;      (  svs-calibration-data t-calibration-data                       svs_rst                 pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           ?                                              2           8           C      *      0        main mm       	  disabled                     pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           ?                                          8           C      +      N        main mm       	  disabled                    spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                           C                  3        parent-clk sel-clk spi-clk          okay               >        default         C                    spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                           C                  4        parent-clk sel-clk spi-clk          okay               ?        default         C                    spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?    0                                      C                  5        parent-clk sel-clk spi-clk        	  disabled                    spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                          C                  <        parent-clk sel-clk spi-clk        	  disabled                    spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                                          C                  =        parent-clk sel-clk spi-clk        	  disabled                    spi@1101d000              mediatek,mt8195-spi-slave           ?                                          C      R        spi         H              X            	  disabled                    spi@1101e000              mediatek,mt8195-spi-slave           ?                                          C      S        spi         H              X            	  disabled                    ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           ?           @                              Wmacirq        .  axi apb mac_main ptp_ref rmii_internal mac_cg         0  C   .       .         R      S      T   .           H      R      S      T        X                             2           g           x   @           A           B                                          okay            rgmii-rxid             C        default sleep              D           E                                 ]            %      N               mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916            ?              C         stmmac-axi-config           :           J           Z                                    @      rx-queues-config            d            z           A   queue0                             queue1                             queue2                             queue3                                tx-queues-config                                   B   queue0                                        queue1                                       queue2                                       queue3                                             usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           ?            -     >              	  mac ippc                                 ?                      +                                 C      /            B        sys_ck ref_ck mcu_ck               F      G            }           H      g        okay            default            I        	host             	-        	=   J             usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          ?                       mac                               H      ,      -        X                  $  C      /                     B      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         okay            	K   K                port       endpoint            	W   L           g            mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          ?    #                                                    C                          source hclk source_cg           okay            default state_uhs              M           N        	g           	q         	 L         	         	         	         	         	         	         	        	   O        	   P                mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          ?    $                                                    C                  $        source hclk source_cg           H              X              okay            default state_uhs              Q   R           Q        	g           	q          
        
                  
         	         
%         
2        	   S        	   T                mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          ?    %                                                    C                   I        source hclk source_cg           H               X            	  disabled                    ufshci@11270000           mediatek,mt8195-ufshci          ?    '        #                                  U      @  C      ?      @      A      6      7      8      Z      ]      X  ufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  
@                                                                         
N        okay            
g   O        
r   P                 thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            ?    '                                      C                               ;   <      $  lvts-calib-data-1 lvts-calib-data-2         "                    usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           ?    )             )>              	  mac ippc                                    V           H      .      /        X                  $  C   .                     .         $  sys_ck ref_ck mcu_ck dma_ck xhci_ck            H      h         }        okay             
        	=   J        	K   W        
             !      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           ?    *       -    *>              	  mac ippc                        *        ?                      +                                H      0        X              C   .            .           sys_ck ref_ck mcu_ck               X            }           H      i        okay            default            Y        	=   J          "   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          ?                       mac                              H      1        X              C   .           sys_ck          okay            	K   W          #         usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           ?    +       -    +>              	  mac ippc                        +        ?                      +                                H      2        X              C   .            .   	        sys_ck ref_ck mcu_ck               Z            }           H      j      	  disabled              $   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          ?                       mac                              H      3        X              C   .   	        sys_ck        	  disabled              %         pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           3pci                      +           ?    /        @       	  pcie-mac                                 
             8                                                              
       [              
          0  C      V      #      &      +      K   .         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          H      G        X                 \      	  
pcie-phy               2                       
                     `  
                  ]                      ]                     ]                     ]           okay            default            ^          &   interrupt-controller                                                ]         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           3pci                      +           ?    /       @       	  pcie-mac                                 
             8         $       $                  $       $                 
       [              
          (  C      W         X         Q   .         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          H      H        X                 _         	  
pcie-phy               2                      
                     `  
                  `                      `                     `                     `           okay            default            a          '   interrupt-controller                                                `         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         ?    2                      9               C      o   .      .           spi sf axi                       +          	  disabled              (      efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            ?                                  +             )   usb3-tx-imp@184,1           ?             
                  s      usb3-rx-imp@184,2           ?             
                 r      usb3-intr@185           ?             
                 q      usb3-tx-imp@186,1           ?             
                  p      usb3-rx-imp@186,2           ?             
                 o      usb3-intr@187           ?             
                 n      usb2-intr-p0@188,1          ?             
                 *      usb2-intr-p1@188,2          ?             
                +      usb2-intr-p2@189,1          ?             
                ,      usb2-intr-p3@189,2          ?             
                -      pciephy-rx-ln1@190,1            ?             
                  z      pciephy-tx-ln1-nmos@190,2           ?             
                 y      pciephy-tx-ln1-pmos@191,1           ?             
                  x      pciephy-rx-ln0@191,2            ?             
                 w      pciephy-tx-ln0-nmos@192,1           ?             
                  v      pciephy-tx-ln0-pmos@192,2           ?             
                 u      pciephy-glb-intr@193            ?             
                  t      dp-data@1ac         ?                      lvts1-calib@1bc         ?                ;      lvts2-calib@1d0         ?     8           <      svs-calib@580           ?     d           =      socinfo-data1@7a0           ?              t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay              .   usb-phy@0           ?               C              ref         
              X         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                              	  disabled              /   usb-phy@0           ?               C              ref         
              Z         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         ?                     C           _mipi_tx0_pll            6            
          	  disabled                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         ?                     C           _mipi_tx1_pll            6            
          	  disabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                 "                                     J           C   b          ;      	  main dma                         +          	  disabled              0      i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                "                                      J           C   b         ;      	  main dma                         +            okay            e            c        default           1   pmic@34           mediatek,mt6360         ?   4              e           WIRQB                                   d          2   charger           mediatek,mt6360-chg          @   usb-otg-vbus-regulator          usb-otg-vbus             C(         X           K         regulator             mediatek,mt6360-regulator              e        ,   f   buck1         	  emi_vdd2                               *                             3      buck2         	  emi_vddq                               *                              f      ldo1            ext_lcd_3v3          2Z         2Z        *                          4      ldo2            panel1_p1v8          w@         w@        *                 5      ldo3            vmc_pmu          O         6        *                  T      ldo5          	  vmch_pmu             2Z         2Z        *                           S      ldo6            mt6360_ldo6                              *                 6      ldo7            emi_vmddr_en                                 *                          7         typec             mediatek,mt6360-tcpc                  d           WPD_IRQB    connector             usb-c-connector         <USB-C           Bdual            L         ^dual            isink            x"d        ",   ports                        +       port@0          ?       endpoint            	W   g           L         port@2          ?      endpoint            	W   h           l                        i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                 "                                     J           C   b         ;      	  main dma                         +          	  disabled              8      clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          ?    0                6              b      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                 "                                      J           C   i          ;      	  main dma                         +          	  disabled              9      i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                "                                      J           C   i         ;      	  main dma                         +          	  disabled              :      i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?                 "                                     J           C   i         ;      	  main dma                         +            okay            e            j        default           ;   typec-mux@48              ite,it5205          ?   H                          
g   k   port       endpoint            	W   l           h               i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    0            "                                     J           C   i         ;      	  main dma                         +          	  disabled              <      i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    @            "                                      J           C   i         ;      	  main dma                         +            okay            e            m        default           =      clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          ?    P                6              i      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                   2           okay              >   usb-phy@0           ?               C                 ref da_ref          
              V      usb-phy@700         ?              C                    ref da_ref             n   o   p        intr rx_imp tx_imp          
              _         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                okay              ?   usb-phy@0           ?               C                 ref da_ref          
              F      usb-phy@700         ?              C                    ref da_ref             q   r   s        intr rx_imp tx_imp          
              G         phy@11e80000              mediatek,mt8195-pcie-phy            ?                     sif            t   u   v   w   x   y   z      G  glb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             2           
            okay               \      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           ?                     C            
  unipro mp           
            okay               U      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           ?             @         C   {          0                                                 Wjob mmu gpu            |      (     2   
   2      2      2      2           core0 core1 core2 core3 core4           okay                         @      clock-controller@13fbf000             mediatek,mt8195-mfgcfg          ?                    6              {      syscon@14000000           mediatek,mt8195-vppsys0 syscon          ?                      6              }                      !      dma-controller@14001000           mediatek,mt8195-mdp3-rdma           ?                        }                                   ~           2                         C   !         <     }         }         }         }         }                        display@14002000              mediatek,mt8195-mdp3-fg         ?                         }                   C   !          display@14003000              mediatek,mt8195-mdp3-stitch         ?     0                   }      0            C   !         display@14004000              mediatek,mt8195-mdp3-hdr            ?     @                   }      @            C   !   "      display@14005000              mediatek,mt8195-mdp3-aal            ?     P                      F                  }      P            C   !   
           2         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?     `                   }      `                %        C   !         display@14007000              mediatek,mt8195-mdp3-tdshp          ?     p                   }      p            C   !   #      display@14008000              mediatek,mt8195-mdp3-color          ?                           I                  }                  C   !   $           2         display@14009000              mediatek,mt8195-mdp3-ovl            ?                           J                  }                  C   !   %           2                       display@1400a000              mediatek,mt8195-mdp3-padding            ?                        }                  C   !              2         display@1400b000              mediatek,mt8195-mdp3-tcc            ?                        }                  C   !         dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?                        }                      +        C   !                            2                     mutex@1400f000            mediatek,mt8195-vpp-mutex           ?                           P                  }                  C   !              2         smi@14010000              mediatek,mt8195-smi-sub-common          ?                     C   !      !      !           apb smi gals0           +              2                    smi@14011000              mediatek,mt8195-smi-sub-common          ?                    C   !      !      !           apb smi gals0           +              2                    smi@14012000              mediatek,mt8195-smi-common-vpp          ?                      C   !      !      !      !           apb smi gals0 gals1            2                    larb@14013000             mediatek,mt8195-smi-larb            ?    0                8           +           C   !      !           apb smi            2                    iommu@14018000            mediatek,mt8195-iommu-vpp           ?                  8  I                                                        R               C   !           bclk                          2                    clock-controller@14e00000             mediatek,mt8195-wpesys          ?                     6              $      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         ?                     6             A      clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         ?    0                6             B      larb@14e04000             mediatek,mt8195-smi-larb            ?    @                8           +           C   $      $           apb smi            2                    larb@14e05000             mediatek,mt8195-smi-larb            ?    P                8           +           C   $      $      !           apb smi gals               2                    syscon@14f00000           mediatek,mt8195-vppsys1 syscon          ?                     6              }   	                  #      mutex@14f01000            mediatek,mt8195-vpp-mutex           ?                          {                  }   	              C   #   '           2         larb@14f02000             mediatek,mt8195-smi-larb            ?                     8           +           C   #      #      !           apb smi gals               2                    larb@14f03000             mediatek,mt8195-smi-larb            ?    0                8           +           C   #      #      !           apb smi gals               2                    display@14f06000              mediatek,mt8195-mdp3-split          ?    `                   }   	  `            C   #      #   +   #   ,           2         display@14f07000              mediatek,mt8195-mdp3-tcc            ?    p                   }   	  p            C   #         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           ?                       }   	                          C   #                            2                     dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           ?                       }   	                          C   #   
                         2                     dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           ?                       }   	                          C   #                            2                     display@14f0b000              mediatek,mt8195-mdp3-fg         ?                       }   	              C   #   	      display@14f0c000              mediatek,mt8195-mdp3-fg         ?                       }   	              C   #         display@14f0d000              mediatek,mt8195-mdp3-fg         ?                       }   	              C   #         display@14f0e000              mediatek,mt8195-mdp3-hdr            ?                       }   	              C   #         display@14f0f000              mediatek,mt8195-mdp3-hdr            ?                       }   	              C   #         display@14f10000              mediatek,mt8195-mdp3-hdr            ?                        }   
               C   #          display@14f11000              mediatek,mt8195-mdp3-aal            ?                          i                  }   
              C   #              2         display@14f12000              mediatek,mt8195-mdp3-aal            ?                           j                  }   
               C   #              2         display@14f13000              mediatek,mt8195-mdp3-aal            ?    0                      k                  }   
  0            C   #   !           2         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?    @                   }   
  @                        C   #         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?    P                   }   
  P                        C   #   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?    `                   }   
  `                        C   #   %      display@14f17000              mediatek,mt8195-mdp3-tdshp          ?    p                   }   
  p            C   #         display@14f18000              mediatek,mt8195-mdp3-tdshp          ?                       }   
              C   #   (      display@14f19000              mediatek,mt8195-mdp3-tdshp          ?                       }   
              C   #   )      display@14f1a000              mediatek,mt8195-mdp3-merge          ?                       }   
              C   #              2         display@14f1b000              mediatek,mt8195-mdp3-merge          ?                       }   
              C   #              2         display@14f1c000              mediatek,mt8195-mdp3-color          ?                          t                  }   
              C   #              2         display@14f1d000              mediatek,mt8195-mdp3-color          ?                       }   
                    u               C   #              2         display@14f1e000              mediatek,mt8195-mdp3-color          ?                          v                  }   
              C   #              2         display@14f1f000              mediatek,mt8195-mdp3-ovl            ?                          w                  }   
              C   #               2                       display@14f20000              mediatek,mt8195-mdp3-padding            ?                        }                  C   #              2         display@14f21000              mediatek,mt8195-mdp3-padding            ?                       }                 C   #              2         display@14f22000              mediatek,mt8195-mdp3-padding            ?                        }                  C   #              2         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?    0                   }     0                        C   #                            2                     dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?    @                   }     @                        C   #                            2                     dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?    P                   }     P                        C   #                            2                     clock-controller@15000000             mediatek,mt8195-imgsys          ?                      6              +      larb@15001000             mediatek,mt8195-smi-larb            ?                     8   	        +           C   +       +       +   
        apb smi gals               2                    smi@15002000              mediatek,mt8195-smi-sub-common          ?                      C   +      +      !           apb smi gals0           +              2                    smi@15003000              mediatek,mt8195-smi-sub-common          ?     0                C   +       +       +   
        apb smi gals0           +              2                    clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         ?                     6                    larb@15120000             mediatek,mt8195-smi-larb            ?                     8   
        +           C   +                  apb smi            2                    clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          ?                     6             C      clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         ?    "                 6                    larb@15230000             mediatek,mt8195-smi-larb            ?    #                 8           +           C   +                  apb smi            2                    clock-controller@15330000             mediatek,mt8195-ipesys          ?    3                 6              ,      larb@15340000             mediatek,mt8195-smi-larb            ?    4                 8           +           C   ,      ,           apb smi            2                    clock-controller@16000000             mediatek,mt8195-camsys          ?                      6              -      larb@16001000             mediatek,mt8195-smi-larb            ?                     8           +           C   -       -       -           apb smi gals               2                    larb@16002000             mediatek,mt8195-smi-larb            ?                      8           +           C   -      -           apb smi            2                    smi@16004000              mediatek,mt8195-smi-sub-common          ?     @                C   -       -       -           apb smi gals0           +              2                    smi@16005000              mediatek,mt8195-smi-sub-common          ?     P                C   -      -      !           apb smi gals0           +              2                    larb@16012000             mediatek,mt8195-smi-larb            ?                     8           +           C                      apb smi            2                     larb@16013000             mediatek,mt8195-smi-larb            ?    0                8           +           C                      apb smi            2                     larb@16014000             mediatek,mt8195-smi-larb            ?    @                8           +           C                      apb smi            2   !                 larb@16015000             mediatek,mt8195-smi-larb            ?    P                8           +           C                      apb smi            2   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa         ?                    6                    clock-controller@1606f000             mediatek,mt8195-camsys_yuva         ?                    6                    clock-controller@1608f000             mediatek,mt8195-camsys_rawb         ?                    6                    clock-controller@160af000             mediatek,mt8195-camsys_yuvb         ?    
                6                    clock-controller@16140000             mediatek,mt8195-camsys_mraw         ?                     6                    larb@16141000             mediatek,mt8195-smi-larb            ?                    8           +           C   -              -           apb smi gals               2   "                 larb@16142000             mediatek,mt8195-smi-larb            ?                     8           +           C                      apb smi            2   "                 clock-controller@17200000             mediatek,mt8195-ccusys          ?                      6                    larb@17201000             mediatek,mt8195-smi-larb            ?                     8           +           C                      apb smi            2                    video-codec@18000000              mediatek,mt8195-vcodec-dec             ~                                  +            ?                   @                                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         ?                                          C      A   %      %                 sel vdec lat top            H      A        X                 2         video-codec@10000             mediatek,mtk-vcodec-lat         ?                                         0                                          C      A   %      %                 sel vdec lat top            H      A        X                 2         video-codec@25000             mediatek,mtk-vcodec-core            ?     P                                   P                                                             C      A   &      &                 sel vdec lat top            H      A        X                 2            larb@1800d000             mediatek,mt8195-smi-larb            ?                     8           +           C   %       %            apb smi            2                    larb@1800e000             mediatek,mt8195-smi-larb            ?                     8           +           C   !      %            apb smi            2                    clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         ?                     6              %      larb@1802e000             mediatek,mt8195-smi-larb            ?                    8           +           C   &       &            apb smi            2                    clock-controller@1802f000             mediatek,mt8195-vdecsys         ?                    6              &      larb@1803e000             mediatek,mt8195-smi-larb            ?                    8           +           C   !      '            apb smi            2                    clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           ?                    6              '      clock-controller@190f3000             mediatek,mt8195-apusys_pll          ?    0                6             D      clock-controller@1a000000             mediatek,mt8195-vencsys         ?                      6              (      larb@1a010000             mediatek,mt8195-smi-larb            ?                     8           +           C   (      (           apb smi            2                    video-codec@1a020000              mediatek,mt8195-vcodec-enc          ?                   H       `     a     b     c     d     v     w     x     y              U                  ~        C   (         	  venc_sel            H      @        X                 2                        +             E      jpeg-decoder@1a040000             mediatek,mt8195-jpgdec             2         0       m     n     r     s     t     u                     +         0                                              jpgdec@0,0            mediatek,mt8195-jpgdec-hw           ?                     0       m     n     r     s     t     u              W               C   (           jpgdec             2         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw           ?                    0       m     n     r     s     t     u              X               C   (           jpgdec             2         jpgdec@1,0            mediatek,mt8195-jpgdec-hw           ?                    0                                              \               C   )           jpgdec             2            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           ?                      6              )      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            ?                                      6                                  "      jpeg-encoder@1a030000             mediatek,mt8195-jpgenc             2                                                     +         0                                              jpgenc@0,0            mediatek,mt8195-jpgenc-hw           ?                             g     h     i     l              V               C   (           jpgenc             2         jpgenc@1,0            mediatek,mt8195-jpgenc-hw           ?                                                         [               C   )           jpgenc             2            larb@1b010000             mediatek,mt8195-smi-larb            ?                     8           +           C   )      )      !            apb smi gals               2                    ovl@1c000000              mediatek,mt8195-disp-ovl            ?                            |                  2           C   "                                                 F   ports                        +       port@0          ?       endpoint              G         port@1          ?      endpoint            	W                             rdma@1c002000             mediatek,mt8195-disp-rdma           ?                            ~                  2           C   "                                                 H   ports                        +       port@0          ?       endpoint            	W                       port@1          ?      endpoint            	W                             color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           ?     0                                        2           C   "                   0              I   ports                        +       port@0          ?       endpoint            	W                       port@1          ?      endpoint            	W                             ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           ?     @                                        2           C   "                   @              J   ports                        +       port@0          ?       endpoint            	W                       port@1          ?      endpoint            	W                             aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           ?     P                                        2           C   "                   P              K   ports                        +       port@0          ?       endpoint            	W                       port@1          ?      endpoint            	W                             gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           ?     `                                        2           C   "                   `              L   ports                        +       port@0          ?       endpoint            	W                       port@1          ?      endpoint            	W                             dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         ?     p                                        2           C   "   	                p              M   ports                        +       port@0          ?       endpoint            	W                       port@1          ?      endpoint            	W                             dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         ?                                             2           C   "      "   *           engine digital hs                      
dphy          	  disabled                         +              N   ports                        +       port@0          ?       endpoint            	W                       port@1          ?      endpoint              O               dsc@1c009000              mediatek,mt8195-disp-dsc            ?                                             2           C   "                                 P      dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         ?                                             2           C   "      "   +           engine digital hs                      
dphy          	  disabled              Q      merge@1c014000            mediatek,mt8195-disp-merge          ?    @                                        2           C   "                   @              R      dp-intf@1c015000              mediatek,mt8195-dp-intf         ?    P                                        2           C   "   ,   "                 pixel engine pll          	  disabled              S      mutex@1c016000            mediatek,mt8195-disp-mutex          ?    `                                        2           C   "                   `              U          T      larb@1c018000             mediatek,mt8195-smi-larb            ?                    8            +           C   "   (   "   (   !           apb smi gals               2                    larb@1c019000             mediatek,mt8195-smi-larb            ?                    8           +           C   "   (   !       !           apb smi gals               2                    syscon@1c100000           mediatek,mt8195-vdosys1 syscon          ?                                                           6                         *      smi@1c01b000              mediatek,mt8195-smi-common-vdo          ?                     C   "   %   "   &   "   )   "   $        apb smi gals0 gals1            2                    iommu@1c01f000            mediatek,mt8195-iommu-vdo           ?                  8  I                                                                                  C   "   '        bclk               2                    mutex@1c101000            mediatek,mt8195-disp-mutex          ?                                            2           C   *                                           U      larb@1c102000             mediatek,mt8195-smi-larb            ?                     8           +           C   *       *       *           apb smi gals               2                    larb@1c103000             mediatek,mt8195-smi-larb            ?    0                8           +           C   *      *      !            apb smi gals               2                    dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           ?    @                                     C   *              2                 @                @                          V      dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           ?    P                                     C   *              2                 `                P                          W      dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           ?    `                                     C   *              2                 A                `                          X      dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           ?    p                                     C   *              2                 a                p                          Y      dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           ?                                         C   *              2                 B                                          Z      dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           ?                                         C   *              2                 b                                          [      dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           ?                                         C   *              2                 C                                          \      dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           ?                                         C   *              2                 c                                          ]      vpp-merge@1c10c000            mediatek,mt8195-disp-merge          ?                                         C   *   	   *           merge merge_async              2                                X           *             ^      vpp-merge@1c10d000            mediatek,mt8195-disp-merge          ?                                         C   *   
   *           merge merge_async              2                                X           *             _      vpp-merge@1c10e000            mediatek,mt8195-disp-merge          ?                                         C   *      *           merge merge_async              2                                X           *             `      vpp-merge@1c10f000            mediatek,mt8195-disp-merge          ?                                         C   *      *           merge merge_async              2                                X           *             a      vpp-merge@1c110000            mediatek,mt8195-disp-merge          ?                                          C   *      *           merge merge_async              2                                 l           *             b      dp-intf@1c113000              mediatek,mt8195-dp-intf         ?    0                                        2           C   *   /   *                 pixel engine pll          	  disabled              c      hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  ?    @            P            p                                                              4  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p          @            P            p                                                          h  C   *   %   *       *   #   *   !   *   $   *   "   *   1   *   &   *   '   *   (   *   )   *   *              mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             2                 d      e                           (     *   3   *   4   *   5   *   6   *   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async              d      edp-tx@1c500000           mediatek,mt8195-edp-tx          ?    P                            dp_calibration_data            2                                        	  disabled              e      dp-tx@1c600000            mediatek,mt8195-dp-tx           ?    `                            dp_calibration_data            2                                        	  disabled              f         thermal-zones             g   cpu0-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical              h         cooling-maps       map0                     0                          cpu1-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical              i         cooling-maps       map0                     0                          cpu2-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical              j         cooling-maps       map0                     0                          cpu3-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical              k         cooling-maps       map0                     0                          cpu4-thermal                                           trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical              l         cooling-maps       map0                     0                          cpu5-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical              m         cooling-maps       map0                     0                          cpu6-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical              n         cooling-maps       map0                     0                          cpu7-thermal                                          trips      trip-alert           L                   Epassive                  trip-crit                            	   Ecritical              o         cooling-maps       map0                     0                          vpu0-thermal                                          trips      trip-alert           L                   Epassive           p      trip-crit                            	   Ecritical              q            vpu1-thermal                                       	   trips      trip-alert           L                   Epassive           r      trip-crit                            	   Ecritical              s            gpu-thermal                                    
   trips      trip-alert           L                   Epassive           t      trip-crit                            	   Ecritical              u            gpu1-thermal                                          trips      trip-alert           L                   Epassive           v      trip-crit                            	   Ecritical              w            vdec-thermal                                          trips      trip-alert           L                   Epassive           x      trip-crit                            	   Ecritical              y            img-thermal                                       trips      trip-alert           L                   Epassive           z      trip-crit                            	   Ecritical              {            infra-thermal                                         trips      trip-alert           L                   Epassive           |      trip-crit                            	   Ecritical              }            cam0-thermal                                          trips      trip-alert           L                   Epassive           ~      trip-crit                            	   Ecritical                          cam1-thermal                                          trips      trip-alert           L                   Epassive                 trip-crit                            	   Ecritical                             chosen          serial0:921600n8          firmware       optee             linaro,optee-tz         Jsmc          memory@40000000         3memory          ?    @                backlight             pwm-backlight                           @        *      k            7          default                    N               	  disabled                    gpio-keys         
    gpio-keys                button-volume-up             }        S   d        
      j         
  <volume_up           e   s         regulator-wifi-3v3-en             regulator-fixed         wifi_3v3_en                   2Z         2Z         p               C            default                       W                regulator-vsys            regulator-fixed         vsys                               LK@         LK@                      W      regulator-vsys-buck           regulator-fixed       
  vsys_buck                              LK@         LK@                      e      regulator-vcc5v0-sys              regulator-fixed         vcc5v0_sys                                     reserved-memory                      +               optee@43200000          ?    C                                   memory@50000000           shared-dma-pool         ?    P                             0      memory@53000000           shared-dma-pool         ?    S       @                  memory@54600000         ?    T`                                   memory@60000000           shared-dma-pool         ?    `                              6      memory@60f00000           shared-dma-pool         ?    `                             8      memory@61000000           shared-dma-pool         ?    a                              5      memory@62000000           shared-dma-pool         ?    b       @                     __symbols__         /cpus/cpu@0         /cpus/cpu@100           /cpus/cpu@200           /cpus/cpu@300           /cpus/cpu@400           /cpus/cpu@500           /cpus/cpu@600           /cpus/cpu@700         "  /cpus/idle-states/cpu-retention-l         "  /cpus/idle-states/cpu-retention-b           /cpus/idle-states/cpu-off-l         /cpus/idle-states/cpu-off-b         /cpus/l2-cache0         /cpus/l2-cache1         /cpus/l3-cache          /dmic-codec         /mt8195-sound           /fixed-factor-clock-13m         /oscillator-26m         %/oscillator-32k         ,/performance-controller@11bc10          8/opp-table-gpu          F/timer        "  L/soc/interrupt-controller@c000000         G  P/soc/interrupt-controller@c000000/ppi-partitions/interrupt-partition-0        G  ]/soc/interrupt-controller@c000000/ppi-partitions/interrupt-partition-1          /soc/syscon@10000000            j/soc/syscon@10001000            p/soc/syscon@10003000            !/soc/pinctrl@10005000         )  v/soc/pinctrl@10005000/audio-default-pins          *  /soc/pinctrl@10005000/dsi0-backlight-pins         '  /soc/pinctrl@10005000/eth-default-pins        %  /soc/pinctrl@10005000/eth-sleep-pins          %  /soc/pinctrl@10005000/gpio-keys-pins             /soc/pinctrl@10005000/i2c2-pins          /soc/pinctrl@10005000/i2c4-pins          /soc/pinctrl@10005000/i2c6-pins       (  /soc/pinctrl@10005000/mmc0-default-pins       $  /soc/pinctrl@10005000/mmc0-uhs-pins       (  	/soc/pinctrl@10005000/mmc1-default-pins       '  /soc/pinctrl@10005000/mmc1-detect-pins        "  ,/soc/pinctrl@10005000/mt6360-pins         !  8/soc/pinctrl@10005000/panel-pins          )  K/soc/pinctrl@10005000/pcie0-default-pins          )  ^/soc/pinctrl@10005000/pcie1-default-pins             q/soc/pinctrl@10005000/pwm0-pins       (  /soc/pinctrl@10005000/spi1-default-pins       (  /soc/pinctrl@10005000/spi2-default-pins       !  /soc/pinctrl@10005000/touch-pins          !  /soc/pinctrl@10005000/uart0-pins          !  /soc/pinctrl@10005000/uart1-pins          *  /soc/pinctrl@10005000/usb3p0-default-pins         *  /soc/pinctrl@10005000/usb2p0-default-pins         %  /soc/pinctrl@10005000/wifi-vreg-pins            /soc/syscon@10006000          &  /soc/syscon@10006000/power-controller         5  /soc/syscon@10006000/power-controller/power-domain@8          D  /soc/syscon@10006000/power-controller/power-domain@8/power-domain@9         /soc/watchdog@10007000          /soc/syscon@1000c000            /soc/timer@10017000         /soc/pwrap@10024000         /soc/pwrap@10024000/pmic            $/soc/pwrap@10024000/pmic/adc          %  -/soc/pwrap@10024000/pmic/audio-codec          -  9/soc/pwrap@10024000/pmic/regulators/buck_vs1          0  M/soc/pwrap@10024000/pmic/regulators/buck_vgpu11       0  d/soc/pwrap@10024000/pmic/regulators/buck_vmodem       -  {/soc/pwrap@10024000/pmic/regulators/buck_vpu          /  /soc/pwrap@10024000/pmic/regulators/buck_vcore        -  /soc/pwrap@10024000/pmic/regulators/buck_vs2          -  /soc/pwrap@10024000/pmic/regulators/buck_vpa          0  /soc/pwrap@10024000/pmic/regulators/buck_vproc2       0  /soc/pwrap@10024000/pmic/regulators/buck_vproc1       5  /soc/pwrap@10024000/pmic/regulators/buck_vcore_sshub          6  /soc/pwrap@10024000/pmic/regulators/buck_vgpu11_sshub         /  4/soc/pwrap@10024000/pmic/regulators/ldo_vaud18        .  J/soc/pwrap@10024000/pmic/regulators/ldo_vsim1         -  _/soc/pwrap@10024000/pmic/regulators/ldo_vibr          .  s/soc/pwrap@10024000/pmic/regulators/ldo_vrf12         -  /soc/pwrap@10024000/pmic/regulators/ldo_vusb          4  /soc/pwrap@10024000/pmic/regulators/ldo_vsram_proc2       .  /soc/pwrap@10024000/pmic/regulators/ldo_vio18         /  /soc/pwrap@10024000/pmic/regulators/ldo_vcamio        .  /soc/pwrap@10024000/pmic/regulators/ldo_vcn18         .  /soc/pwrap@10024000/pmic/regulators/ldo_vfe28         .  /soc/pwrap@10024000/pmic/regulators/ldo_vcn13         3  !/soc/pwrap@10024000/pmic/regulators/ldo_vcn33_1_bt        5  ;/soc/pwrap@10024000/pmic/regulators/ldo_vcn33_1_wifi          /  W/soc/pwrap@10024000/pmic/regulators/ldo_vaux18        5  m/soc/pwrap@10024000/pmic/regulators/ldo_vsram_others          /  /soc/pwrap@10024000/pmic/regulators/ldo_vefuse        .  /soc/pwrap@10024000/pmic/regulators/ldo_vxo22         .  /soc/pwrap@10024000/pmic/regulators/ldo_vrfck         0  /soc/pwrap@10024000/pmic/regulators/ldo_vrfck_1       /  /soc/pwrap@10024000/pmic/regulators/ldo_vbif28        .  /soc/pwrap@10024000/pmic/regulators/ldo_vio28         -  /soc/pwrap@10024000/pmic/regulators/ldo_vemc          /  /soc/pwrap@10024000/pmic/regulators/ldo_vemc_1        3  5/soc/pwrap@10024000/pmic/regulators/ldo_vcn33_2_bt        5  O/soc/pwrap@10024000/pmic/regulators/ldo_vcn33_2_wifi          -  k/soc/pwrap@10024000/pmic/regulators/ldo_va12          -  /soc/pwrap@10024000/pmic/regulators/ldo_va09          .  /soc/pwrap@10024000/pmic/regulators/ldo_vrf18         1  /soc/pwrap@10024000/pmic/regulators/ldo_vsram_md          -  /soc/pwrap@10024000/pmic/regulators/ldo_vufs          -  /soc/pwrap@10024000/pmic/regulators/ldo_vm18          .  /soc/pwrap@10024000/pmic/regulators/ldo_vbbck         4  /soc/pwrap@10024000/pmic/regulators/ldo_vsram_proc1       .  /soc/pwrap@10024000/pmic/regulators/ldo_vsim2         ;  -/soc/pwrap@10024000/pmic/regulators/ldo_vsram_others_sshub          K/soc/pwrap@10024000/pmic/rtc            U/soc/pwrap@10024000/pmic/keys           `/soc/spmi@10027000          e/soc/spmi@10027000/pmic@6         ,  n/soc/spmi@10027000/pmic@6/regulators/vbuck1         ~/soc/spmi@10027000/pmic@7         ,  /soc/spmi@10027000/pmic@7/regulators/vbuck1         /soc/infra-iommu@10315000            \/soc/mailbox@10320000            a/soc/mailbox@10330000           /soc/scp@10500000           /soc/clock-controller@10720000          /soc/dsp@10803000           /soc/mailbox@10816000           /soc/mailbox@10817000           /soc/mt8195-afe-pcm@10890000            /soc/serial@11001100            /soc/serial@11001200            /soc/serial@11001300            /soc/serial@11001400            /soc/serial@11001500            /soc/serial@11001600            /soc/auxadc@11002000            /soc/syscon@11003000            )/soc/spi@1100a000           /soc/thermal-sensor@1100b000            
/soc/svs@1100bc00           /soc/pwm@1100e000           /soc/pwm@1100f000           ./soc/spi@11010000           "/soc/spi@11012000           '/soc/spi@11013000           ,/soc/spi@11018000           1/soc/spi@11019000           6/soc/spi@1101d000           </soc/spi@1101e000           B/soc/ethernet@11021000        +  F/soc/ethernet@11021000/mdio/ethernet-phy@1        )  P/soc/ethernet@11021000/stmmac-axi-config          (  a/soc/ethernet@11021000/rx-queues-config       (  n/soc/ethernet@11021000/tx-queues-config         {/soc/usb@11201000           /soc/usb@11201000/usb@0          /soc/usb@11201000/port/endpoint         /soc/mmc@11230000           /soc/mmc@11240000           /soc/mmc@11250000           /soc/ufshci@11270000            /soc/thermal-sensor@11278000            /soc/usb@11290000           /soc/usb@112a1000           /soc/usb@112a1000/usb@0         /soc/usb@112b1000           /soc/usb@112b1000/usb@0         /soc/pcie@112f0000        (  /soc/pcie@112f0000/interrupt-controller         /soc/pcie@112f8000        (  /soc/pcie@112f8000/interrupt-controller         /soc/spi@1132c000           /soc/efuse@11c10000       &  
/soc/efuse@11c10000/usb3-tx-imp@184,1         &  /soc/efuse@11c10000/usb3-rx-imp@184,2         "  $/soc/efuse@11c10000/usb3-intr@185         &  //soc/efuse@11c10000/usb3-tx-imp@186,1         &  >/soc/efuse@11c10000/usb3-rx-imp@186,2         "  M/soc/efuse@11c10000/usb3-intr@187         '  Z/soc/efuse@11c10000/usb2-intr-p0@188,1        '  e/soc/efuse@11c10000/usb2-intr-p1@188,2        '  p/soc/efuse@11c10000/usb2-intr-p2@189,1        '  {/soc/efuse@11c10000/usb2-intr-p3@189,2        )  /soc/efuse@11c10000/pciephy-rx-ln1@190,1          .  /soc/efuse@11c10000/pciephy-tx-ln1-nmos@190,2         .  /soc/efuse@11c10000/pciephy-tx-ln1-pmos@191,1         )  /soc/efuse@11c10000/pciephy-rx-ln0@191,2          .  /soc/efuse@11c10000/pciephy-tx-ln0-nmos@192,1         .  /soc/efuse@11c10000/pciephy-tx-ln0-pmos@192,2         )  /soc/efuse@11c10000/pciephy-glb-intr@193             /soc/efuse@11c10000/dp-data@1ac       $  /soc/efuse@11c10000/lvts1-calib@1bc       $  %/soc/efuse@11c10000/lvts2-calib@1d0       "  6/soc/efuse@11c10000/svs-calib@580           E/soc/t-phy@11c40000         L/soc/t-phy@11c40000/usb-phy@0           T/soc/t-phy@11c50000         [/soc/t-phy@11c50000/usb-phy@0           c/soc/dsi-phy@11c80000           l/soc/dsi-phy@11c90000           u/soc/i2c@11d00000           z/soc/i2c@11d01000           /soc/i2c@11d01000/pmic@34         9  /soc/i2c@11d01000/pmic@34/charger/usb-otg-vbus-regulator          *  /soc/i2c@11d01000/pmic@34/regulator/buck1         *  /soc/i2c@11d01000/pmic@34/regulator/buck2         )  /soc/i2c@11d01000/pmic@34/regulator/ldo1          )  /soc/i2c@11d01000/pmic@34/regulator/ldo2          )  /soc/i2c@11d01000/pmic@34/regulator/ldo3          )  /soc/i2c@11d01000/pmic@34/regulator/ldo5          )  /soc/i2c@11d01000/pmic@34/regulator/ldo6          )  /soc/i2c@11d01000/pmic@34/regulator/ldo7          @  /soc/i2c@11d01000/pmic@34/typec/connector/ports/port@0/endpoint       @  /soc/i2c@11d01000/pmic@34/typec/connector/ports/port@2/endpoint         /soc/i2c@11d02000           /soc/clock-controller@11d03000           /soc/i2c@11e00000            /soc/i2c@11e01000            /soc/i2c@11e02000         -  */soc/i2c@11e02000/typec-mux@48/port/endpoint            /soc/i2c@11e03000           
/soc/i2c@11e04000           9/soc/clock-controller@11e05000          H/soc/t-phy@11e30000         O/soc/t-phy@11e30000/usb-phy@0            W/soc/t-phy@11e30000/usb-phy@700         _/soc/t-phy@11e40000         f/soc/t-phy@11e40000/usb-phy@0            n/soc/t-phy@11e40000/usb-phy@700         v/soc/phy@11e80000           ~/soc/ufs-phy@11fa0000           /soc/gpu@13000000           /soc/clock-controller@13fbf000          /soc/syscon@14000000            /soc/smi@14010000           /soc/smi@14011000           /soc/smi@14012000           /soc/larb@14013000          /soc/iommu@14018000         /soc/clock-controller@14e00000          /soc/clock-controller@14e02000          /soc/clock-controller@14e03000          /soc/larb@14e04000          /soc/larb@14e05000          /soc/syscon@14f00000            $/soc/larb@14f02000          */soc/larb@14f03000          0/soc/clock-controller@15000000          7/soc/larb@15001000          =/soc/smi@15002000           U/soc/smi@15003000           m/soc/clock-controller@15110000          }/soc/larb@15120000          /soc/clock-controller@15130000          /soc/clock-controller@15220000          /soc/larb@15230000          /soc/clock-controller@15330000          /soc/larb@15340000          /soc/clock-controller@16000000          /soc/larb@16001000          /soc/larb@16002000          /soc/smi@16004000           /soc/smi@16005000           /soc/larb@16012000          /soc/larb@16013000          /soc/larb@16014000          /soc/larb@16015000          /soc/clock-controller@1604f000          /soc/clock-controller@1606f000          +/soc/clock-controller@1608f000          7/soc/clock-controller@160af000          C/soc/clock-controller@16140000          O/soc/larb@16141000          V/soc/larb@16142000          ]/soc/clock-controller@17200000          d/soc/larb@17201000          k/soc/larb@1800d000          r/soc/larb@1800e000          y/soc/clock-controller@1800f000          /soc/larb@1802e000          /soc/clock-controller@1802f000          /soc/larb@1803e000          /soc/clock-controller@1803f000          /soc/clock-controller@190f3000          /soc/clock-controller@1a000000          /soc/larb@1a010000          /soc/video-codec@1a020000           /soc/clock-controller@1b000000          /soc/syscon@1c01a000            /soc/larb@1b010000          /soc/ovl@1c000000         (  /soc/ovl@1c000000/ports/port@0/endpoint       (  /soc/ovl@1c000000/ports/port@1/endpoint          /soc/rdma@1c002000        )  /soc/rdma@1c002000/ports/port@0/endpoint          )  /soc/rdma@1c002000/ports/port@1/endpoint            /soc/color@1c003000       *  /soc/color@1c003000/ports/port@0/endpoint         *  /soc/color@1c003000/ports/port@1/endpoint           */soc/ccorr@1c004000       *  1/soc/ccorr@1c004000/ports/port@0/endpoint         *  ;/soc/ccorr@1c004000/ports/port@1/endpoint           F/soc/aal@1c005000         (  K/soc/aal@1c005000/ports/port@0/endpoint       (  S/soc/aal@1c005000/ports/port@1/endpoint         \/soc/gamma@1c006000       *  c/soc/gamma@1c006000/ports/port@0/endpoint         *  m/soc/gamma@1c006000/ports/port@1/endpoint           x/soc/dither@1c007000          +  /soc/dither@1c007000/ports/port@0/endpoint        +  /soc/dither@1c007000/ports/port@1/endpoint          /soc/dsi@1c008000         (  /soc/dsi@1c008000/ports/port@0/endpoint       (  /soc/dsi@1c008000/ports/port@1/endpoint         /soc/dsc@1c009000           /soc/dsi@1c012000           /soc/merge@1c014000         /soc/dp-intf@1c015000           /soc/mutex@1c016000         /soc/larb@1c018000          /soc/larb@1c019000          /soc/syscon@1c100000            /soc/smi@1c01b000           /soc/iommu@1c01f000          t/soc/mutex@1c101000         /soc/larb@1c102000           /soc/larb@1c103000          /soc/dma-controller@1c104000            /soc/dma-controller@1c105000            /soc/dma-controller@1c106000            '/soc/dma-controller@1c107000            2/soc/dma-controller@1c108000            =/soc/dma-controller@1c109000            H/soc/dma-controller@1c10a000            S/soc/dma-controller@1c10b000             {/soc/vpp-merge@1c10c000          /soc/vpp-merge@1c10d000          /soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000         ^/soc/dp-intf@1c113000            f/soc/hdr-engine@1c114000            g/soc/edp-tx@1c500000            h/soc/dp-tx@1c600000         n/thermal-zones        -  |/thermal-zones/cpu0-thermal/trips/trip-alert          ,  /thermal-zones/cpu0-thermal/trips/trip-crit       -  /thermal-zones/cpu1-thermal/trips/trip-alert          ,  /thermal-zones/cpu1-thermal/trips/trip-crit       -  /thermal-zones/cpu2-thermal/trips/trip-alert          ,  /thermal-zones/cpu2-thermal/trips/trip-crit       -  /thermal-zones/cpu3-thermal/trips/trip-alert          ,  /thermal-zones/cpu3-thermal/trips/trip-crit       -  /thermal-zones/cpu4-thermal/trips/trip-alert          ,  /thermal-zones/cpu4-thermal/trips/trip-crit       -  /thermal-zones/cpu5-thermal/trips/trip-alert          ,  /thermal-zones/cpu5-thermal/trips/trip-crit       -  /thermal-zones/cpu6-thermal/trips/trip-alert          ,  /thermal-zones/cpu6-thermal/trips/trip-crit       -  /thermal-zones/cpu7-thermal/trips/trip-alert          ,  /thermal-zones/cpu7-thermal/trips/trip-crit       -  $/thermal-zones/vpu0-thermal/trips/trip-alert          ,  //thermal-zones/vpu0-thermal/trips/trip-crit       -  9/thermal-zones/vpu1-thermal/trips/trip-alert          ,  D/thermal-zones/vpu1-thermal/trips/trip-crit       ,  N/thermal-zones/gpu-thermal/trips/trip-alert       +  Y/thermal-zones/gpu-thermal/trips/trip-crit        -  c/thermal-zones/gpu1-thermal/trips/trip-alert          ,  n/thermal-zones/gpu1-thermal/trips/trip-crit       -  x/thermal-zones/vdec-thermal/trips/trip-alert          ,  /thermal-zones/vdec-thermal/trips/trip-crit       ,  /thermal-zones/img-thermal/trips/trip-alert       +  /thermal-zones/img-thermal/trips/trip-crit        .  /thermal-zones/infra-thermal/trips/trip-alert         -  /thermal-zones/infra-thermal/trips/trip-crit          -  /thermal-zones/cam0-thermal/trips/trip-alert          ,  /thermal-zones/cam0-thermal/trips/trip-crit       -  /thermal-zones/cam1-thermal/trips/trip-alert          ,  /thermal-zones/cam1-thermal/trips/trip-crit         /backlight          [/gpio-keys          /regulator-wifi-3v3-en          /regulator-vsys         /regulator-vsys-buck            /regulator-vcc5v0-sys            /reserved-memory/optee@43200000       !  /reserved-memory/memory@50000000          !  '/reserved-memory/memory@53000000          !  //reserved-memory/memory@54600000          !  ?/reserved-memory/memory@60000000          !  H/reserved-memory/memory@60f00000          !  T/reserved-memory/memory@61000000          !  a/reserved-memory/memory@62000000             	compatible interrupt-parent #address-cells #size-cells model chassis-type dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c0 i2c1 i2c2 i2c3 i2c4 ethernet0 serial0 serial1 spi0 spi1 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform pinctrl-names pinctrl-0 audio-routing mediatek,adsp link-name sound-dai #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges mediatek,rsel-resistance-in-si-unit pinmux output-high drive-strength input-enable bias-disable input-disable bias-pull-up drive-strength-microamp bias-pull-down output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes mediatek,long-press-mode power-off-time-sec linux,keycodes wakeup-source #iommu-cells #mbox-cells memory-region firmware-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,tx-delay-ps mediatek,mac-wol snps,reset-gpio snps,reset-delays-us snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys mediatek,syscon-wakeup role-switch-default-mode usb-role-switch vusb33-supply vbus-supply remote-endpoint bus-width max-frequency hs400-ds-delay cap-mmc-highspeed cap-mmc-hw-reset mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable vmmc-supply vqmmc-supply cap-sd-highspeed cd-gpios no-mmc sd-uhs-sdr50 sd-uhs-sdr104 freq-table-hz mediatek,ufs-disable-mcq vcc-supply vccq2-supply usb2-lpm-disable mediatek,u3p-dis-msk bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN1-supply LDO_VIN3-supply label data-role op-sink-microwatt power-role try-power-role source-pdos sink-pdos mode-switch orientation-switch operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path brightness-levels default-brightness-level enable-gpios num-interpolated-steps pwms debounce-interval linux,code enable-active-high vin-supply regulator-boot-on no-map cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_ret_l cpu_ret_b cpu_off_l cpu_off_b l2_0 l2_1 l3_0 dmic_codec sound clk13m clk26m clk32k performance gpu_opp_table timer gic ppi_cluster0 ppi_cluster1 infracfg_ao audio_default_pins dsi0_backlight_pins eth_default_pins eth_sleep_pins gpio_key_pins i2c2_pins i2c4_pins i2c6_pins mmc0_default_pins mmc0_uhs_pins mmc1_default_pins mmc1_pins_detect mt6360_pins panel_default_pins pcie0_default_pins pcie1_default_pins pwm0_default_pins spi1_pins spi2_pins touch_pins uart0_pins uart1_pins usb3_port0_pins usb2_port0_pins wifi_vreg_pins scpsys spm mfg0 mfg1 watchdog apmixedsys systimer pwrap pmic pmic_adc mt6359codec mt6359_vs1_buck_reg mt6359_vgpu11_buck_reg mt6359_vmodem_buck_reg mt6359_vpu_buck_reg mt6359_vcore_buck_reg mt6359_vs2_buck_reg mt6359_vpa_buck_reg mt6359_vproc2_buck_reg mt6359_vproc1_buck_reg mt6359_vcore_sshub_buck_reg mt6359_vgpu11_sshub_buck_reg mt6359_vaud18_ldo_reg mt6359_vsim1_ldo_reg mt6359_vibr_ldo_reg mt6359_vrf12_ldo_reg mt6359_vusb_ldo_reg mt6359_vsram_proc2_ldo_reg mt6359_vio18_ldo_reg mt6359_vcamio_ldo_reg mt6359_vcn18_ldo_reg mt6359_vfe28_ldo_reg mt6359_vcn13_ldo_reg mt6359_vcn33_1_bt_ldo_reg mt6359_vcn33_1_wifi_ldo_reg mt6359_vaux18_ldo_reg mt6359_vsram_others_ldo_reg mt6359_vefuse_ldo_reg mt6359_vxo22_ldo_reg mt6359_vrfck_ldo_reg mt6359_vrfck_1_ldo_reg mt6359_vbif28_ldo_reg mt6359_vio28_ldo_reg mt6359_vemc_ldo_reg mt6359_vemc_1_ldo_reg mt6359_vcn33_2_bt_ldo_reg mt6359_vcn33_2_wifi_ldo_reg mt6359_va12_ldo_reg mt6359_va09_ldo_reg mt6359_vrf18_ldo_reg mt6359_vsram_md_ldo_reg mt6359_vufs_ldo_reg mt6359_vm18_ldo_reg mt6359_vbbck_ldo_reg mt6359_vsram_proc1_ldo_reg mt6359_vsim2_ldo_reg mt6359_vsram_others_sshub_ldo mt6359rtc mt6359keys spmi mt6315_6 mt6315_6_vbuck1 mt6315_7 mt6315_7_vbuck1 iommu_infra scp_adsp adsp_mailbox0 adsp_mailbox1 afe uart0 uart1 uart2 uart3 uart4 uart5 auxadc pericfg_ao lvts_ap svs disp_pwm0 disp_pwm1 spi2 spi3 spi4 spi5 spis0 spis1 eth rgmii_phy stmmac_axi_setup mtl_rx_setup mtl_tx_setup ssusb0 xhci0 mtu3_hs0_role_sw mmc0 mmc1 mmc2 ufshci lvts_mcu xhci1 ssusb2 xhci2 ssusb3 xhci3 pcie0 pcie_intc0 pcie1 pcie_intc1 nor_flash efuse u3_tx_imp_p0 u3_rx_imp_p0 u3_intr_p0 comb_tx_imp_p1 comb_rx_imp_p1 comb_intr_p1 u2_intr_p0 u2_intr_p1 u2_intr_p2 u2_intr_p3 pciephy_rx_ln1 pciephy_tx_ln1_nmos pciephy_tx_ln1_pmos pciephy_rx_ln0 pciephy_tx_ln0_nmos pciephy_tx_ln0_pmos pciephy_glb_intr dp_calibration lvts_efuse_data1 lvts_efuse_data2 svs_calib_data u3phy2 u2port2 u3phy3 u2port3 mipi_tx0 mipi_tx1 i2c5 i2c6 mt6360 otg_vbus_regulator mt6360_buck1 mt6360_buck2 mt6360_ldo1 mt6360_ldo2 mt6360_ldo3 mt6360_ldo5 mt6360_ldo6 mt6360_ldo7 typec_con_hs typec_con_mux i2c7 imp_iic_wrap_s it5205_sbu_mux imp_iic_wrap_w u3phy1 u2port1 u3port1 u3phy0 u2port0 u3port0 pciephy ufsphy gpu mfgcfg vppsys0 smi_sub_common_vpp0_vpp1_2x1 smi_sub_common_vdec_vpp0_2x1 smi_common_vpp larb4 iommu_vpp wpesys wpesys_vpp0 wpesys_vpp1 larb7 larb8 vppsys1 larb5 larb6 imgsys larb9 smi_sub_common_img0_3x1 smi_sub_common_img1_3x1 imgsys1_dip_top larb10 imgsys1_dip_nr imgsys1_wpe larb11 ipesys larb12 camsys larb13 larb14 smi_sub_common_cam_4x1 smi_sub_common_cam_7x1 larb16 larb17 larb27 larb28 camsys_rawa camsys_yuva camsys_rawb camsys_yuvb camsys_mraw larb25 larb26 ccusys larb18 larb24 larb23 vdecsys_soc larb21 vdecsys larb22 vdecsys_core1 apusys_pll vencsys larb19 venc vencsys_core1 vdosys0 larb20 ovl0 ovl0_in ovl0_out rdma0_in rdma0_out color0 color0_in color0_out ccorr0 ccorr0_in ccorr0_out aal0 aal0_in aal0_out gamma0 gamma0_in gamma0_out dither0 dither0_in dither0_out dsi0 dsi0_in dsi0_out dsc0 dsi1 merge0 dp_intf0 mutex larb0 larb1 vdosys1 smi_common_vdo iommu_vdo larb2 larb3 vdo1_rdma0 vdo1_rdma1 vdo1_rdma2 vdo1_rdma3 vdo1_rdma4 vdo1_rdma5 vdo1_rdma6 vdo1_rdma7 dp_intf1 edp_tx thermal_zones cpu0_alert cpu0_crit cpu1_alert cpu1_crit cpu2_alert cpu2_crit cpu3_alert cpu3_crit cpu4_alert cpu4_crit cpu5_alert cpu5_crit cpu6_alert cpu6_crit cpu7_alert cpu7_crit vpu0_alert vpu0_crit vpu1_alert vpu1_crit gpu0_alert gpu0_crit gpu1_alert gpu1_crit vdec_alert vdec_crit img_alert img_crit infra_alert infra_crit cam0_alert cam0_crit cam1_alert cam1_crit backlight wifi_vreg vsys vsys_buck vcc5v0_vsys optee_reserved scp_mem vpu_mem bl31_secmon_mem adsp_mem afe_dma_mem adsp_dma_mem apu_mem 