 )   8  x   (              @                             $    mediatek,mt8195-evb mediatek,mt8195                                  +         !   7MediaTek MT8195 evaluation board       aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000             /soc/serial@11001100          cpus                         +       cpu@0            cpu           arm,cortex-a55                       psci                           #ec3@        3  4        F              V           c   @        u                         @                                            	      cpu@100          cpu           arm,cortex-a55                      psci                           #ec3@        3  4        F              V           c   @        u                         @                                            
      cpu@200          cpu           arm,cortex-a55                      psci                           #ec3@        3  4        F              V           c   @        u                         @                                                  cpu@300          cpu           arm,cortex-a55                      psci                           #ec3@        3  4        F              V           c   @        u                         @                                                  cpu@400          cpu           arm,cortex-a78                      psci                          #f        3           F              V           c   @        u                         @                                                  cpu@500          cpu           arm,cortex-a78                      psci                          #f        3           F              V           c   @        u                         @                                                  cpu@600          cpu           arm,cortex-a78                      psci                          #f        3           F              V           c   @        u                         @                                                  cpu@700          cpu           arm,cortex-a78                      psci                          #f        3           F              V           c   @        u                         @                                                  cpu-map    cluster0       core0              	      core1              
      core2                    core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-retention-l           arm,idle-state                                2            _        0  D                 cpu-retention-b           arm,idle-state                                -                    0                   cpu-off-l             arm,idle-state                               7                    0  H                 cpu-off-b             arm,idle-state                               2                    0                      l2-cache0             cache           A           X           e   @        w                       M                 l2-cache1             cache           A           X           e   @        w                       M                 l3-cache              cache           A           X            e   @        w            M                    dsu-pmu           arm,dsu-pmu         [                       f   	   
                          kfail          dmic-codec            dmic-codec          r              2      mt8195-sound                     	  kdisabled          fixed-factor-clock-13m            fixed-factor-clock                                                       clk13m             (      oscillator-26m            fixed-clock                     #        clk26m                   oscillator-32k            fixed-clock                     #           clk32k        performance-controller@11bc10             mediatek,cpufreq-hw                            0                                   opp-table-gpu             operating-points-v2                     V   opp-390000000               >        	 	h      opp-410000000               p        	 	      opp-431000000                       	 	      opp-473000000               1h@        	 	<      opp-515000000               F        	 	<      opp-556000000               !#         	 	Ҧ      opp-598000000               #        	 	      opp-640000000               &%         	 	      opp-670000000               'c        	 
      opp-700000000               )'         	 
L      opp-730000000               +        	 
}      opp-760000000               -L         	 
`      opp-790000000               /q        	 
4      opp-820000000               05         	       opp-850000000               2        	 @      opp-880000000               4s         	 q         pmu-a55           arm,cortex-a55-pmu                      [                  pmu-a78           arm,cortex-a78-pmu                      [                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  [                                             
             soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3          )           :                        Q                                              [      	                     ppi-partitions     interrupt-partition-0           f   	   
                       interrupt-partition-1           f                                   syscon@10000000            mediatek,mt8195-topckgen syscon                                                    syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon                                           o                    syscon@10003000           mediatek,mt8195-pericfg syscon                0                              7      pinctrl@10005000              mediatek,mt8195-pinctrl               P                                                                                                         B  |iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint                                                      Q        [                      )                 i2c0-pins              E   pins                	           e                    i2c1-pins              F   pins              
             e                    i2c4-pins              G   pins                           e                   i2c6-pins              C   pins                           e         i2c7-pins      pins                           e         nor-pins               A   pins0                                pins1                                   uart0-pins             .   pins              b  c            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd                  `           power-controller          !    mediatek,mt8195-power-controller                         +                          *   power-domain@8                                   +                  power-domain@9              	                            mfg alt                                 +                  power-domain@10             
                  power-domain@11                               power-domain@12                               power-domain@13                               power-domain@14                                     power-domain@15                                             	      @      A      K                                                                                                                                vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18                                   +                  power-domain@16                   8              $      %      &      '      (      )      D  vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5                                 +                  power-domain@17                                               vppsys1 vppsys1-0 vppsys1-1                              power-domain@22                                                    $  wepsys-0 wepsys-1 wepsys-2 wepsys-3                              power-domain@23                                    vdec0-0                                 +                   power-domain@24                                    vdec1-0                              power-domain@25                                     vdec2-0                                 power-domain@26                        !            venc0-larb                                  +                   power-domain@27                        "            venc1-larb                                  power-domain@18                               #       #      #         &  vdosys1 vdosys1-0 vdosys1-1 vdosys1-2                                   +                  power-domain@19                                          power-domain@20                                          power-domain@21                           Q        hdmi_tx                      power-domain@28                        $       $   
        img-0 img-1                                 +                  power-domain@29                               power-domain@30                              $      %           ipe ipe-0 ipe-1                                 power-domain@31                   (     &       &      &      &      &           cam-0 cam-1 cam-2 cam-3 cam-4                                   +                  power-domain@32                                power-domain@33             !                  power-domain@34             "                           power-domain@0                                            power-domain@1                                           power-domain@2                                power-domain@3                                power-domain@4                            5      7        csi_rx_top csi_rx_top1                    power-domain@5                         '           ether                     power-domain@6                            X      n        adsp adsp1                       +                             power-domain@7                             g      "      n      2        audio audio1 audio2 audio3                                        watchdog@10007000             mediatek,mt8195-wdt          *              p                o              -      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon                                                     timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer              p                [      	                  (      pwrap@10024000            mediatek,mt8195-pwrap syscon                 @                |pwrap           [                                         	  spi wrap            B      $        R            spmi@10027000             mediatek,mt8195-spmi                  p                            |pmif spmimst                               E      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         B      $        R            infra-iommu@10315000              mediatek,mt8195-iommu-infra              1P       P       P  [                                                                         i              =      mailbox@10320000              mediatek,mt8195-gce              2        @         [                      v                            y      mailbox@10330000              mediatek,mt8195-gce              3        @         [                      v                            W      scp@10500000              mediatek,mt8195-scp       0       P             r             p                 |sram cfg l1tcm          [                   	  kdisabled               X      clock-controller@10720000             mediatek,mt8195-scp_adsp                 r                               )      dsp@10803000              mediatek,mt8195-dsp               0                           	  |cfg sram          ,        X         n         )          #      K  adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             *           rx tx              +   ,      	  kdisabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           v                 `                [                        +      mailbox@10817000              mediatek,mt8195-adsp-mbox           v                 p                [                        ,      mt8195-afe-pcm@10890000           mediatek,mt8195-audio                                               *           [      6                  -         	  audiosys                                                               g      "      #      n      e      a      b      c      d      2   )            clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  kdisabled                     serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 [                                     	  baud bus            kokay            default            .      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 [                                     	  baud bus          	  kdisabled          serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 [                                     	  baud bus          	  kdisabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 [                                    	  baud bus          	  kdisabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 [                                    	  baud bus          	  kdisabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart                                 [                                    	  baud bus          	  kdisabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc                                                main                       kokay          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon                 0                              '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  [                                                parent-clk sel-clk spi-clk        	  kdisabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap                               [                                                      /   0      $  lvts-calib-data-1 lvts-calib-data-2                             svs@1100bc00              mediatek,mt8195-svs                               [                                    main               1   /      (  svs-calibration-data t-calibration-data                       svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                                 [                         *           $                 *      0        main mm       	  kdisabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                                 [                     $                 +      N        main mm       	  kdisabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  [                                        3        parent-clk sel-clk spi-clk        	  kdisabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  [                                        4        parent-clk sel-clk spi-clk        	  kdisabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                 0                [                                        5        parent-clk sel-clk spi-clk        	  kdisabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 [                                        <        parent-clk sel-clk spi-clk        	  kdisabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 [                                        =        parent-clk sel-clk spi-clk        	  kdisabled          spi@1101d000              mediatek,mt8195-spi-slave                                [                            R        spi         B              R            	  kdisabled          spi@1101e000              mediatek,mt8195-spi-slave                                [                            S        spi         B              R            	  kdisabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a                       @         [                     /macirq        .  axi apb mac_main ptp_ref rmii_internal mac_cg         0     '       '         R      S      T   '           B      R      S      T        R                             *           ?           P   2        `   3        s   4                                        	  kdisabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config                                                                     2      rx-queues-config                                   3   queue0                             queue1                             queue2                             queue3                                tx-queues-config            %            ;           4   queue0          M                    Y          queue1          M                    Y         queue2          M                    Y         queue3          M                    Y               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3                        -     >              	  |mac ippc                                 ?                      +           [                            /            B        sys_ck ref_ck mcu_ck            g   5      6            l        z   7      g        kokay       usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                  |mac         [                      B      ,      -        R                  $        /                     B      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         kokay             mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc               #                              [                                                source hclk source_cg         	  kdisabled          mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc               $                              [                                        $        source hclk source_cg           B              R            	  kdisabled          mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc               %                              [                                         I        source hclk source_cg           B               R            	  kdisabled          ufshci@11270000           mediatek,mt8195-ufshci               '        #         [                      g   8      @        ?      @      A      6      7      8      Z      ]      X  ufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @                                                                                 	  kdisabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu                 '                [                                                     /   0      $  lvts-calib-data-1 lvts-calib-data-2                             usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci                )             )>              	  |mac ippc            [                     g   9      :           B      .      /        R                  $     '                     '         $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         z   7      h         l        kokay          usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3                *       -    *>              	  |mac ippc                        *        ?                      +           [                     B      0        R                 '            '           sys_ck ref_ck mcu_ck            g   ;            l        z   7      i        kokay       usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                  |mac         [                     B      1        R                 '           sys_ck          kokay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3                +       -    +>              	  |mac ippc                        +        ?                      +           [                     B      2        R                 '            '   	        sys_ck ref_ck mcu_ck            g   <            l        z   7      j        kokay       usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                  |mac         [                     B      3        R                 '   	        sys_ck          kokay                      pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            pci                      +                /        @       	  |pcie-mac            [                                  8                                                                     =                        0        V      #      &      +      K   '         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          B      G        R              g   >      	  pcie-phy               *            )                                `  	                  ?                      ?                     ?                     ?         	  kdisabled       interrupt-controller             Q                     )              ?         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            pci                      +                /       @       	  |pcie-mac            [                                  8         $       $                  $       $                        =                        (        W         X         Q   '         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          B      H        R              g   :         	  pcie-phy               *           )                                `  	                  @                      @                     @                     @         	  kdisabled       interrupt-controller             Q                     )              @         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor              2                [      9                     o   '      '           spi sf axi                       +            kokay            default            A   flash@0           jedec,spi-nor                                 efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse                                               +      usb3-tx-imp@184,1                         )                  M      usb3-rx-imp@184,2                         )                 L      usb3-intr@185                         )                 K      usb3-tx-imp@186,1                         )                  J      usb3-rx-imp@186,2                         )                 I      usb3-intr@187                         )                 H      usb2-intr-p0@188,1                        )             usb2-intr-p1@188,2                        )            usb2-intr-p2@189,1                        )            usb2-intr-p3@189,2                        )            pciephy-rx-ln1@190,1                          )                  T      pciephy-tx-ln1-nmos@190,2                         )                 S      pciephy-tx-ln1-pmos@191,1                         )                  R      pciephy-rx-ln0@191,2                          )                 Q      pciephy-tx-ln0-nmos@192,1                         )                  P      pciephy-tx-ln0-pmos@192,2                         )                 O      pciephy-glb-intr@193                          )                  N      dp-data@1ac                                lvts1-calib@1bc                          /      lvts2-calib@1d0               8           0      svs-calib@580                 d           1      socinfo-data1@7a0                          t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                kokay       usb-phy@0                                         ref         .              ;         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                kokay       usb-phy@0                                         ref         .              <         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx                                          mipi_tx0_pll                        .          	  kdisabled                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx                                          mipi_tx1_pll                        .          	  kdisabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                            "               [                                    B          ;      	  main dma                         +          	  kdisabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "                [                                    B         ;      	  main dma                         +            kokay            default            C        #       i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                            "               [                                    B         ;      	  main dma                         +          	  kdisabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s               0                              B      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                            "                [                                    D          ;      	  main dma                         +            kokay            default            E        #       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "                [                                    D         ;      	  main dma                         +            kokay            default            F        #       i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                            "               [                                    D         ;      	  main dma                         +          	  kdisabled          i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c               0            "               [                                    D         ;      	  main dma                         +          	  kdisabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c               @            "                [                                    D         ;      	  main dma                         +            kokay            default            G        #       clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w               P                              D      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                   *           kokay       usb-phy@0                                            ref da_ref          .              9      usb-phy@700                                            ref da_ref             H   I   J        intr rx_imp tx_imp          .              :         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                                kokay       usb-phy@0                                            ref da_ref          .              5      usb-phy@700                                            ref da_ref             K   L   M        intr rx_imp tx_imp          .              6         phy@11e80000              mediatek,mt8195-pcie-phy                                  |sif            N   O   P   Q   R   S   T      G  glb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             *           .          	  kdisabled               >      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy                                             
  unipro mp           .          	  kdisabled               8      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm                         @            U          0  [                                               /job mmu gpu         9   V      (     *   
   *      *      *      *           Mcore0 core1 core2 core3 core4         	  kdisabled          clock-controller@13fbf000             mediatek,mt8195-mfgcfg                                             U      syscon@14000000           mediatek,mt8195-vppsys0 syscon                                            `   W                            dma-controller@14001000           mediatek,mt8195-mdp3-rdma                                 `   W                  x                 X           *              Y                       <     W         W         W         W         W                       display@14002000              mediatek,mt8195-mdp3-fg                                `   W                                display@14003000              mediatek,mt8195-mdp3-stitch               0                `   W      0                        display@14004000              mediatek,mt8195-mdp3-hdr                  @                `   W      @                  "      display@14005000              mediatek,mt8195-mdp3-aal                  P                [      F               `   W      P                  
           *         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                 `                `   W      `            x    %                    display@14007000              mediatek,mt8195-mdp3-tdshp                p                `   W      p                  #      display@14008000              mediatek,mt8195-mdp3-color                                [      I               `   W                        $           *         display@14009000              mediatek,mt8195-mdp3-ovl                                  [      J               `   W                        %           *              Y         display@1400a000              mediatek,mt8195-mdp3-padding                                  `   W                                   *         display@1400b000              mediatek,mt8195-mdp3-tcc                                  `   W                              dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot                               `   W                  x    +                         Y              *                    mutex@1400f000            mediatek,mt8195-vpp-mutex                                 [      P               `   W                                   *         smi@14010000              mediatek,mt8195-smi-sub-common                                                          apb smi gals0              Z           *              [      smi@14011000              mediatek,mt8195-smi-sub-common                                                         apb smi gals0              Z           *              x      smi@14012000              mediatek,mt8195-smi-common-vpp                                                                 apb smi gals0 gals1            *              Z      larb@14013000             mediatek,mt8195-smi-larb                 0                              [                            apb smi            *              ^      iommu@14018000            mediatek,mt8195-iommu-vpp                              8     \   ]   ^   _   `   a   b   c   d   e   f   g   h   i        [      R                             bclk            i              *              Y      clock-controller@14e00000             mediatek,mt8195-wpesys                                                    clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0                                        clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1              0                         larb@14e04000             mediatek,mt8195-smi-larb                 @                              j                            apb smi            *                    larb@14e05000             mediatek,mt8195-smi-larb                 P                              Z                                  apb smi gals               *              `      syscon@14f00000           mediatek,mt8195-vppsys1 syscon                                           `   W   	                        mutex@14f01000            mediatek,mt8195-vpp-mutex                                [      {               `   W   	                    '           *         larb@14f02000             mediatek,mt8195-smi-larb                                                j                                  apb smi gals               *                    larb@14f03000             mediatek,mt8195-smi-larb                 0                              [                                  apb smi gals               *              _      display@14f06000              mediatek,mt8195-mdp3-split               `                `   W   	  `                        +      ,           *         display@14f07000              mediatek,mt8195-mdp3-tcc                 p                `   W   	  p                        dma-controller@14f08000           mediatek,mt8195-mdp3-rdma                                `   W   	              x                             k              *                    dma-controller@14f09000           mediatek,mt8195-mdp3-rdma                                `   W   	              x                  
           k              *                    dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma                                `   W   	              x                             Y              *                    display@14f0b000              mediatek,mt8195-mdp3-fg                              `   W   	                    	      display@14f0c000              mediatek,mt8195-mdp3-fg                              `   W   	                          display@14f0d000              mediatek,mt8195-mdp3-fg                              `   W   	                          display@14f0e000              mediatek,mt8195-mdp3-hdr                                 `   W   	                          display@14f0f000              mediatek,mt8195-mdp3-hdr                                 `   W   	                          display@14f10000              mediatek,mt8195-mdp3-hdr                                  `   W   
                            display@14f11000              mediatek,mt8195-mdp3-aal                                 [      i               `   W   
                               *         display@14f12000              mediatek,mt8195-mdp3-aal                                  [      j               `   W   
                                *         display@14f13000              mediatek,mt8195-mdp3-aal                 0                [      k               `   W   
  0                  !           *         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                @                `   W   
  @            x                        display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                P                `   W   
  P            x                  $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                `   W   
  `            x                  %      display@14f17000              mediatek,mt8195-mdp3-tdshp               p                `   W   
  p                        display@14f18000              mediatek,mt8195-mdp3-tdshp                               `   W   
                    (      display@14f19000              mediatek,mt8195-mdp3-tdshp                               `   W   
                    )      display@14f1a000              mediatek,mt8195-mdp3-merge                               `   W   
                               *         display@14f1b000              mediatek,mt8195-mdp3-merge                               `   W   
                               *         display@14f1c000              mediatek,mt8195-mdp3-color                               [      t               `   W   
                               *         display@14f1d000              mediatek,mt8195-mdp3-color                               `   W   
              [      u                                *         display@14f1e000              mediatek,mt8195-mdp3-color                               [      v               `   W   
                               *         display@14f1f000              mediatek,mt8195-mdp3-ovl                                 [      w               `   W   
                                *              k         display@14f20000              mediatek,mt8195-mdp3-padding                                  `   W                                   *         display@14f21000              mediatek,mt8195-mdp3-padding                                 `   W                                  *         display@14f22000              mediatek,mt8195-mdp3-padding                                  `   W                                   *         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot              0                `   W     0            x                             k              *                    dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot              @                `   W     @            x                             k              *                    dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot              P                `   W     P            x                             Y              *                    clock-controller@15000000             mediatek,mt8195-imgsys                                               $      larb@15001000             mediatek,mt8195-smi-larb                                     	           l           $       $       $   
        apb smi gals               *                    smi@15002000              mediatek,mt8195-smi-sub-common                                    $      $                 apb smi gals0              Z           *              o      smi@15003000              mediatek,mt8195-smi-sub-common                0                   $       $       $   
        apb smi gals0              j           *              l      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top                                             m      larb@15120000             mediatek,mt8195-smi-larb                                     
           l           $      m            apb smi            *                    clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr                                         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe              "                               n      larb@15230000             mediatek,mt8195-smi-larb                 #                               l           $      n            apb smi            *                    clock-controller@15330000             mediatek,mt8195-ipesys               3                               %      larb@15340000             mediatek,mt8195-smi-larb                 4                               o           %      %           apb smi            *              a      clock-controller@16000000             mediatek,mt8195-camsys                                               &      larb@16001000             mediatek,mt8195-smi-larb                                                p           &       &       &           apb smi gals               *                    larb@16002000             mediatek,mt8195-smi-larb                                                 q           &      &           apb smi            *              b      smi@16004000              mediatek,mt8195-smi-sub-common                @                   &       &       &           apb smi gals0              j           *              p      smi@16005000              mediatek,mt8195-smi-sub-common                P                   &      &                 apb smi gals0              Z           *              q      larb@16012000             mediatek,mt8195-smi-larb                                                q           r       r            apb smi            *               c      larb@16013000             mediatek,mt8195-smi-larb                 0                              p           s       s            apb smi            *                     larb@16014000             mediatek,mt8195-smi-larb                 @                              q           t       t            apb smi            *   !           i      larb@16015000             mediatek,mt8195-smi-larb                 P                              p           u       u            apb smi            *   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa                                            r      clock-controller@1606f000             mediatek,mt8195-camsys_yuva                                            s      clock-controller@1608f000             mediatek,mt8195-camsys_rawb                                            t      clock-controller@160af000             mediatek,mt8195-camsys_yuvb              
                              u      clock-controller@16140000             mediatek,mt8195-camsys_mraw                                             v      larb@16141000             mediatek,mt8195-smi-larb                                               p           &       v       &           apb smi gals               *   "                 larb@16142000             mediatek,mt8195-smi-larb                                                q           v       v            apb smi            *   "           h      clock-controller@17200000             mediatek,mt8195-ccusys                                               w      larb@17201000             mediatek,mt8195-smi-larb                                                q           w       w            apb smi            *              d      video-codec@18000000              mediatek,mt8195-vcodec-dec             X           k                       +                                @                                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc                                    Y     Y                 A                          sel vdec lat top            B      A        R                 *         video-codec@10000             mediatek,mtk-vcodec-lat                                [                   0     k      k     k     k     k     k                 A                          sel vdec lat top            B      A        R                 *         video-codec@25000             mediatek,mtk-vcodec-core                  P                [                   P     k     k     k     k     k     k     k     k     k     k                 A                          sel vdec lat top            B      A        R                 *            larb@1800d000             mediatek,mt8195-smi-larb                                                j                              apb smi            *                    larb@1800e000             mediatek,mt8195-smi-larb                                                x                             apb smi            *              g      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc                                                   larb@1802e000             mediatek,mt8195-smi-larb                                               j                              apb smi            *                    clock-controller@1802f000             mediatek,mt8195-vdecsys                                                  larb@1803e000             mediatek,mt8195-smi-larb                                               x                              apb smi            *              f      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1                                                     clock-controller@190f3000             mediatek,mt8195-apusys_pll               0                         clock-controller@1a000000             mediatek,mt8195-vencsys                                              !      larb@1a010000             mediatek,mt8195-smi-larb                                                j           !      !           apb smi            *                    video-codec@1a020000              mediatek,mt8195-vcodec-enc                              H     k  `   k  a   k  b   k  c   k  d   k  v   k  w   k  x   k  y        [      U                  X           !         	  venc_sel            B      @        R                 *                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec             *         0     k  m   k  n   k  r   k  s   k  t   k  u                     +         0                                              jpgdec@0,0            mediatek,mt8195-jpgdec-hw                                 0     k  m   k  n   k  r   k  s   k  t   k  u        [      W                  !           jpgdec             *         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw                                0     k  m   k  n   k  r   k  s   k  t   k  u        [      X                  !           jpgdec             *         jpgdec@1,0            mediatek,mt8195-jpgdec-hw                                0     Y     Y     Y     Y     Y     Y          [      \                  "           jpgdec             *            clock-controller@1b000000             mediatek,mt8195-vencsys_core1                                                "      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon                                    y                          `   y                          jpeg-encoder@1a030000             mediatek,mt8195-jpgenc             *               Y     Y     Y     Y                       +         0                                              jpgenc@0,0            mediatek,mt8195-jpgenc-hw                                       k  g   k  h   k  i   k  l        [      V                  !           jpgenc             *         jpgenc@1,0            mediatek,mt8195-jpgenc-hw                                      Y     Y     Y     Y          [      [                  "           jpgenc             *            larb@1b010000             mediatek,mt8195-smi-larb                                                Z           "      "                  apb smi gals               *              e      ovl@1c000000              mediatek,mt8195-disp-ovl                                   [      |                  *                             k           `   y             ports                        +       port@0                  endpoint             port@1                 endpoint               z           {               rdma@1c002000             mediatek,mt8195-disp-rdma                                  [      ~                  *                            k            `   y             ports                        +       port@0                  endpoint               {           z         port@1                 endpoint               |           }               color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color                 0                [                        *                         `   y     0       ports                        +       port@0                  endpoint               }           |         port@1                 endpoint               ~                          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr                 @                [                        *                         `   y     @       ports                        +       port@0                  endpoint                          ~         port@1                 endpoint                                         aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal                 P                [                        *                         `   y     P       ports                        +       port@0                  endpoint                                   port@1                 endpoint                                         gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma                 `                [                        *                         `   y     `       ports                        +       port@0                  endpoint                                   port@1                 endpoint                                         dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither               p                [                        *                 	        `   y     p       ports                        +       port@0                  endpoint                                   port@1                 endpoint                   dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                               [                        *                       *           engine digital hs           g           dphy          	  kdisabled          dsc@1c009000              mediatek,mt8195-disp-dsc                                  [                        *                         `   y               dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                               [                        *                       +           engine digital hs           g           dphy          	  kdisabled          merge@1c014000            mediatek,mt8195-disp-merge               @                [                        *                         `   y     @          dp-intf@1c015000              mediatek,mt8195-dp-intf              P                [                        *                 ,                    pixel engine pll          	  kdisabled          mutex@1c016000            mediatek,mt8195-disp-mutex               `                [                        *                         `   y     `            x  U      larb@1c018000             mediatek,mt8195-smi-larb                                                j              (      (              apb smi gals               *                    larb@1c019000             mediatek,mt8195-smi-larb                                               Z              (                     apb smi gals               *              \      syscon@1c100000           mediatek,mt8195-vdosys1 syscon                                   y              `   y                             o              #      smi@1c01b000              mediatek,mt8195-smi-common-vdo                                      %      &      )      $        apb smi gals0 gals1            *              j      iommu@1c01f000            mediatek,mt8195-iommu-vdo                              8                                                    [                     i                 '        bclk               *              k      mutex@1c101000            mediatek,mt8195-disp-mutex                               [                        *              #           `   y                 x        larb@1c102000             mediatek,mt8195-smi-larb                                                j           #       #       #           apb smi gals               *                    larb@1c103000             mediatek,mt8195-smi-larb                 0                              Z           #      #                  apb smi gals               *              ]      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma                @                [                        #              *              k   @        `   y     @                     dma-controller@1c105000           mediatek,mt8195-vdo1-rdma                P                [                        #              *              Y   `        `   y     P                     dma-controller@1c106000           mediatek,mt8195-vdo1-rdma                `                [                        #              *              k   A        `   y     `                     dma-controller@1c107000           mediatek,mt8195-vdo1-rdma                p                [                        #              *              Y   a        `   y     p                     dma-controller@1c108000           mediatek,mt8195-vdo1-rdma                                [                        #              *              k   B        `   y                          dma-controller@1c109000           mediatek,mt8195-vdo1-rdma                                [                        #              *              Y   b        `   y                          dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma                                [                        #              *              k   C        `   y                          dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma                                [                        #              *              Y   c        `   y                          vpp-merge@1c10c000            mediatek,mt8195-disp-merge                               [                        #   	   #           merge merge_async              *           `   y                             #         vpp-merge@1c10d000            mediatek,mt8195-disp-merge                               [                        #   
   #           merge merge_async              *           `   y                             #         vpp-merge@1c10e000            mediatek,mt8195-disp-merge                               [                        #      #           merge merge_async              *           `   y                             #         vpp-merge@1c10f000            mediatek,mt8195-disp-merge                               [                        #      #           merge merge_async              *           `   y                             #         vpp-merge@1c110000            mediatek,mt8195-disp-merge                                [                        #      #           merge merge_async              *           `   y                              #         dp-intf@1c113000              mediatek,mt8195-dp-intf              0                [                        *              #   /   #                 pixel engine pll          	  kdisabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p       @            P            p                                                              4  |mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  `   y     @       y     P       y     p       y            y            y            y               h     #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *              mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             *              Y   d   Y   e        [                   (     #   3   #   4   #   5   #   6   #   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx               P                            dp_calibration_data            *           [                             	  kdisabled          dp-tx@1c600000            mediatek,mt8195-dp-tx                `                            dp_calibration_data            *           [                             	  kdisabled             thermal-zones      cpu0-thermal            $          2           H         trips      trip-alert          X L        d           passive                  trip-crit           X         d        	   critical             cooling-maps       map0            o         0  t   	   
                  cpu1-thermal            $          2           H         trips      trip-alert          X L        d           passive                  trip-crit           X         d        	   critical             cooling-maps       map0            o         0  t   	   
                  cpu2-thermal            $          2           H         trips      trip-alert          X L        d           passive                  trip-crit           X         d        	   critical             cooling-maps       map0            o         0  t   	   
                  cpu3-thermal            $          2           H         trips      trip-alert          X L        d           passive                  trip-crit           X         d        	   critical             cooling-maps       map0            o         0  t   	   
                  cpu4-thermal            $          2           H          trips      trip-alert          X L        d           passive                  trip-crit           X         d        	   critical             cooling-maps       map0            o         0  t                        cpu5-thermal            $          2           H         trips      trip-alert          X L        d           passive                  trip-crit           X         d        	   critical             cooling-maps       map0            o         0  t                        cpu6-thermal            $          2           H         trips      trip-alert          X L        d           passive                  trip-crit           X         d        	   critical             cooling-maps       map0            o         0  t                        cpu7-thermal            $          2           H         trips      trip-alert          X L        d           passive                  trip-crit           X         d        	   critical             cooling-maps       map0            o         0  t                        vpu0-thermal            $          2           H         trips      trip-alert          X L        d           passive       trip-crit           X         d        	   critical                vpu1-thermal            $          2           H      	   trips      trip-alert          X L        d           passive       trip-crit           X         d        	   critical                gpu-thermal         $          2           H      
   trips      trip-alert          X L        d           passive       trip-crit           X         d        	   critical                gpu1-thermal            $          2           H         trips      trip-alert          X L        d           passive       trip-crit           X         d        	   critical                vdec-thermal            $          2           H         trips      trip-alert          X L        d           passive       trip-crit           X         d        	   critical                img-thermal         $          2           H         trips      trip-alert          X L        d           passive       trip-crit           X         d        	   critical                infra-thermal           $          2           H         trips      trip-alert          X L        d           passive       trip-crit           X         d        	   critical                cam0-thermal            $          2           H         trips      trip-alert          X L        d           passive       trip-crit           X         d        	   critical                cam1-thermal            $          2           H         trips      trip-alert          X L        d           passive       trip-crit           X         d        	   critical                   chosen          serial0:921600n8          memory@40000000          memory               @                   	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux bias-pull-up drive-strength drive-strength-microamp bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 #io-channel-cells nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup freq-table-hz mediatek,ufs-disable-mcq usb2-lpm-disable bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map spi-max-frequency bits #phy-cells operating-points-v2 power-domain-names mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path 