  b   8  \X   (              \                                                                       ,Freescale i.MX8DXL EVK           2fsl,imx8dxl-evk fsl,imx8dxl    aliases           =/bus@5b000000/ethernet@5b040000           G/bus@5b000000/ethernet@5b050000          Q/bus@5d000000/gpio@5d080000          W/bus@5d000000/gpio@5d090000          ]/bus@5d000000/gpio@5d0a0000          c/bus@5d000000/gpio@5d0b0000          i/bus@5d000000/gpio@5d0c0000          o/bus@5d000000/gpio@5d0d0000          u/bus@5d000000/gpio@5d0e0000          {/bus@5d000000/gpio@5d0f0000          /bus@5d000000/mailbox@5d1c0000           /bus@5a000000/i2c@5a820000           /bus@5b000000/mmc@5b010000           /bus@5b000000/mmc@5b020000           /bus@5a000000/serial@5a060000         cpus                                 cpu@0            cpu          2arm,cortex-a35                            psci                                                                           cpu@1            cpu          2arm,cortex-a35                           psci                                                                           l2-cache0            2cache                        opp-table            2operating-points-v2                          opp-900000000               5          B@         I      opp-1200000000              G                   I         .         interrupt-controller@51a00000            2arm,gic-v3                Q             Q                 :            K        `      	                     reserved-memory                                   k   dsp@92400000                 @                  r                  linux,cma            2shared-dma-pool          y                                                       pmu          2arm,armv8-pmuv3         `               psci             2arm,psci-1.0             smc       system-controller            2fsl,imx-scu         tx0 rx0 gip3          $                                   power-controller             2fsl,scu-pd                   8                                                              clock-controller             2fsl,imx8dxl-clk fsl,scu-clk                                   xtal_32KHz xtal_24Mhz                     pinctrl          2fsl,imx8dxl-iomuxc          default               hoggrp        0     <        I         @     L   k     L                  usbotg1grp                   !      usbotg2grp                   !      eqosgrp            -         ,         3         9         6         5         4         :         /         7         8         0         2         1                  .      fec1grp            #         *         -          ,          $       `   &       `   '       `   (       `   )       `   %       `          `          `           `   !       `   "       `          `            (      lpspi3grp         0     =      @   >      @   ?      @   A      @      i2c2grp            s     !   t     !                  cm40lpuartgrp              S         R            i2c3grp            v     !   u     !      lpuart0grp             \          ]                         usdhc1grp              	      A   
       !          !          !          !          !          !          !          !          !          A                   usdhc2gpiogrp         $           @          !   !      !            #      usdhc2grp         T     $     A   %      !   &      !   '      !   (      !   )      !         !            "         ocotp            2fsl,imx8qxp-scu-ocotp                               mac@2c4                           *      mac@2c6                           0         rtc          2fsl,imx8qxp-sc-rtc        keys          "   2fsl,imx8qxp-sc-key fsl,imx-sc-key              t                watchdog             2fsl,imx-sc-wdt          .   <      thermal-sensor           2fsl,imx-sc-thermal          :               	         timer            2arm,armv8-timer       0  `                                 
         thermal-zones      cpu-thermal0            P           f          t   	  c   trips      trip0                               passive             
      trip1                            	   critical             cooling-maps       map0               
                          pmic-thermal0           P           f          t   	     trips      trip0                               passive                   trip1            H                	   critical             cooling-maps       map0                                            clock-xtal32k            2fixed-clock                                xtal_32KHz                    clock-xtal24m            2fixed-clock                     n6         xtal_24MHz                    bus@59000000             2simple-bus                                   kY       Y         clock-audio-ipg          2fixed-clock                     	h         audio_ipg_clk                     clock-controller@59580000            2fsl,imx8qxp-lpcg             YX                                                         4  dsp_lpcg_adb_clk dsp_lpcg_ipg_clk dsp_lpcg_core_clk                                 clock-controller@59590000            2fsl,imx8qxp-lpcg             YY                                               dsp_ram_lpcg_ipg_clk                                   dsp@596e8000             2fsl,imx8qxp-dsp          Yn                                      ipg ocram core                                          txdb0 txdb1 rxdb0 rxdb1       0                                                         	  disabled             bus@5a000000             2simple-bus                                   kZ       Z         clock-dma-ipg            2fixed-clock                     	h         dma_ipg_clk                   serial@5a060000          Z             `                                      	  ipg baud                  9        okay          &   2fsl,imx8qxp-lpuart fsl,imx7ulp-lpuart           default                  serial@5a070000          Z             `                                      	  ipg baud                  :      	  disabled          &   2fsl,imx8qxp-lpuart fsl,imx7ulp-lpuart         serial@5a080000          Z             `                                      	  ipg baud                  ;      	  disabled          &   2fsl,imx8qxp-lpuart fsl,imx7ulp-lpuart         serial@5a090000          Z	             `                                      	  ipg baud                  <      	  disabled          &   2fsl,imx8qxp-lpuart fsl,imx7ulp-lpuart         clock-controller@5a460000            2fsl,imx8qxp-lpcg             ZF                               9                           '  uart0_lpcg_baud_clk uart0_lpcg_ipg_clk                9                  clock-controller@5a470000            2fsl,imx8qxp-lpcg             ZG                               :                           '  uart1_lpcg_baud_clk uart1_lpcg_ipg_clk                :                  clock-controller@5a480000            2fsl,imx8qxp-lpcg             ZH                               ;                           '  uart2_lpcg_baud_clk uart2_lpcg_ipg_clk                ;                  clock-controller@5a490000            2fsl,imx8qxp-lpcg             ZI                               <                           '  uart3_lpcg_baud_clk uart3_lpcg_ipg_clk                <                  i2c@5a800000             Z    @         `                                        per ipg               `           n6               `      	  disabled          6   2fsl,imx8dxl-lpi2c fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c         i2c@5a810000             Z    @         `                                        per ipg               a           n6               a      	  disabled          6   2fsl,imx8dxl-lpi2c fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c         i2c@5a820000             Z    @         `                                        per ipg               b           n6               b        okay          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c                                            default               gpio@20          2ti,tca6416                        (        8               +      gpio@21          2ti,tca6416              !         (        8               :      i2c-mux@70           2nxp,pca9548                                       p   i2c@0                                             gpio@68          2maxim,max7322               h         (        8         	  disabled                ;         i2c@4                                               i2c@5                                               i2c@6                                                     i2c@5a830000             Z    @         `                                        per ipg               c           n6               c      	  disabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       clock-controller@5ac00000            2fsl,imx8qxp-lpcg             Z                               `                              i2c0_lpcg_clk i2c0_lpcg_ipg_clk               `                  clock-controller@5ac10000            2fsl,imx8qxp-lpcg             Z                               a                              i2c1_lpcg_clk i2c1_lpcg_ipg_clk               a                  clock-controller@5ac20000            2fsl,imx8qxp-lpcg             Z                               b                              i2c2_lpcg_clk i2c2_lpcg_ipg_clk               b                  clock-controller@5ac30000            2fsl,imx8qxp-lpcg             Z                               c                              i2c3_lpcg_clk i2c3_lpcg_ipg_clk               c                     bus@5b000000             2simple-bus                                   k[       [         clock-conn-axi           2fixed-clock                     CU        conn_axi_clk                3      clock-conn-ahb           2fixed-clock                     	!        conn_ahb_clk          clock-conn-ipg           2fixed-clock                             conn_ipg_clk                2      mmc@5b010000            `                   [                                         ipg ahb per                       okay          $   2fsl,imx8dxl-usdhc fsl,imx8qxp-usdhc         default                     D            N         T         \      mmc@5b020000            `                   [                 !      !       !           ipg ahb per                       j                      okay          $   2fsl,imx8dxl-usdhc fsl,imx8qxp-usdhc         default            "   #        D              $           %                 %              mmc@5b030000            `                   [                 &      &       &           ipg ahb per                     	  disabled          $   2fsl,imx8dxl-usdhc fsl,imx8qxp-usdhc       ethernet@5b040000            [           0  `                                                     '      '      '      '            ipg ahb enet_clk_ref ptp                             sY@                                          	  disabled             2fsl,imx8qm-fec          default            (        rgmii-txid             )                              *        mac-address    mdio                                 ethernet-phy@1           2ethernet-phy-ieee802.3-c22                      (   +               4  '         D        Y   ,            )   vddio-regulator         f w@        ~ w@            ,               ethernet@5b050000            [             `                          (      -      -      -       -      -           stmmaceth pclk ptp_ref tx mem                            sY@                      okay          (   2nxp,imx8dxl-dwmac-eqos snps,dwmac-5.10a                      eth_wake_irq macirq         default            .      	  rgmii-id               /           0        mac-address    mdio             2snps,dwmac-mdio                              ethernet-phy@0           2ethernet-phy-ieee802.3-c22                                 D                 (   +              4            @        Y   1            /   vddio-regulator         f w@        ~ w@            1               clock-controller@5b200000            2fsl,imx8qxp-lpcg             [                                      2   3                        9  sdhc0_lpcg_per_clk sdhc0_lpcg_ipg_clk sdhc0_lpcg_ahb_clk                                    clock-controller@5b210000            2fsl,imx8qxp-lpcg             [!                                     2   3                        9  sdhc1_lpcg_per_clk sdhc1_lpcg_ipg_clk sdhc1_lpcg_ahb_clk                              !      clock-controller@5b220000            2fsl,imx8qxp-lpcg             ["                                     2   3                        9  sdhc2_lpcg_per_clk sdhc2_lpcg_ipg_clk sdhc2_lpcg_ahb_clk                              &      clock-controller@5b230000            2fsl,imx8qxp-lpcg             [#                             4   4   3            2   2                                   enet0_lpcg_timer_clk enet0_lpcg_txc_sampling_clk enet0_lpcg_ahb_clk enet0_lpcg_rgmii_txc_clk enet0_lpcg_ipg_clk enet0_lpcg_ipg_s_clk                              '      clock-controller@5b240000            2fsl,imx8qxp-lpcg             [$                            4   3   3            2                              6  eqos_ptp eqos_mem_clk eqos_aclk eqos_clk eqos_csr_clk                             -      clock-conn-enet0-root            2fixed-clock                     沀        conn_enet0_root_clk             4      usb@5b0e0000              2fsl,imx8dxl-usb fsl,imx7ulp-usb          [                          `                     5           6                7                               "           6                      	  disabled       clock-dummy          2fixed-clock                               
  clk_dummy               7         usbmisc@5b0e0200            G            2fsl,imx7ulp-usbmisc          [                6      usbphy@0x5b110000         &   2fsl,imx8dxl-usbphy fsl,imx7ulp-usbphy            [                 8                       	  disabled                5      clock-controller@5b280000            2fsl,imx8qxp-lpcg             [(                                       2        usboh3_2_phy_ipg_clk                              8         bus@5c000000             2simple-bus                                   k\       \         ddr-pmu@5c020000             2fsl,imx8-ddr-pmu             \             `       G            bus@5d000000             2simple-bus                                   k]       ]         clock-lsio-mem           2fixed-clock                              lsio_mem_clk          clock-lsio-bus           2fixed-clock                              lsio_bus_clk                9      gpio@5d080000            ]             `       N            (        8            K        :                           2fsl,imx8dxl-gpio fsl,imx35-gpio       gpio@5d090000            ]	             `       O            (        8            K        :                           2fsl,imx8dxl-gpio fsl,imx35-gpio       gpio@5d0a0000            ]
             `       P            (        8            K        :                           2fsl,imx8dxl-gpio fsl,imx35-gpio       gpio@5d0b0000            ]             `       Q            (        8            K        :                           2fsl,imx8dxl-gpio fsl,imx35-gpio       gpio@5d0c0000            ]             `       R            (        8            K        :                           2fsl,imx8dxl-gpio fsl,imx35-gpio         okay                <      gpio@5d0d0000            ]             `       S            (        8            K        :                           2fsl,imx8dxl-gpio fsl,imx35-gpio         okay                %      gpio@5d0e0000            ]             `       T            (        8            K        :                           2fsl,imx8dxl-gpio fsl,imx35-gpio       gpio@5d0f0000            ]             `       U            (        8            K        :                           2fsl,imx8dxl-gpio fsl,imx35-gpio       mailbox@5d1b0000             ]             `       V           T         	  disabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1c0000             ]             `       W           T         -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu                      mailbox@5d1d0000             ]             `       X           T         	  disabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1e0000             ]             `       Y           T         	  disabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1f0000             ]             `       Z           T         	  disabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d200000             ]              `       [           T                       	  disabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d210000             ]!             `                  T                       	  disabled          mailbox@5d280000             ](             `                  T                                   clock-controller@5d400000            2fsl,imx8qxp-lpcg             ]@                      4                                 9                                       h  pwm0_lpcg_ipg_clk pwm0_lpcg_ipg_hf_clk pwm0_lpcg_ipg_s_clk pwm0_lpcg_ipg_slv_clk pwm0_lpcg_ipg_mstr_clk                     clock-controller@5d410000            2fsl,imx8qxp-lpcg             ]A                      4                                 9                                       h  pwm1_lpcg_ipg_clk pwm1_lpcg_ipg_hf_clk pwm1_lpcg_ipg_s_clk pwm1_lpcg_ipg_slv_clk pwm1_lpcg_ipg_mstr_clk                     clock-controller@5d420000            2fsl,imx8qxp-lpcg             ]B                      4                                 9                                       h  pwm2_lpcg_ipg_clk pwm2_lpcg_ipg_hf_clk pwm2_lpcg_ipg_s_clk pwm2_lpcg_ipg_slv_clk pwm2_lpcg_ipg_mstr_clk                     clock-controller@5d430000            2fsl,imx8qxp-lpcg             ]C                      4                                 9                                       h  pwm3_lpcg_ipg_clk pwm3_lpcg_ipg_hf_clk pwm3_lpcg_ipg_s_clk pwm3_lpcg_ipg_slv_clk pwm3_lpcg_ipg_mstr_clk                     clock-controller@5d440000            2fsl,imx8qxp-lpcg             ]D                      4                                 9                                       h  pwm4_lpcg_ipg_clk pwm4_lpcg_ipg_hf_clk pwm4_lpcg_ipg_s_clk pwm4_lpcg_ipg_slv_clk pwm4_lpcg_ipg_mstr_clk                     clock-controller@5d450000            2fsl,imx8qxp-lpcg             ]E                      4                                 9                                       h  pwm5_lpcg_ipg_clk pwm5_lpcg_ipg_hf_clk pwm5_lpcg_ipg_s_clk pwm5_lpcg_ipg_slv_clk pwm5_lpcg_ipg_mstr_clk                     clock-controller@5d460000            2fsl,imx8qxp-lpcg             ]F                      4                                 9                                       h  pwm6_lpcg_ipg_clk pwm6_lpcg_ipg_hf_clk pwm6_lpcg_ipg_s_clk pwm6_lpcg_ipg_slv_clk pwm6_lpcg_ipg_mstr_clk                     clock-controller@5d470000            2fsl,imx8qxp-lpcg             ]G                      4                                 9                                       h  pwm7_lpcg_ipg_clk pwm7_lpcg_ipg_hf_clk pwm7_lpcg_ipg_s_clk pwm7_lpcg_ipg_slv_clk pwm7_lpcg_ipg_mstr_clk                        chosen          `/bus@5a000000/serial@5a060000         memory@80000000          memory                      @         regulator-0          2regulator-fixed         f 2Z        ~ 2Z        lmux3_en         {   :                     regulator-1          2regulator-fixed         lfec1_supply         f 2Z        ~ 2Z        {   +                     	  disabled          regulator-2          2regulator-fixed         lfec1_io_supply          f w@        ~ w@        {   ;                                	  disabled          regulator-3          2regulator-fixed       	  lSD1_SPWR            f -        ~ -        {   <                                      $         	interrupt-parent #address-cells #size-cells model compatible ethernet0 ethernet1 gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 mu1 i2c2 mmc0 mmc1 serial0 device_type reg enable-method next-level-cache clocks #cooling-cells operating-points-v2 phandle opp-shared opp-hz opp-microvolt clock-latency-ns opp-suspend #interrupt-cells interrupt-controller interrupts ranges no-map reusable size alloc-ranges linux,cma-default mbox-names mboxes #power-domain-cells wakeup-irq #clock-cells clock-names pinctrl-names pinctrl-0 fsl,pins linux,keycodes wakeup-source timeout-sec #thermal-sensor-cells polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device clock-frequency clock-output-names clock-indices power-domains memory-region status assigned-clocks assigned-clock-rates gpio-controller #gpio-cells bus-width no-sd no-sdio non-removable fsl,tuning-start-tap fsl,tuning-step vmmc-supply cd-gpios wp-gpios fsl,num-tx-queues fsl,num-rx-queues phy-mode phy-handle fsl,magic-packet rx-internal-delay-ps nvmem-cells nvmem-cell-names reset-gpios reset-assert-us qca,disable-smarteee vddio-supply regulator-min-microvolt regulator-max-microvolt interrupt-names eee-broken-1000t qca,disable-hibernation-mode reset-deassert-us fsl,usbphy fsl,usbmisc ahb-burst-config tx-burst-size-dword rx-burst-size-dword #stream-id-cells #index-cells #mbox-cells stdout-path regulator-name gpio regulator-always-on enable-active-high off-on-delay-us 