  f   8  a   (              a                                                                      ,Freescale i.MX8QXP MEK           2fsl,imx8qxp-mek fsl,imx8qxp    aliases           =/bus@5b000000/ethernet@5b040000           G/bus@5b000000/ethernet@5b050000          Q/bus@5d000000/gpio@5d080000          W/bus@5d000000/gpio@5d090000          ]/bus@5d000000/gpio@5d0a0000          c/bus@5d000000/gpio@5d0b0000          i/bus@5d000000/gpio@5d0c0000          o/bus@5d000000/gpio@5d0d0000          u/bus@5d000000/gpio@5d0e0000          {/bus@5d000000/gpio@5d0f0000          /bus@5a000000/i2c@5a800000           /bus@5a000000/i2c@5a810000           /bus@5a000000/i2c@5a820000           /bus@5a000000/i2c@5a830000           /bus@5b000000/mmc@5b010000           /bus@5b000000/mmc@5b020000           /bus@5b000000/mmc@5b030000           /bus@5d000000/mailbox@5d1b0000           /bus@5d000000/mailbox@5d1c0000           /bus@5d000000/mailbox@5d1d0000           /bus@5d000000/mailbox@5d1e0000           /bus@5d000000/mailbox@5d1f0000           /bus@5a000000/serial@5a060000            /bus@5a000000/serial@5a070000            /bus@5a000000/serial@5a080000            /bus@5a000000/serial@5a090000             /vpu@2c000000/vpu-core@2d080000           /vpu@2c000000/vpu-core@2d090000       cpus                                 cpu@0            cpu          2arm,cortex-a35                            psci            
              @        )           6           C   @        U           b           s                z                               cpu@1            cpu          2arm,cortex-a35                           psci            
              @        )           6           C   @        U           b           s                z                         	      cpu@2            cpu          2arm,cortex-a35                           psci            
              @        )           6           C   @        U           b           s                z                         
      cpu@3            cpu          2arm,cortex-a35                           psci            
              @        )           6           C   @        U           b           s                z                               l2-cache0            2cache                                    @        +                       opp-table            2operating-points-v2                        opp-900000000               5          B@         I      opp-1200000000              G                   I                  interrupt-controller@51a00000            2arm,gic-v3                Q             Q                                           	                    reserved-memory                                      decoder-boot@84000000                                   &                 encoder-boot@86000000                                    &                 decoder-rpc@92000000                                    &                 dsp@92400000                 @                  &                 encoder-rpc@94400000                 @       p           &                    pmu          2arm,cortex-a35-pmu                         psci             2arm,psci-1.0            smc       system-controller            2fsl,imx-scu         -tx0 rx0 gip3          $  8                                 power-controller             2fsl,imx8qxp-scu-pd fsl,scu-pd           ?                    clock-controller             2fsl,imx8qxp-clk fsl,scu-clk         S                    pinctrl          2fsl,imx8qxp-iomuxc     fec1grp         `   5          4          &          %          '          (          )          *          ,          -          .          /          0          1                  2      ioexprstgrp         `   Z     !           %      isl29023grp         `   [      !           '      lpi2c1grp           `         !         !           $      lpuart0grp          `   o          p                        usdhc1grp           `   	      A   
       !          !          !          !          !          !          !          !          !          A           +      usdhc2grp         T  `         A          !           !   !       !   "       !   #       !          !           -         ocotp            2fsl,imx8qxp-scu-ocotp                                  keys          "   2fsl,imx8qxp-sc-key fsl,imx-sc-key           i   t        xokay          rtc          2fsl,imx8qxp-sc-rtc        watchdog          "   2fsl,imx8qxp-sc-wdt fsl,imx-sc-wdt              <      thermal-sensor        *   2fsl,imx8qxp-sc-thermal fsl,imx-sc-thermal                                  timer            2arm,armv8-timer       0                                   
         clock-xtal32k            2fixed-clock         S                       xtal_32KHz        clock-xtal24m            2fixed-clock         S            n6         xtal_24MHz        thermal-zones      cpu0-thermal                                      c   trips      trip0                               passive                  trip1                            	   critical             cooling-maps       map0                     0        	   
               pmic-thermal0                                        trips      trip0                               passive                  trip1            H                	   critical             cooling-maps       map0                     0        	   
                  bus@58000000             2simple-bus                                   X       X         clock-img-ipg            2fixed-clock         S                     img_ipg_clk                  jpegdec@58400000             X@           0        5         6         7         8           s                     #per ipg         /                     ?        (  T                                  2nxp,imx8qxp-jpgdec        jpegenc@58450000             XE           0        1         2         3         4           s                     #per ipg         /                     ?        (  T                                  2nxp,imx8qxp-jpgenc        clock-controller@585d0000            2fsl,imx8qxp-lpcg             X]             S           s              b             0  img_jpeg_dec_lpcg_clk img_jpeg_dec_lpcg_ipg_clk         T                      clock-controller@585f0000            2fsl,imx8qxp-lpcg             X_             S           s              b             0  img_jpeg_enc_lpcg_clk img_jpeg_enc_lpcg_ipg_clk         T                         vpu@2c000000                                     ,       ,                   ,                  T             xokay             2nxp,imx8qxp-vpu    mailbox@2d000000             2fsl,imx6sx-mu            -                               p           T             xokay                     mailbox@2d020000             2fsl,imx6sx-mu            -                              p           T             xokay                     vpu-core@2d080000            -              2nxp,imx8q-vpu-decoder           T             -tx0 tx1 rx        $  8                                       xokay            |            vpu-core@2d090000            -              2nxp,imx8q-vpu-encoder           T             -tx0 tx1 rx        $  8                                       xokay            |               bus@59000000             2simple-bus                                   Y       Y         clock-audio-ipg          2fixed-clock         S            '         audio_ipg_clk                    clock-controller@59580000            2fsl,imx8qxp-lpcg             YX             S           s                 b               4  dsp_lpcg_adb_clk dsp_lpcg_ipg_clk dsp_lpcg_core_clk         T                       clock-controller@59590000            2fsl,imx8qxp-lpcg             YY             S           s           b           dsp_ram_lpcg_ipg_clk            T                      dsp@596e8000             2fsl,imx8qxp-dsp          Yn           s                          #ipg ocram core           T                               -txdb0 txdb1 rxdb0 rxdb1       0  8                                              |           xokay             bus@5a000000             2simple-bus                                   Z       Z         clock-dma-ipg            2fixed-clock         S            '         dma_ipg_clk            !      serial@5a060000          Z                               s                   	  #ipg baud            /      9           ?Ĵ         T      9        xokay             2fsl,imx8qxp-lpuart          default                  serial@5a070000          Z                               s                   	  #ipg baud            /      :           ?Ĵ         T      :      	  xdisabled             2fsl,imx8qxp-lpuart        serial@5a080000          Z                               s                   	  #ipg baud            /      ;           ?Ĵ         T      ;      	  xdisabled             2fsl,imx8qxp-lpuart        serial@5a090000          Z	                               s                     	  #ipg baud            /      <           ?Ĵ         T      <      	  xdisabled             2fsl,imx8qxp-lpuart        clock-controller@5a460000            2fsl,imx8qxp-lpcg             ZF             S           s      9      !        b             '  uart0_lpcg_baud_clk uart0_lpcg_ipg_clk          T      9                 clock-controller@5a470000            2fsl,imx8qxp-lpcg             ZG             S           s      :      !        b             '  uart1_lpcg_baud_clk uart1_lpcg_ipg_clk          T      :                 clock-controller@5a480000            2fsl,imx8qxp-lpcg             ZH             S           s      ;      !        b             '  uart2_lpcg_baud_clk uart2_lpcg_ipg_clk          T      ;                 clock-controller@5a490000            2fsl,imx8qxp-lpcg             ZI             S           s      <      !        b             '  uart3_lpcg_baud_clk uart3_lpcg_ipg_clk          T      <                  i2c@5a800000             Z    @                           s   "       "           #per ipg         /      `           ?n6         T      `      	  xdisabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       i2c@5a810000             Z    @                           s   #       #           #per ipg         /      a           ?n6         T      a        xokay          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c                                            default            $   %   i2c-mux@71           2nxp,pca9646 nxp,pca9546                                       q           &         i2c@0                                             gpio@68          2maxim,max7322               h                             i2c@1                                               i2c@2                                            pressure-sensor@60           2fsl,mpl3115             `         i2c@3                                            gpio@1a          2nxp,pca9557                                       gpio@1d          2nxp,pca9557                                       light-sensor@44         default            '         2isil,isl29023               D             &                             i2c@5a820000             Z    @                           s   (       (           #per ipg         /      b           ?n6         T      b      	  xdisabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       i2c@5a830000             Z    @                           s   )       )           #per ipg         /      c           ?n6         T      c      	  xdisabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       clock-controller@5ac00000            2fsl,imx8qxp-lpcg             Z             S           s      `      !        b                i2c0_lpcg_clk i2c0_lpcg_ipg_clk         T      `           "      clock-controller@5ac10000            2fsl,imx8qxp-lpcg             Z             S           s      a      !        b                i2c1_lpcg_clk i2c1_lpcg_ipg_clk         T      a           #      clock-controller@5ac20000            2fsl,imx8qxp-lpcg             Z             S           s      b      !        b                i2c2_lpcg_clk i2c2_lpcg_ipg_clk         T      b           (      clock-controller@5ac30000            2fsl,imx8qxp-lpcg             Z             S           s      c      !        b                i2c3_lpcg_clk i2c3_lpcg_ipg_clk         T      c           )         bus@5b000000             2simple-bus                                   [       [         clock-conn-axi           2fixed-clock         S            CU        conn_axi_clk               6      clock-conn-ahb           2fixed-clock         S            	!        conn_ahb_clk          clock-conn-ipg           2fixed-clock         S                    conn_ipg_clk               5      mmc@5b010000                               [             s   *      *      *            #ipg ahb per         T              xokay          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc           /                 ?         default            +                                            mmc@5b020000                               [             s   ,      ,      ,            #ipg ahb per         T                                    xokay          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc           /                 ?         default            -                      .        !   /              *   /             mmc@5b030000                               [             s   0      0      0            #ipg ahb per         T            	  xdisabled          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc         ethernet@5b040000            [           0                                                s   1      1      1      1            #ipg ahb enet_clk_ref ptp            /                          ?沀sY@        3           E           T              xokay          .   2fsl,imx8qxp-fec fsl,imx8qm-fec fsl,imx6sx-fec           default            2      	  Wrgmii-id            `   3         k   mdio                                 ethernet-phy@0           2ethernet-phy-ieee802.3-c22                          3            ethernet@5b050000            [           0                                               s   4      4      4      4            #ipg ahb enet_clk_ref ptp            /                          ?沀sY@        3           E           T            	  xdisabled          .   2fsl,imx8qxp-fec fsl,imx8qm-fec fsl,imx6sx-fec         clock-controller@5b200000            2fsl,imx8qxp-lpcg             [              S           s            5   6        b                9  sdhc0_lpcg_per_clk sdhc0_lpcg_ipg_clk sdhc0_lpcg_ahb_clk            T                 *      clock-controller@5b210000            2fsl,imx8qxp-lpcg             [!             S           s            5   6        b                9  sdhc1_lpcg_per_clk sdhc1_lpcg_ipg_clk sdhc1_lpcg_ahb_clk            T                 ,      clock-controller@5b220000            2fsl,imx8qxp-lpcg             ["             S           s            5   6        b                9  sdhc2_lpcg_per_clk sdhc2_lpcg_ipg_clk sdhc2_lpcg_ahb_clk            T                 0      clock-controller@5b230000            2fsl,imx8qxp-lpcg             [#             S         0  s                     6            5   5        b                           enet0_lpcg_timer_clk enet0_lpcg_txc_sampling_clk enet0_lpcg_ahb_clk enet0_lpcg_rgmii_txc_clk enet0_lpcg_ipg_clk enet0_lpcg_ipg_s_clk            T                 1      clock-controller@5b240000            2fsl,imx8qxp-lpcg             [$             S         0  s                     6            5   5        b                           enet1_lpcg_timer_clk enet1_lpcg_txc_sampling_clk enet1_lpcg_ahb_clk enet1_lpcg_rgmii_txc_clk enet1_lpcg_ipg_clk enet1_lpcg_ipg_s_clk            T                 4         bus@5c000000             2simple-bus                                   \       \         ddr-pmu@5c020000             2fsl,imx8-ddr-pmu             \                                bus@5d000000             2simple-bus                                   ]       ]         clock-lsio-mem           2fixed-clock         S                     lsio_mem_clk          clock-lsio-bus           2fixed-clock         S                     lsio_bus_clk               7      gpio@5d080000            ]                                                                       T                2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d090000            ]	                                                                       T                2fsl,imx8qxp-gpio fsl,imx35-gpio            &      gpio@5d0a0000            ]
                                                                       T                2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0b0000            ]                                                                       T                2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0c0000            ]                                                                       T                2fsl,imx8qxp-gpio fsl,imx35-gpio            /      gpio@5d0d0000            ]                                                                       T                2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0e0000            ]                                                                       T                2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0f0000            ]                                                                       T                2fsl,imx8qxp-gpio fsl,imx35-gpio       mailbox@5d1b0000             ]                               p         	  xdisabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1c0000             ]                               p         -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu                     mailbox@5d1d0000             ]                               p         	  xdisabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1e0000             ]                               p         	  xdisabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1f0000             ]                               p         	  xdisabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d200000             ]                                p           T            	  xdisabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d210000             ]!                               p           T            	  xdisabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d280000             ](                               p           T               2fsl,imx8qxp-mu fsl,imx6sx-mu                     clock-controller@5d400000            2fsl,imx8qxp-lpcg             ]@             S         4  s                              7                 b                      h  pwm0_lpcg_ipg_clk pwm0_lpcg_ipg_hf_clk pwm0_lpcg_ipg_s_clk pwm0_lpcg_ipg_slv_clk pwm0_lpcg_ipg_mstr_clk         T            clock-controller@5d410000            2fsl,imx8qxp-lpcg             ]A             S         4  s                              7                 b                      h  pwm1_lpcg_ipg_clk pwm1_lpcg_ipg_hf_clk pwm1_lpcg_ipg_s_clk pwm1_lpcg_ipg_slv_clk pwm1_lpcg_ipg_mstr_clk         T            clock-controller@5d420000            2fsl,imx8qxp-lpcg             ]B             S         4  s                              7                 b                      h  pwm2_lpcg_ipg_clk pwm2_lpcg_ipg_hf_clk pwm2_lpcg_ipg_s_clk pwm2_lpcg_ipg_slv_clk pwm2_lpcg_ipg_mstr_clk         T            clock-controller@5d430000            2fsl,imx8qxp-lpcg             ]C             S         4  s                              7                 b                      h  pwm3_lpcg_ipg_clk pwm3_lpcg_ipg_hf_clk pwm3_lpcg_ipg_s_clk pwm3_lpcg_ipg_slv_clk pwm3_lpcg_ipg_mstr_clk         T            clock-controller@5d440000            2fsl,imx8qxp-lpcg             ]D             S         4  s                              7                 b                      h  pwm4_lpcg_ipg_clk pwm4_lpcg_ipg_hf_clk pwm4_lpcg_ipg_s_clk pwm4_lpcg_ipg_slv_clk pwm4_lpcg_ipg_mstr_clk         T            clock-controller@5d450000            2fsl,imx8qxp-lpcg             ]E             S         4  s                              7                 b                      h  pwm5_lpcg_ipg_clk pwm5_lpcg_ipg_hf_clk pwm5_lpcg_ipg_s_clk pwm5_lpcg_ipg_slv_clk pwm5_lpcg_ipg_mstr_clk         T            clock-controller@5d460000            2fsl,imx8qxp-lpcg             ]F             S         4  s                              7                 b                      h  pwm6_lpcg_ipg_clk pwm6_lpcg_ipg_hf_clk pwm6_lpcg_ipg_s_clk pwm6_lpcg_ipg_slv_clk pwm6_lpcg_ipg_mstr_clk         T            clock-controller@5d470000            2fsl,imx8qxp-lpcg             ]G             S         4  s                              7                 b                      h  pwm7_lpcg_ipg_clk pwm7_lpcg_ipg_hf_clk pwm7_lpcg_ipg_s_clk pwm7_lpcg_ipg_slv_clk pwm7_lpcg_ipg_mstr_clk         T               chosen          |/bus@5a000000/serial@5a060000         memory@80000000          memory                      @         usdhc2-vmmc          2regulator-fixed       	  SD1_SPWR             -         -           /                           .         	interrupt-parent #address-cells #size-cells model compatible ethernet0 ethernet1 gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 i2c0 i2c1 i2c2 i2c3 mmc0 mmc1 mmc2 mu0 mu1 mu2 mu3 mu4 serial0 serial1 serial2 serial3 vpu-core0 vpu-core1 device_type reg enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache clocks operating-points-v2 #cooling-cells phandle cache-level opp-shared opp-hz opp-microvolt clock-latency-ns opp-suspend #interrupt-cells interrupt-controller interrupts ranges no-map mbox-names mboxes #power-domain-cells #clock-cells fsl,pins linux,keycodes status timeout-sec #thermal-sensor-cells clock-frequency clock-output-names polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device clock-names assigned-clocks assigned-clock-rates power-domains clock-indices #mbox-cells memory-region pinctrl-names pinctrl-0 reset-gpios gpio-controller #gpio-cells bus-width no-sd no-sdio non-removable fsl,tuning-start-tap fsl,tuning-step vmmc-supply cd-gpios wp-gpios fsl,num-tx-queues fsl,num-rx-queues phy-mode phy-handle fsl,magic-packet stdout-path regulator-name regulator-min-microvolt regulator-max-microvolt gpio enable-active-high 