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Macros | |
#define | CPU_ID_IMPLEMENTOR_MASK 0xff000000 |
#define | CPU_ID_ARM_LTD 0x41000000 /* 'A' */ |
#define | CPU_ID_BROADCOM 0x42000000 /* 'B' */ |
#define | CPU_ID_CAVIUM 0x43000000 /* 'C' */ |
#define | CPU_ID_DEC 0x44000000 /* 'D' */ |
#define | CPU_ID_INFINEON 0x49000000 /* 'I' */ |
#define | CPU_ID_MOTOROLA 0x4d000000 /* 'M' */ |
#define | CPU_ID_NVIDIA 0x4e000000 /* 'N' */ |
#define | CPU_ID_APM 0x50000000 /* 'P' */ |
#define | CPU_ID_QUALCOMM 0x51000000 /* 'Q' */ |
#define | CPU_ID_SAMSUNG 0x53000000 /* 'S' */ |
#define | CPU_ID_TI 0x54000000 /* 'T' */ |
#define | CPU_ID_MARVELL 0x56000000 /* 'V' */ |
#define | CPU_ID_APPLE 0x61000000 /* 'a' */ |
#define | CPU_ID_FARADAY 0x66000000 /* 'f' */ |
#define | CPU_ID_INTEL 0x69000000 /* 'i' */ |
#define | CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) |
#define | CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) |
#define | CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) |
#define | CPU_ID_FOUNDRY_MASK 0x00ff0000 |
#define | CPU_ID_FOUNDRY_VLSI 0x00560000 |
#define | CPU_ID_7ARCH_MASK 0x00800000 |
#define | CPU_ID_7ARCH_V3 0x00000000 |
#define | CPU_ID_7ARCH_V4T 0x00800000 |
#define | CPU_ID_7VARIANT_MASK 0x007f0000 |
#define | CPU_ID_ARCH_MASK 0x000f0000 |
#define | CPU_ID_ARCH_V3 0x00000000 |
#define | CPU_ID_ARCH_V4 0x00010000 |
#define | CPU_ID_ARCH_V4T 0x00020000 |
#define | CPU_ID_ARCH_V5 0x00030000 |
#define | CPU_ID_ARCH_V5T 0x00040000 |
#define | CPU_ID_ARCH_V5TE 0x00050000 |
#define | CPU_ID_ARCH_V5TEJ 0x00060000 |
#define | CPU_ID_ARCH_V6 0x00070000 |
#define | CPU_ID_VARIANT_MASK 0x00f00000 |
#define | CPU_ID_PARTNO_MASK 0x0000fff0 |
#define | CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ |
#define | CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ |
#define | CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ |
#define | CPU_ID_REVISION_MASK 0x0000000f |
#define | CPU_ID_CPU_MASK 0xfffffff0 |
#define | CPU_ID_ARM2 0x41560200 |
#define | CPU_ID_ARM250 0x41560250 |
#define | CPU_ID_ARM3 0x41560300 |
#define | CPU_ID_ARM600 0x41560600 |
#define | CPU_ID_ARM610 0x41560610 |
#define | CPU_ID_ARM620 0x41560620 |
#define | CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ |
#define | CPU_ID_ARM710 0x41007100 |
#define | CPU_ID_ARM7500 0x41027100 |
#define | CPU_ID_ARM710A 0x41067100 |
#define | CPU_ID_ARM7500FE 0x41077100 |
#define | CPU_ID_ARM710T 0x41807100 |
#define | CPU_ID_ARM720T 0x41807200 |
#define | CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ |
#define | CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ |
#define | CPU_ID_ARM810 0x41018100 |
#define | CPU_ID_ARM920T 0x41129200 |
#define | CPU_ID_ARM922T 0x41029220 |
#define | CPU_ID_ARM926EJS 0x41069260 |
#define | CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ |
#define | CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ |
#define | CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ |
#define | CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ |
#define | CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ |
#define | CPU_ID_ARM1022ES 0x4105a220 |
#define | CPU_ID_ARM1026EJS 0x4106a260 |
#define | CPU_ID_ARM11MPCORE 0x410fb020 |
#define | CPU_ID_ARM1136JS 0x4107b360 |
#define | CPU_ID_ARM1136JSR1 0x4117b360 |
#define | CPU_ID_ARM1156T2S 0x4107b560 /* MPU only */ |
#define | CPU_ID_ARM1176JZS 0x410fb760 |
#define | CPU_ID_ARM11_P(n) ((n & 0xff07f000) == 0x4107b000) |
#define | CPU_ID_CORTEXA5R0 0x410fc050 |
#define | CPU_ID_CORTEXA7R0 0x410fc070 |
#define | CPU_ID_CORTEXA8R1 0x411fc080 |
#define | CPU_ID_CORTEXA8R2 0x412fc080 |
#define | CPU_ID_CORTEXA8R3 0x413fc080 |
#define | CPU_ID_CORTEXA9R1 0x411fc090 |
#define | CPU_ID_CORTEXA9R2 0x412fc090 |
#define | CPU_ID_CORTEXA9R3 0x413fc090 |
#define | CPU_ID_CORTEXA9R4 0x414fc090 |
#define | CPU_ID_CORTEXA15R2 0x412fc0f0 |
#define | CPU_ID_CORTEXA15R3 0x413fc0f0 |
#define | CPU_ID_CORTEXA17R1 0x411fc0e0 |
#define | CPU_ID_CORTEXA35R0 0x410fd040 |
#define | CPU_ID_CORTEXA53R0 0x410fd030 |
#define | CPU_ID_CORTEXA55R1 0x411fd050 |
#define | CPU_ID_CORTEXA57R0 0x410fd070 |
#define | CPU_ID_CORTEXA57R1 0x411fd070 |
#define | CPU_ID_CORTEXA72R0 0x410fd080 |
#define | CPU_ID_CORTEXA73R0 0x410fd090 |
#define | CPU_ID_CORTEXA75R2 0x412fd0a0 |
#define | CPU_ID_CORTEX_P(n) ((n & 0xff0fe000) == 0x410fc000) |
#define | CPU_ID_CORTEX_A5_P(n) ((n & 0xff0ff0f0) == 0x410fc050) |
#define | CPU_ID_CORTEX_A7_P(n) ((n & 0xff0ff0f0) == 0x410fc070) |
#define | CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080) |
#define | CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090) |
#define | CPU_ID_CORTEX_A15_P(n) ((n & 0xff0ff0f0) == 0x410fc0f0) |
#define | CPU_ID_CORTEX_A35_P(n) ((n & 0xff0ff0f0) == 0x410fd040) |
#define | CPU_ID_CORTEX_A53_P(n) ((n & 0xff0ff0f0) == 0x410fd030) |
#define | CPU_ID_CORTEX_A55_P(n) ((n & 0xff0ff0f0) == 0x410fd050) |
#define | CPU_ID_CORTEX_A57_P(n) ((n & 0xff0ff0f0) == 0x410fd070) |
#define | CPU_ID_CORTEX_A72_P(n) ((n & 0xff0ff0f0) == 0x410fd080) |
#define | CPU_ID_CORTEX_A73_P(n) ((n & 0xff0ff0f0) == 0x410fd090) |
#define | CPU_ID_CORTEX_A75_P(n) ((n & 0xff0ff0f0) == 0x410fd0a0) |
#define | CPU_ID_SA110 0x4401a100 |
#define | CPU_ID_SA1100 0x4401a110 |
#define | CPU_ID_TI925T 0x54029250 |
#define | CPU_ID_MV88FR571_VD 0x56155710 |
#define | CPU_ID_MV88SV131 0x56251310 |
#define | CPU_ID_FA526 0x66015260 |
#define | CPU_ID_SA1110 0x6901b110 |
#define | CPU_ID_IXP1200 0x6901c120 |
#define | CPU_ID_80200 0x69052000 |
#define | CPU_ID_PXA250 0x69052100 /* sans core revision */ |
#define | CPU_ID_PXA210 0x69052120 |
#define | CPU_ID_PXA250A 0x69052100 /* 1st version Core */ |
#define | CPU_ID_PXA210A 0x69052120 /* 1st version Core */ |
#define | CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ |
#define | CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ |
#define | CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ |
#define | CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ |
#define | CPU_ID_PXA27X 0x69054110 |
#define | CPU_ID_80321_400 0x69052420 |
#define | CPU_ID_80321_600 0x69052430 |
#define | CPU_ID_80321_400_B0 0x69052c20 |
#define | CPU_ID_80321_600_B0 0x69052c30 |
#define | CPU_ID_80321_600_2 0x69052c32 |
#define | CPU_ID_80219_400 0x69052e20 |
#define | CPU_ID_80219_600 0x69052e30 |
#define | CPU_ID_IXP425_533 0x690541c0 |
#define | CPU_ID_IXP425_400 0x690541d0 |
#define | CPU_ID_IXP425_266 0x690541f0 |
#define | CPU_ID_MV88SV58XX_P(n) ((n & 0xff0fff00) == 0x560f5800) |
#define | CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */ |
#define | CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */ |
#define | CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */ |
#define | CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */ |
#define | CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ |
#define | CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */ |
#define | CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */ |
#define CPU_ID_7ARCH_MASK 0x00800000 |
Definition at line 76 of file arm_cputypes.h.
#define CPU_ID_7ARCH_V3 0x00000000 |
Definition at line 77 of file arm_cputypes.h.
#define CPU_ID_7ARCH_V4T 0x00800000 |
Definition at line 78 of file arm_cputypes.h.
#define CPU_ID_7VARIANT_MASK 0x007f0000 |
Definition at line 79 of file arm_cputypes.h.
#define CPU_ID_80200 0x69052000 |
Definition at line 188 of file arm_cputypes.h.
#define CPU_ID_80219_400 0x69052e20 |
Definition at line 203 of file arm_cputypes.h.
#define CPU_ID_80219_600 0x69052e30 |
Definition at line 204 of file arm_cputypes.h.
#define CPU_ID_80321_400 0x69052420 |
Definition at line 198 of file arm_cputypes.h.
#define CPU_ID_80321_400_B0 0x69052c20 |
Definition at line 200 of file arm_cputypes.h.
#define CPU_ID_80321_600 0x69052430 |
Definition at line 199 of file arm_cputypes.h.
#define CPU_ID_80321_600_2 0x69052c32 |
Definition at line 202 of file arm_cputypes.h.
#define CPU_ID_80321_600_B0 0x69052c30 |
Definition at line 201 of file arm_cputypes.h.
#define CPU_ID_APM 0x50000000 /* 'P' */ |
Definition at line 57 of file arm_cputypes.h.
#define CPU_ID_APPLE 0x61000000 /* 'a' */ |
Definition at line 62 of file arm_cputypes.h.
#define CPU_ID_ARCH_MASK 0x000f0000 |
Definition at line 82 of file arm_cputypes.h.
#define CPU_ID_ARCH_V3 0x00000000 |
Definition at line 83 of file arm_cputypes.h.
#define CPU_ID_ARCH_V4 0x00010000 |
Definition at line 84 of file arm_cputypes.h.
#define CPU_ID_ARCH_V4T 0x00020000 |
Definition at line 85 of file arm_cputypes.h.
#define CPU_ID_ARCH_V5 0x00030000 |
Definition at line 86 of file arm_cputypes.h.
#define CPU_ID_ARCH_V5T 0x00040000 |
Definition at line 87 of file arm_cputypes.h.
#define CPU_ID_ARCH_V5TE 0x00050000 |
Definition at line 88 of file arm_cputypes.h.
#define CPU_ID_ARCH_V5TEJ 0x00060000 |
Definition at line 89 of file arm_cputypes.h.
#define CPU_ID_ARCH_V6 0x00070000 |
Definition at line 90 of file arm_cputypes.h.
#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ |
Definition at line 137 of file arm_cputypes.h.
#define CPU_ID_ARM1022ES 0x4105a220 |
Definition at line 138 of file arm_cputypes.h.
#define CPU_ID_ARM1026EJS 0x4106a260 |
Definition at line 139 of file arm_cputypes.h.
#define CPU_ID_ARM1136JS 0x4107b360 |
Definition at line 141 of file arm_cputypes.h.
#define CPU_ID_ARM1136JSR1 0x4117b360 |
Definition at line 142 of file arm_cputypes.h.
#define CPU_ID_ARM1156T2S 0x4107b560 /* MPU only */ |
Definition at line 143 of file arm_cputypes.h.
#define CPU_ID_ARM1176JZS 0x410fb760 |
Definition at line 144 of file arm_cputypes.h.
#define CPU_ID_ARM11_P | ( | n | ) | ((n & 0xff07f000) == 0x4107b000) |
Definition at line 145 of file arm_cputypes.h.
#define CPU_ID_ARM11MPCORE 0x410fb020 |
Definition at line 140 of file arm_cputypes.h.
#define CPU_ID_ARM2 0x41560200 |
Definition at line 108 of file arm_cputypes.h.
#define CPU_ID_ARM250 0x41560250 |
Definition at line 109 of file arm_cputypes.h.
#define CPU_ID_ARM3 0x41560300 |
Definition at line 112 of file arm_cputypes.h.
#define CPU_ID_ARM600 0x41560600 |
Definition at line 113 of file arm_cputypes.h.
#define CPU_ID_ARM610 0x41560610 |
Definition at line 114 of file arm_cputypes.h.
#define CPU_ID_ARM620 0x41560620 |
Definition at line 115 of file arm_cputypes.h.
#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ |
Definition at line 118 of file arm_cputypes.h.
#define CPU_ID_ARM710 0x41007100 |
Definition at line 119 of file arm_cputypes.h.
#define CPU_ID_ARM710A 0x41067100 |
Definition at line 121 of file arm_cputypes.h.
#define CPU_ID_ARM710T 0x41807100 |
Definition at line 123 of file arm_cputypes.h.
#define CPU_ID_ARM720T 0x41807200 |
Definition at line 124 of file arm_cputypes.h.
#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ |
Definition at line 126 of file arm_cputypes.h.
#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ |
Definition at line 125 of file arm_cputypes.h.
#define CPU_ID_ARM7500 0x41027100 |
Definition at line 120 of file arm_cputypes.h.
#define CPU_ID_ARM7500FE 0x41077100 |
Definition at line 122 of file arm_cputypes.h.
#define CPU_ID_ARM810 0x41018100 |
Definition at line 129 of file arm_cputypes.h.
#define CPU_ID_ARM920T 0x41129200 |
Definition at line 130 of file arm_cputypes.h.
#define CPU_ID_ARM922T 0x41029220 |
Definition at line 131 of file arm_cputypes.h.
#define CPU_ID_ARM926EJS 0x41069260 |
Definition at line 132 of file arm_cputypes.h.
#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ |
Definition at line 133 of file arm_cputypes.h.
#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ |
Definition at line 134 of file arm_cputypes.h.
#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ |
Definition at line 135 of file arm_cputypes.h.
#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ |
Definition at line 136 of file arm_cputypes.h.
#define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ |
Definition at line 214 of file arm_cputypes.h.
#define CPU_ID_ARM_88SV581X_V7 0x413fc080 /* Marvell Sheeva 88SV581x v7 Core */ |
Definition at line 215 of file arm_cputypes.h.
#define CPU_ID_ARM_88SV584X_V6 0x410fb020 /* Marvell Sheeva 88SV584x v6 Core */ |
Definition at line 216 of file arm_cputypes.h.
#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ |
Definition at line 50 of file arm_cputypes.h.
#define CPU_ID_BROADCOM 0x42000000 /* 'B' */ |
Definition at line 51 of file arm_cputypes.h.
#define CPU_ID_CAVIUM 0x43000000 /* 'C' */ |
Definition at line 52 of file arm_cputypes.h.
#define CPU_ID_CORTEX_A15_P | ( | n | ) | ((n & 0xff0ff0f0) == 0x410fc0f0) |
Definition at line 172 of file arm_cputypes.h.
#define CPU_ID_CORTEX_A35_P | ( | n | ) | ((n & 0xff0ff0f0) == 0x410fd040) |
Definition at line 173 of file arm_cputypes.h.
#define CPU_ID_CORTEX_A53_P | ( | n | ) | ((n & 0xff0ff0f0) == 0x410fd030) |
Definition at line 174 of file arm_cputypes.h.
#define CPU_ID_CORTEX_A55_P | ( | n | ) | ((n & 0xff0ff0f0) == 0x410fd050) |
Definition at line 175 of file arm_cputypes.h.
#define CPU_ID_CORTEX_A57_P | ( | n | ) | ((n & 0xff0ff0f0) == 0x410fd070) |
Definition at line 176 of file arm_cputypes.h.
#define CPU_ID_CORTEX_A5_P | ( | n | ) | ((n & 0xff0ff0f0) == 0x410fc050) |
Definition at line 168 of file arm_cputypes.h.
#define CPU_ID_CORTEX_A72_P | ( | n | ) | ((n & 0xff0ff0f0) == 0x410fd080) |
Definition at line 177 of file arm_cputypes.h.
#define CPU_ID_CORTEX_A73_P | ( | n | ) | ((n & 0xff0ff0f0) == 0x410fd090) |
Definition at line 178 of file arm_cputypes.h.
#define CPU_ID_CORTEX_A75_P | ( | n | ) | ((n & 0xff0ff0f0) == 0x410fd0a0) |
Definition at line 179 of file arm_cputypes.h.
#define CPU_ID_CORTEX_A7_P | ( | n | ) | ((n & 0xff0ff0f0) == 0x410fc070) |
Definition at line 169 of file arm_cputypes.h.
#define CPU_ID_CORTEX_A8_P | ( | n | ) | ((n & 0xff0ff0f0) == 0x410fc080) |
Definition at line 170 of file arm_cputypes.h.
#define CPU_ID_CORTEX_A9_P | ( | n | ) | ((n & 0xff0ff0f0) == 0x410fc090) |
Definition at line 171 of file arm_cputypes.h.
#define CPU_ID_CORTEX_P | ( | n | ) | ((n & 0xff0fe000) == 0x410fc000) |
Definition at line 167 of file arm_cputypes.h.
#define CPU_ID_CORTEXA15R2 0x412fc0f0 |
Definition at line 155 of file arm_cputypes.h.
#define CPU_ID_CORTEXA15R3 0x413fc0f0 |
Definition at line 156 of file arm_cputypes.h.
#define CPU_ID_CORTEXA17R1 0x411fc0e0 |
Definition at line 157 of file arm_cputypes.h.
#define CPU_ID_CORTEXA35R0 0x410fd040 |
Definition at line 158 of file arm_cputypes.h.
#define CPU_ID_CORTEXA53R0 0x410fd030 |
Definition at line 159 of file arm_cputypes.h.
#define CPU_ID_CORTEXA55R1 0x411fd050 |
Definition at line 160 of file arm_cputypes.h.
#define CPU_ID_CORTEXA57R0 0x410fd070 |
Definition at line 161 of file arm_cputypes.h.
#define CPU_ID_CORTEXA57R1 0x411fd070 |
Definition at line 162 of file arm_cputypes.h.
#define CPU_ID_CORTEXA5R0 0x410fc050 |
Definition at line 146 of file arm_cputypes.h.
#define CPU_ID_CORTEXA72R0 0x410fd080 |
Definition at line 163 of file arm_cputypes.h.
#define CPU_ID_CORTEXA73R0 0x410fd090 |
Definition at line 164 of file arm_cputypes.h.
#define CPU_ID_CORTEXA75R2 0x412fd0a0 |
Definition at line 165 of file arm_cputypes.h.
#define CPU_ID_CORTEXA7R0 0x410fc070 |
Definition at line 147 of file arm_cputypes.h.
#define CPU_ID_CORTEXA8R1 0x411fc080 |
Definition at line 148 of file arm_cputypes.h.
#define CPU_ID_CORTEXA8R2 0x412fc080 |
Definition at line 149 of file arm_cputypes.h.
#define CPU_ID_CORTEXA8R3 0x413fc080 |
Definition at line 150 of file arm_cputypes.h.
#define CPU_ID_CORTEXA9R1 0x411fc090 |
Definition at line 151 of file arm_cputypes.h.
#define CPU_ID_CORTEXA9R2 0x412fc090 |
Definition at line 152 of file arm_cputypes.h.
#define CPU_ID_CORTEXA9R3 0x413fc090 |
Definition at line 153 of file arm_cputypes.h.
#define CPU_ID_CORTEXA9R4 0x414fc090 |
Definition at line 154 of file arm_cputypes.h.
#define CPU_ID_CPU_MASK 0xfffffff0 |
Definition at line 105 of file arm_cputypes.h.
#define CPU_ID_DEC 0x44000000 /* 'D' */ |
Definition at line 53 of file arm_cputypes.h.
#define CPU_ID_FA526 0x66015260 |
Definition at line 185 of file arm_cputypes.h.
#define CPU_ID_FARADAY 0x66000000 /* 'f' */ |
Definition at line 63 of file arm_cputypes.h.
#define CPU_ID_FOUNDRY_MASK 0x00ff0000 |
Definition at line 72 of file arm_cputypes.h.
#define CPU_ID_FOUNDRY_VLSI 0x00560000 |
Definition at line 73 of file arm_cputypes.h.
#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 |
Definition at line 49 of file arm_cputypes.h.
#define CPU_ID_INFINEON 0x49000000 /* 'I' */ |
Definition at line 54 of file arm_cputypes.h.
#define CPU_ID_INTEL 0x69000000 /* 'i' */ |
Definition at line 64 of file arm_cputypes.h.
#define CPU_ID_IS7 | ( | x | ) | (((x) & 0x0000f000) == 0x00007000) |
Definition at line 68 of file arm_cputypes.h.
#define CPU_ID_ISNEW | ( | x | ) | (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) |
Definition at line 69 of file arm_cputypes.h.
#define CPU_ID_ISOLD | ( | x | ) | (((x) & 0x0000f000) == 0x00000000) |
Definition at line 67 of file arm_cputypes.h.
#define CPU_ID_IXP1200 0x6901c120 |
Definition at line 187 of file arm_cputypes.h.
#define CPU_ID_IXP425_266 0x690541f0 |
Definition at line 207 of file arm_cputypes.h.
#define CPU_ID_IXP425_400 0x690541d0 |
Definition at line 206 of file arm_cputypes.h.
#define CPU_ID_IXP425_533 0x690541c0 |
Definition at line 205 of file arm_cputypes.h.
#define CPU_ID_MARVELL 0x56000000 /* 'V' */ |
Definition at line 61 of file arm_cputypes.h.
#define CPU_ID_MOTOROLA 0x4d000000 /* 'M' */ |
Definition at line 55 of file arm_cputypes.h.
#define CPU_ID_MV88FR571_VD 0x56155710 |
Definition at line 183 of file arm_cputypes.h.
#define CPU_ID_MV88SV131 0x56251310 |
Definition at line 184 of file arm_cputypes.h.
#define CPU_ID_MV88SV581X_V6 0x560f5810 /* Marvell Sheeva 88SV581x v6 Core */ |
Definition at line 209 of file arm_cputypes.h.
#define CPU_ID_MV88SV581X_V7 0x561f5810 /* Marvell Sheeva 88SV581x v7 Core */ |
Definition at line 210 of file arm_cputypes.h.
#define CPU_ID_MV88SV584X_V6 0x561f5840 /* Marvell Sheeva 88SV584x v6 Core */ |
Definition at line 211 of file arm_cputypes.h.
#define CPU_ID_MV88SV584X_V7 0x562f5840 /* Marvell Sheeva 88SV584x v7 Core */ |
Definition at line 212 of file arm_cputypes.h.
#define CPU_ID_MV88SV58XX_P | ( | n | ) | ((n & 0xff0fff00) == 0x560f5800) |
Definition at line 208 of file arm_cputypes.h.
#define CPU_ID_NVIDIA 0x4e000000 /* 'N' */ |
Definition at line 56 of file arm_cputypes.h.
#define CPU_ID_PARTNO_MASK 0x0000fff0 |
Definition at line 94 of file arm_cputypes.h.
#define CPU_ID_PXA210 0x69052120 |
Definition at line 190 of file arm_cputypes.h.
#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ |
Definition at line 192 of file arm_cputypes.h.
#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ |
Definition at line 194 of file arm_cputypes.h.
#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ |
Definition at line 196 of file arm_cputypes.h.
#define CPU_ID_PXA250 0x69052100 /* sans core revision */ |
Definition at line 189 of file arm_cputypes.h.
#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ |
Definition at line 191 of file arm_cputypes.h.
#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ |
Definition at line 193 of file arm_cputypes.h.
#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ |
Definition at line 195 of file arm_cputypes.h.
#define CPU_ID_PXA27X 0x69054110 |
Definition at line 197 of file arm_cputypes.h.
#define CPU_ID_QUALCOMM 0x51000000 /* 'Q' */ |
Definition at line 58 of file arm_cputypes.h.
#define CPU_ID_REVISION_MASK 0x0000000f |
Definition at line 102 of file arm_cputypes.h.
#define CPU_ID_SA110 0x4401a100 |
Definition at line 180 of file arm_cputypes.h.
#define CPU_ID_SA1100 0x4401a110 |
Definition at line 181 of file arm_cputypes.h.
#define CPU_ID_SA1110 0x6901b110 |
Definition at line 186 of file arm_cputypes.h.
#define CPU_ID_SAMSUNG 0x53000000 /* 'S' */ |
Definition at line 59 of file arm_cputypes.h.
#define CPU_ID_TI 0x54000000 /* 'T' */ |
Definition at line 60 of file arm_cputypes.h.
#define CPU_ID_TI925T 0x54029250 |
Definition at line 182 of file arm_cputypes.h.
#define CPU_ID_VARIANT_MASK 0x00f00000 |
Definition at line 91 of file arm_cputypes.h.
#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ |
Definition at line 97 of file arm_cputypes.h.
#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ |
Definition at line 98 of file arm_cputypes.h.
#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ |
Definition at line 99 of file arm_cputypes.h.