cpu_sh.h File Reference

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cpu_sh.h File Reference
#include "interrupt.h"
#include "misc.h"
#include "sh4_dmacreg.h"
#include "thirdparty/sh4_cpu.h"

Go to the source code of this file.

Classes

struct  sh_cpu_type_def
 
struct  sh_cpu
 

Macros

#define SH_CPU_TYPE_DEFS
 
#define SH_N_IC_ARGS   2
 
#define SH_INSTR_ALIGNMENT_SHIFT   1
 
#define SH_IC_ENTRIES_SHIFT   11
 
#define SH_IC_ENTRIES_PER_PAGE   (1 << SH_IC_ENTRIES_SHIFT)
 
#define SH_PC_TO_IC_ENTRY(a)
 
#define SH_ADDR_TO_PAGENR(a)
 
#define SH_MAX_VPH_TLB_ENTRIES   128
 
#define SH_N_GPRS   16
 
#define SH_N_GPRS_BANKED   8
 
#define SH_N_FPRS   16
 
#define SH_N_ITLB_ENTRIES   4
 
#define SH_N_UTLB_ENTRIES   64
 
#define SH_INVALID_INSTR   0x00fb
 
#define SH_SR_T   0x00000001 /* True/false */
 
#define SH_SR_S   0x00000002 /* Saturation */
 
#define SH_SR_IMASK   0x000000f0 /* Interrupt mask */
 
#define SH_SR_IMASK_SHIFT   4
 
#define SH_SR_Q   0x00000100 /* State for Divide Step */
 
#define SH_SR_M   0x00000200 /* State for Divide Step */
 
#define SH_SR_FD   0x00008000 /* FPU Disable */
 
#define SH_SR_BL   0x10000000 /* Exception/Interrupt Block */
 
#define SH_SR_RB   0x20000000 /* Register Bank 0/1 */
 
#define SH_SR_MD   0x40000000 /* Privileged Mode */
 
#define SH_FPSCR_RM_MASK   0x00000003 /* Rounding Mode */
 
#define SH_FPSCR_RM_NEAREST   0x0 /* Round to nearest */
 
#define SH_FPSCR_RM_ZERO   0x1 /* Round to zero */
 
#define SH_FPSCR_INEXACT   0x00000004 /* Inexact exception */
 
#define SH_FPSCR_UNDERFLOW   0x00000008 /* Underflow exception */
 
#define SH_FPSCR_OVERFLOW   0x00000010 /* Overflow exception */
 
#define SH_FPSCR_DIV_BY_ZERO   0x00000020 /* Div by zero exception */
 
#define SH_FPSCR_INVALID   0x00000040 /* Invalid exception */
 
#define SH_FPSCR_EN_INEXACT   0x00000080 /* Inexact enable */
 
#define SH_FPSCR_EN_UNDERFLOW   0x00000100 /* Underflow enable */
 
#define SH_FPSCR_EN_OVERFLOW   0x00000200 /* Overflow enable */
 
#define SH_FPSCR_EN_DIV_BY_ZERO   0x00000400 /* Div by zero enable */
 
#define SH_FPSCR_EN_INVALID   0x00000800 /* Invalid enable */
 
#define SH_FPSCR_CAUSE_INEXACT   0x00001000 /* Cause Inexact */
 
#define SH_FPSCR_CAUSE_UNDERFLOW   0x00002000 /* Cause Underflow */
 
#define SH_FPSCR_CAUSE_OVERFLOW   0x00004000 /* Cause Overflow */
 
#define SH_FPSCR_CAUSE_DIVBY0   0x00008000 /* Cause Div by 0 */
 
#define SH_FPSCR_CAUSE_INVALID   0x00010000 /* Cause Invalid */
 
#define SH_FPSCR_CAUSE_ERROR   0x00020000 /* Cause Error */
 
#define SH_FPSCR_DN_ZERO   0x00040000 /* Denormalization Mode */
 
#define SH_FPSCR_PR   0x00080000 /* Double-Precision Mode */
 
#define SH_FPSCR_SZ   0x00100000 /* Double-Precision Size */
 
#define SH_FPSCR_FR   0x00200000 /* Register Bank Select */
 
#define SH_INT_ASSERTED   0x10
 
#define SH_INT_PRIO_MASK   0x0f
 

Functions

void sh_cpu_interrupt_assert (struct interrupt *interrupt)
 
void sh_cpu_interrupt_deassert (struct interrupt *interrupt)
 
int sh_cpu_instruction_has_delayslot (struct cpu *cpu, unsigned char *ib)
 
int sh_run_instr (struct cpu *cpu)
 
void sh_update_translation_table (struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
 
void sh_invalidate_translation_caches (struct cpu *cpu, uint64_t, int)
 
void sh_invalidate_code_translation (struct cpu *cpu, uint64_t, int)
 
void sh_init_64bit_dummy_tables (struct cpu *cpu)
 
int sh_memory_rw (struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
 
int sh_cpu_family_init (struct cpu_family *)
 
void sh_update_interrupt_priorities (struct cpu *cpu)
 
void sh_update_sr (struct cpu *cpu, uint32_t new_sr)
 
void sh_exception (struct cpu *cpu, int expevt, int intevt, uint32_t vaddr)
 
int sh_translate_v2p (struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
 

Macro Definition Documentation

◆ SH_ADDR_TO_PAGENR

#define SH_ADDR_TO_PAGENR (   a)
Value:

Definition at line 76 of file cpu_sh.h.

◆ SH_CPU_TYPE_DEFS

#define SH_CPU_TYPE_DEFS
Value:
{ \
{ "SH7708R", 32, 3, 0, 0, }, \
{ "SH7750", 32, 4, SH4_PVR_SH7750, 0 }, \
{ "SH7750R", 32, 4, SH4_PVR_SH7750, SH4_PRR_7750R }, \
{ "SH7751R", 32, 4, SH4_PVR_SH7751, SH4_PRR_7751R }, \
/* { "SH5", 64, 5, 0, 0 }, */ \
{ NULL, 0, 0, 0, 0 } }

Definition at line 61 of file cpu_sh.h.

◆ SH_FPSCR_CAUSE_DIVBY0

#define SH_FPSCR_CAUSE_DIVBY0   0x00008000 /* Cause Div by 0 */

Definition at line 213 of file cpu_sh.h.

◆ SH_FPSCR_CAUSE_ERROR

#define SH_FPSCR_CAUSE_ERROR   0x00020000 /* Cause Error */

Definition at line 215 of file cpu_sh.h.

◆ SH_FPSCR_CAUSE_INEXACT

#define SH_FPSCR_CAUSE_INEXACT   0x00001000 /* Cause Inexact */

Definition at line 210 of file cpu_sh.h.

◆ SH_FPSCR_CAUSE_INVALID

#define SH_FPSCR_CAUSE_INVALID   0x00010000 /* Cause Invalid */

Definition at line 214 of file cpu_sh.h.

◆ SH_FPSCR_CAUSE_OVERFLOW

#define SH_FPSCR_CAUSE_OVERFLOW   0x00004000 /* Cause Overflow */

Definition at line 212 of file cpu_sh.h.

◆ SH_FPSCR_CAUSE_UNDERFLOW

#define SH_FPSCR_CAUSE_UNDERFLOW   0x00002000 /* Cause Underflow */

Definition at line 211 of file cpu_sh.h.

◆ SH_FPSCR_DIV_BY_ZERO

#define SH_FPSCR_DIV_BY_ZERO   0x00000020 /* Div by zero exception */

Definition at line 203 of file cpu_sh.h.

◆ SH_FPSCR_DN_ZERO

#define SH_FPSCR_DN_ZERO   0x00040000 /* Denormalization Mode */

Definition at line 216 of file cpu_sh.h.

◆ SH_FPSCR_EN_DIV_BY_ZERO

#define SH_FPSCR_EN_DIV_BY_ZERO   0x00000400 /* Div by zero enable */

Definition at line 208 of file cpu_sh.h.

◆ SH_FPSCR_EN_INEXACT

#define SH_FPSCR_EN_INEXACT   0x00000080 /* Inexact enable */

Definition at line 205 of file cpu_sh.h.

◆ SH_FPSCR_EN_INVALID

#define SH_FPSCR_EN_INVALID   0x00000800 /* Invalid enable */

Definition at line 209 of file cpu_sh.h.

◆ SH_FPSCR_EN_OVERFLOW

#define SH_FPSCR_EN_OVERFLOW   0x00000200 /* Overflow enable */

Definition at line 207 of file cpu_sh.h.

◆ SH_FPSCR_EN_UNDERFLOW

#define SH_FPSCR_EN_UNDERFLOW   0x00000100 /* Underflow enable */

Definition at line 206 of file cpu_sh.h.

◆ SH_FPSCR_FR

#define SH_FPSCR_FR   0x00200000 /* Register Bank Select */

Definition at line 219 of file cpu_sh.h.

◆ SH_FPSCR_INEXACT

#define SH_FPSCR_INEXACT   0x00000004 /* Inexact exception */

Definition at line 200 of file cpu_sh.h.

◆ SH_FPSCR_INVALID

#define SH_FPSCR_INVALID   0x00000040 /* Invalid exception */

Definition at line 204 of file cpu_sh.h.

◆ SH_FPSCR_OVERFLOW

#define SH_FPSCR_OVERFLOW   0x00000010 /* Overflow exception */

Definition at line 202 of file cpu_sh.h.

◆ SH_FPSCR_PR

#define SH_FPSCR_PR   0x00080000 /* Double-Precision Mode */

Definition at line 217 of file cpu_sh.h.

◆ SH_FPSCR_RM_MASK

#define SH_FPSCR_RM_MASK   0x00000003 /* Rounding Mode */

Definition at line 197 of file cpu_sh.h.

◆ SH_FPSCR_RM_NEAREST

#define SH_FPSCR_RM_NEAREST   0x0 /* Round to nearest */

Definition at line 198 of file cpu_sh.h.

◆ SH_FPSCR_RM_ZERO

#define SH_FPSCR_RM_ZERO   0x1 /* Round to zero */

Definition at line 199 of file cpu_sh.h.

◆ SH_FPSCR_SZ

#define SH_FPSCR_SZ   0x00100000 /* Double-Precision Size */

Definition at line 218 of file cpu_sh.h.

◆ SH_FPSCR_UNDERFLOW

#define SH_FPSCR_UNDERFLOW   0x00000008 /* Underflow exception */

Definition at line 201 of file cpu_sh.h.

◆ SH_IC_ENTRIES_PER_PAGE

#define SH_IC_ENTRIES_PER_PAGE   (1 << SH_IC_ENTRIES_SHIFT)

Definition at line 73 of file cpu_sh.h.

◆ SH_IC_ENTRIES_SHIFT

#define SH_IC_ENTRIES_SHIFT   11

Definition at line 72 of file cpu_sh.h.

◆ SH_INSTR_ALIGNMENT_SHIFT

#define SH_INSTR_ALIGNMENT_SHIFT   1

Definition at line 71 of file cpu_sh.h.

◆ SH_INT_ASSERTED

#define SH_INT_ASSERTED   0x10

Definition at line 223 of file cpu_sh.h.

◆ SH_INT_PRIO_MASK

#define SH_INT_PRIO_MASK   0x0f

Definition at line 224 of file cpu_sh.h.

◆ SH_INVALID_INSTR

#define SH_INVALID_INSTR   0x00fb

Definition at line 93 of file cpu_sh.h.

◆ SH_MAX_VPH_TLB_ENTRIES

#define SH_MAX_VPH_TLB_ENTRIES   128

Definition at line 81 of file cpu_sh.h.

◆ SH_N_FPRS

#define SH_N_FPRS   16

Definition at line 86 of file cpu_sh.h.

◆ SH_N_GPRS

#define SH_N_GPRS   16

Definition at line 84 of file cpu_sh.h.

◆ SH_N_GPRS_BANKED

#define SH_N_GPRS_BANKED   8

Definition at line 85 of file cpu_sh.h.

◆ SH_N_IC_ARGS

#define SH_N_IC_ARGS   2

Definition at line 70 of file cpu_sh.h.

◆ SH_N_ITLB_ENTRIES

#define SH_N_ITLB_ENTRIES   4

Definition at line 88 of file cpu_sh.h.

◆ SH_N_UTLB_ENTRIES

#define SH_N_UTLB_ENTRIES   64

Definition at line 89 of file cpu_sh.h.

◆ SH_PC_TO_IC_ENTRY

#define SH_PC_TO_IC_ENTRY (   a)
Value:

Definition at line 74 of file cpu_sh.h.

◆ SH_SR_BL

#define SH_SR_BL   0x10000000 /* Exception/Interrupt Block */

Definition at line 192 of file cpu_sh.h.

◆ SH_SR_FD

#define SH_SR_FD   0x00008000 /* FPU Disable */

Definition at line 191 of file cpu_sh.h.

◆ SH_SR_IMASK

#define SH_SR_IMASK   0x000000f0 /* Interrupt mask */

Definition at line 187 of file cpu_sh.h.

◆ SH_SR_IMASK_SHIFT

#define SH_SR_IMASK_SHIFT   4

Definition at line 188 of file cpu_sh.h.

◆ SH_SR_M

#define SH_SR_M   0x00000200 /* State for Divide Step */

Definition at line 190 of file cpu_sh.h.

◆ SH_SR_MD

#define SH_SR_MD   0x40000000 /* Privileged Mode */

Definition at line 194 of file cpu_sh.h.

◆ SH_SR_Q

#define SH_SR_Q   0x00000100 /* State for Divide Step */

Definition at line 189 of file cpu_sh.h.

◆ SH_SR_RB

#define SH_SR_RB   0x20000000 /* Register Bank 0/1 */

Definition at line 193 of file cpu_sh.h.

◆ SH_SR_S

#define SH_SR_S   0x00000002 /* Saturation */

Definition at line 186 of file cpu_sh.h.

◆ SH_SR_T

#define SH_SR_T   0x00000001 /* True/false */

Definition at line 185 of file cpu_sh.h.

Function Documentation

◆ sh_cpu_family_init()

int sh_cpu_family_init ( struct cpu_family )

◆ sh_cpu_instruction_has_delayslot()

int sh_cpu_instruction_has_delayslot ( struct cpu cpu,
unsigned char *  ib 
)

Definition at line 395 of file cpu_sh.cc.

References BE16_TO_HOST, cpu::byte_order, EMUL_BIG_ENDIAN, cpu::is_32bit, and LE16_TO_HOST.

◆ sh_cpu_interrupt_assert()

void sh_cpu_interrupt_assert ( struct interrupt interrupt)

◆ sh_cpu_interrupt_deassert()

void sh_cpu_interrupt_deassert ( struct interrupt interrupt)

◆ sh_exception()

void sh_exception ( struct cpu cpu,
int  expevt,
int  intevt,
uint32_t  vaddr 
)

◆ sh_init_64bit_dummy_tables()

void sh_init_64bit_dummy_tables ( struct cpu cpu)

◆ sh_invalidate_code_translation()

void sh_invalidate_code_translation ( struct cpu cpu,
uint64_t  ,
int   
)

◆ sh_invalidate_translation_caches()

void sh_invalidate_translation_caches ( struct cpu cpu,
uint64_t  ,
int   
)

◆ sh_memory_rw()

int sh_memory_rw ( struct cpu cpu,
struct memory mem,
uint64_t  vaddr,
unsigned char *  data,
size_t  len,
int  writeflag,
int  cache_flags 
)

◆ sh_run_instr()

int sh_run_instr ( struct cpu cpu)

◆ sh_translate_v2p()

int sh_translate_v2p ( struct cpu cpu,
uint64_t  vaddr,
uint64_t *  return_addr,
int  flags 
)

Definition at line 248 of file memory_sh.cc.

References cpu::cd, sh_cpu::mmucr, cpu::sh, SH4_MMUCR_AT, SH_SR_MD, and sh_cpu::sr.

◆ sh_update_interrupt_priorities()

void sh_update_interrupt_priorities ( struct cpu cpu)

◆ sh_update_sr()

void sh_update_sr ( struct cpu cpu,
uint32_t  new_sr 
)

Definition at line 585 of file cpu_sh.cc.

References cpu::cd, sh_cpu::r, sh_cpu::r_bank, cpu::sh, SH_N_GPRS_BANKED, SH_SR_RB, and sh_cpu::sr.

Referenced by sh_exception(), and X().

◆ sh_update_translation_table()

void sh_update_translation_table ( struct cpu cpu,
uint64_t  vaddr_page,
unsigned char *  host_page,
int  writeflag,
uint64_t  paddr_page 
)
SH_INSTR_ALIGNMENT_SHIFT
#define SH_INSTR_ALIGNMENT_SHIFT
Definition: cpu_sh.h:71
SH4_PRR_7751R
#define SH4_PRR_7751R
Definition: sh4_cpu.h:200
SH4_PVR_SH7751
#define SH4_PVR_SH7751
Definition: sh4_cpu.h:196
SH4_PRR_7750R
#define SH4_PRR_7750R
Definition: sh4_cpu.h:199
SH_IC_ENTRIES_PER_PAGE
#define SH_IC_ENTRIES_PER_PAGE
Definition: cpu_sh.h:73
SH_IC_ENTRIES_SHIFT
#define SH_IC_ENTRIES_SHIFT
Definition: cpu_sh.h:72
SH4_PVR_SH7750
#define SH4_PVR_SH7750
Definition: sh4_cpu.h:193

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