sh4_cpu.h File Reference

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Macros
sh4_cpu.h File Reference

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Macros

#define SH3_PHYS_MASK   0x1fffffff
 
#define SH3_P0SEG_BASE   0x00000000 /* TLB mapped, also U0SEG */
 
#define SH3_P0SEG_END   0x7fffffff
 
#define SH3_P1SEG_BASE   0x80000000 /* pa == va */
 
#define SH3_P1SEG_END   0x9fffffff
 
#define SH3_P2SEG_BASE   0xa0000000 /* pa == va, non-cacheable */
 
#define SH3_P2SEG_END   0xbfffffff
 
#define SH3_P3SEG_BASE   0xc0000000 /* TLB mapped, kernel mode */
 
#define SH3_P3SEG_END   0xdfffffff
 
#define SH3_P4SEG_BASE   0xe0000000 /* peripheral space */
 
#define SH3_P4SEG_END   0xffffffff
 
#define SH3_P1SEG_TO_PHYS(x)   ((uint32_t)(x) & SH3_PHYS_MASK)
 
#define SH3_P2SEG_TO_PHYS(x)   ((uint32_t)(x) & SH3_PHYS_MASK)
 
#define SH3_PHYS_TO_P1SEG(x)   ((uint32_t)(x) | SH3_P1SEG_BASE)
 
#define SH3_PHYS_TO_P2SEG(x)   ((uint32_t)(x) | SH3_P2SEG_BASE)
 
#define SH3_P1SEG_TO_P2SEG(x)   ((uint32_t)(x) | 0x20000000)
 
#define SH3_P2SEG_TO_P1SEG(x)   ((uint32_t)(x) & ~0x20000000)
 
#define RUN_P2
 
#define RUN_P1
 
#define SH4_PVR_ADDR   0xff000030 /* P4 address */
 
#define SH4_PVR   (*(volatile uint32_t *) SH4_PVR_ADDR)
 
#define SH4_PRR_ADDR   0xff000044 /* P4 address */
 
#define SH4_PRR   (*(volatile uint32_t *) SH4_PRR_ADDR)
 
#define SH4_PVR_MASK   0xffffff00
 
#define SH4_PVR_SH7750   0x04020500 /* SH7750 */
 
#define SH4_PVR_SH7750S   0x04020600 /* SH7750S */
 
#define SH4_PVR_SH775xR   0x04050000 /* SH775xR */
 
#define SH4_PVR_SH7751   0x04110000 /* SH7751 */
 
#define SH4_PRR_MASK   0xfffffff0
 
#define SH4_PRR_7750R   0x00000100 /* SH7750R */
 
#define SH4_PRR_7751R   0x00000110 /* SH7751R */
 
#define CPU_CONSDEV   1 /* dev_t: console terminal device */
 
#define CPU_LOADANDRESET   2 /* load kernel image and reset */
 
#define CPU_MAXID   3 /* number of valid machdep ids */
 
#define CTL_MACHDEP_NAMES
 

Macro Definition Documentation

◆ CPU_CONSDEV

#define CPU_CONSDEV   1 /* dev_t: console terminal device */

Definition at line 211 of file sh4_cpu.h.

◆ CPU_LOADANDRESET

#define CPU_LOADANDRESET   2 /* load kernel image and reset */

Definition at line 212 of file sh4_cpu.h.

◆ CPU_MAXID

#define CPU_MAXID   3 /* number of valid machdep ids */

Definition at line 213 of file sh4_cpu.h.

◆ CTL_MACHDEP_NAMES

#define CTL_MACHDEP_NAMES
Value:
{ \
{ 0, 0 }, \
{ "console_device", CTLTYPE_STRUCT }, \
{ "load_and_reset", CTLTYPE_INT }, \
}

Definition at line 215 of file sh4_cpu.h.

◆ RUN_P1

#define RUN_P1
Value:
do { \
void *p; \
p = &&P1; \
__asm volatile("nop;nop;nop;nop;nop;nop;nop;nop"); \
goto *(void *)SH3_P2SEG_TO_P1SEG(p); \
P1: (void)0; \
} while (0)

Definition at line 172 of file sh4_cpu.h.

◆ RUN_P2

#define RUN_P2
Value:
do { \
void *p; \
p = &&P2; \
goto *(void *)SH3_P1SEG_TO_P2SEG(p); \
P2: (void)0; \
} while (0)

Definition at line 164 of file sh4_cpu.h.

◆ SH3_P0SEG_BASE

#define SH3_P0SEG_BASE   0x00000000 /* TLB mapped, also U0SEG */

Definition at line 143 of file sh4_cpu.h.

◆ SH3_P0SEG_END

#define SH3_P0SEG_END   0x7fffffff

Definition at line 144 of file sh4_cpu.h.

◆ SH3_P1SEG_BASE

#define SH3_P1SEG_BASE   0x80000000 /* pa == va */

Definition at line 145 of file sh4_cpu.h.

◆ SH3_P1SEG_END

#define SH3_P1SEG_END   0x9fffffff

Definition at line 146 of file sh4_cpu.h.

◆ SH3_P1SEG_TO_P2SEG

#define SH3_P1SEG_TO_P2SEG (   x)    ((uint32_t)(x) | 0x20000000)

Definition at line 158 of file sh4_cpu.h.

◆ SH3_P1SEG_TO_PHYS

#define SH3_P1SEG_TO_PHYS (   x)    ((uint32_t)(x) & SH3_PHYS_MASK)

Definition at line 154 of file sh4_cpu.h.

◆ SH3_P2SEG_BASE

#define SH3_P2SEG_BASE   0xa0000000 /* pa == va, non-cacheable */

Definition at line 147 of file sh4_cpu.h.

◆ SH3_P2SEG_END

#define SH3_P2SEG_END   0xbfffffff

Definition at line 148 of file sh4_cpu.h.

◆ SH3_P2SEG_TO_P1SEG

#define SH3_P2SEG_TO_P1SEG (   x)    ((uint32_t)(x) & ~0x20000000)

Definition at line 159 of file sh4_cpu.h.

◆ SH3_P2SEG_TO_PHYS

#define SH3_P2SEG_TO_PHYS (   x)    ((uint32_t)(x) & SH3_PHYS_MASK)

Definition at line 155 of file sh4_cpu.h.

◆ SH3_P3SEG_BASE

#define SH3_P3SEG_BASE   0xc0000000 /* TLB mapped, kernel mode */

Definition at line 149 of file sh4_cpu.h.

◆ SH3_P3SEG_END

#define SH3_P3SEG_END   0xdfffffff

Definition at line 150 of file sh4_cpu.h.

◆ SH3_P4SEG_BASE

#define SH3_P4SEG_BASE   0xe0000000 /* peripheral space */

Definition at line 151 of file sh4_cpu.h.

◆ SH3_P4SEG_END

#define SH3_P4SEG_END   0xffffffff

Definition at line 152 of file sh4_cpu.h.

◆ SH3_PHYS_MASK

#define SH3_PHYS_MASK   0x1fffffff

Definition at line 141 of file sh4_cpu.h.

◆ SH3_PHYS_TO_P1SEG

#define SH3_PHYS_TO_P1SEG (   x)    ((uint32_t)(x) | SH3_P1SEG_BASE)

Definition at line 156 of file sh4_cpu.h.

◆ SH3_PHYS_TO_P2SEG

#define SH3_PHYS_TO_P2SEG (   x)    ((uint32_t)(x) | SH3_P2SEG_BASE)

Definition at line 157 of file sh4_cpu.h.

◆ SH4_PRR

#define SH4_PRR   (*(volatile uint32_t *) SH4_PRR_ADDR)

Definition at line 190 of file sh4_cpu.h.

◆ SH4_PRR_7750R

#define SH4_PRR_7750R   0x00000100 /* SH7750R */

Definition at line 199 of file sh4_cpu.h.

◆ SH4_PRR_7751R

#define SH4_PRR_7751R   0x00000110 /* SH7751R */

Definition at line 200 of file sh4_cpu.h.

◆ SH4_PRR_ADDR

#define SH4_PRR_ADDR   0xff000044 /* P4 address */

Definition at line 189 of file sh4_cpu.h.

◆ SH4_PRR_MASK

#define SH4_PRR_MASK   0xfffffff0

Definition at line 198 of file sh4_cpu.h.

◆ SH4_PVR

#define SH4_PVR   (*(volatile uint32_t *) SH4_PVR_ADDR)

Definition at line 188 of file sh4_cpu.h.

◆ SH4_PVR_ADDR

#define SH4_PVR_ADDR   0xff000030 /* P4 address */

Definition at line 187 of file sh4_cpu.h.

◆ SH4_PVR_MASK

#define SH4_PVR_MASK   0xffffff00

Definition at line 192 of file sh4_cpu.h.

◆ SH4_PVR_SH7750

#define SH4_PVR_SH7750   0x04020500 /* SH7750 */

Definition at line 193 of file sh4_cpu.h.

◆ SH4_PVR_SH7750S

#define SH4_PVR_SH7750S   0x04020600 /* SH7750S */

Definition at line 194 of file sh4_cpu.h.

◆ SH4_PVR_SH7751

#define SH4_PVR_SH7751   0x04110000 /* SH7751 */

Definition at line 196 of file sh4_cpu.h.

◆ SH4_PVR_SH775xR

#define SH4_PVR_SH775xR   0x04050000 /* SH775xR */

Definition at line 195 of file sh4_cpu.h.

SH3_P2SEG_TO_P1SEG
#define SH3_P2SEG_TO_P1SEG(x)
Definition: sh4_cpu.h:159
P2
#define P2(addr)
Definition: hitachi_hm53462_rop.h:29
SH3_P1SEG_TO_P2SEG
#define SH3_P1SEG_TO_P2SEG(x)
Definition: sh4_cpu.h:158
P1
#define P1(addr)
Definition: hitachi_hm53462_rop.h:28

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