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◆ ADDR_API_SHFT
#define ADDR_API_SHFT 22 /* API is 6 bits */ |
◆ ADDR_PIDX
#define ADDR_PIDX 0x0ffff000 |
◆ ADDR_PIDX_SHFT
#define ADDR_PIDX_SHFT 12 |
◆ ADDR_POFF
#define ADDR_POFF 0x00000fff |
◆ ADDR_SR
#define ADDR_SR (~0x0fffffffL) |
◆ ADDR_SR_SHFT
◆ PTE_API
#define PTE_API 0x0000003f |
◆ PTE_API_SHFT
◆ PTE_BR
#define PTE_BR 0x00000003 /* Both Read Only (U: RO, S: RO) */ |
◆ PTE_BW
#define PTE_BW 0x00000002 /* Supervisor (U: RW, S: RW) */ |
◆ PTE_CHG
#define PTE_CHG 0x00000080 |
◆ PTE_EXEC
#define PTE_EXEC 0x00000200 /* pseudo bit; page is exec */ |
◆ PTE_G
#define PTE_G 0x00000008 /* guarded region (not on 601) */ |
◆ PTE_HID
#define PTE_HID 0x00000040 |
◆ PTE_I
#define PTE_I 0x00000020 /* cache inhibit */ |
◆ PTE_IG
◆ PTE_M
#define PTE_M 0x00000010 /* memory coherency enable */ |
◆ PTE_PP
#define PTE_PP 0x00000003 |
◆ PTE_REF
#define PTE_REF 0x00000100 |
◆ PTE_RO
◆ PTE_RPGN
#define PTE_RPGN (~0xfffL) |
◆ PTE_RPGN_SHFT
◆ PTE_RW
◆ PTE_SO
#define PTE_SO 0x00000000 /* Super. Only (U: XX, S: RW) */ |
◆ PTE_SW
#define PTE_SW 0x00000001 /* Super. Write-Only (U: RO, S: RW) */ |
◆ PTE_VALID
#define PTE_VALID 0x80000000 |
◆ PTE_VSID
#define PTE_VSID 0x7fffff80 |
◆ PTE_VSID_LEN
◆ PTE_VSID_SHFT
◆ PTE_W
#define PTE_W 0x00000040 /* 1 = write-through, 0 = write-back */ |
◆ PTE_WIMG
◆ SR_KEY_LEN
#define SR_KEY_LEN 4 /* 16 segment registers */ |
◆ SR_NOEXEC
#define SR_NOEXEC 0x10000000 /* No-execute protection bit */ |
◆ SR_PRKEY
#define SR_PRKEY 0x20000000 /* User protection key */ |
◆ SR_SUKEY
#define SR_SUKEY 0x40000000 /* Supervisor protection key */ |
◆ SR_TYPE
#define SR_TYPE 0x80000000 /* T=0 selects memory format */ |
◆ SR_VSID
◆ SR_VSID_SHFT
#define SR_VSID_SHFT 0 /* Starts at LSB */ |
◆ SR_VSID_WIDTH
#define SR_VSID_WIDTH 24 /* Goes for 24 bits */ |