memory_mips.cc Source File

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memory_mips.cc
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1 /*
2  * Copyright (C) 2003-2009 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * MIPS-specific memory routines. Included from cpu_mips.c.
29  */
30 
31 #include <sys/types.h>
32 #include <sys/mman.h>
33 
34 
35 /*
36  * memory_cache_R3000():
37  *
38  * R2000/R3000 specific cache handling.
39  *
40  * Return value is 1 if a jump to do_return_ok is supposed to happen directly
41  * after this routine is finished, 0 otherwise.
42  */
43 int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr,
44  int writeflag, size_t len, unsigned char *data)
45 {
46  unsigned int i;
47  int cache_isolated = 0, addr, hit, which_cache = cache;
48 
49 
50  if (len > 4 || cache == CACHE_NONE)
51  return 0;
52 
53 
54  /*
55  * R2000/R3000 without correct cache emulation:
56  *
57  * TODO: This is just enough to trick NetBSD/pmax and Ultrix into
58  * being able to detect the cache sizes and think that the caches
59  * are actually working, but they are not.
60  */
61 
62  if (cache != CACHE_DATA)
63  return 0;
64 
65  /* Is this a cache hit or miss? */
66  hit = (cpu->cd.mips.cache_last_paddr[which_cache]
67  & ~cpu->cd.mips.cache_mask[which_cache])
68  == (paddr & ~(cpu->cd.mips.cache_mask[which_cache]));
69 
70  /*
71  * The cache miss bit is only set on cache reads, and only to the
72  * data cache. (?)
73  *
74  * (TODO: is this correct? I don't remember where I got this from.)
75  */
76  if (cache == CACHE_DATA && writeflag==MEM_READ) {
78  if (!hit)
79  cpu->cd.mips.coproc[0]->reg[COP0_STATUS] |=
81  }
82 
83  /*
84  * Is the Data cache isolated? Then don't access main memory:
85  */
86  if (cache == CACHE_DATA &&
88  cache_isolated = 1;
89 
90  addr = paddr & cpu->cd.mips.cache_mask[which_cache];
91 
92  /* Data cache isolated? Then don't access main memory: */
93  if (cache_isolated) {
94  /* debug("ISOLATED write=%i cache=%i vaddr=%016"PRIx64" "
95  "paddr=%016"PRIx64" => addr in cache = 0x%lx\n",
96  writeflag, cache, (uint64_t) vaddr,
97  (uint64_t) paddr, addr); */
98 
99  if (writeflag==MEM_READ) {
100  for (i=0; i<len; i++)
101  data[i] = cpu->cd.mips.cache[cache][(addr+i) &
102  cpu->cd.mips.cache_mask[cache]];
103  } else {
104  for (i=0; i<len; i++)
105  cpu->cd.mips.cache[cache][(addr+i) &
106  cpu->cd.mips.cache_mask[cache]] = data[i];
107  }
108  return 1;
109  } else {
110  /* Reload caches if necessary: */
111 
112  /* No! Not when not emulating caches fully. (TODO?) */
113  cpu->cd.mips.cache_last_paddr[cache] = paddr;
114  }
115 
116  return 0;
117 }
118 
119 
120 #define TRANSLATE_ADDRESS translate_v2p_mmu3k
121 #define V2P_MMU3K
122 #include "memory_mips_v2p.cc"
123 #undef TRANSLATE_ADDRESS
124 #undef V2P_MMU3K
125 
126 #define TRANSLATE_ADDRESS translate_v2p_mmu8k
127 #define V2P_MMU8K
128 #include "memory_mips_v2p.cc"
129 #undef TRANSLATE_ADDRESS
130 #undef V2P_MMU8K
131 
132 #define TRANSLATE_ADDRESS translate_v2p_mmu10k
133 #define V2P_MMU10K
134 #include "memory_mips_v2p.cc"
135 #undef TRANSLATE_ADDRESS
136 #undef V2P_MMU10K
137 
138 /* Almost generic :-) */
139 #define TRANSLATE_ADDRESS translate_v2p_mmu4100
140 #define V2P_MMU4100
141 #include "memory_mips_v2p.cc"
142 #undef TRANSLATE_ADDRESS
143 #undef V2P_MMU4100
144 
145 #define TRANSLATE_ADDRESS translate_v2p_generic
146 #include "memory_mips_v2p.cc"
147 
148 
mips_coproc::reg
uint64_t reg[N_MIPS_COPROC_REGS]
Definition: cpu_mips.h:102
data
u_short data
Definition: siireg.h:79
mips_cpu::coproc
struct mips_coproc * coproc[N_MIPS_COPROCS]
Definition: cpu_mips.h:219
memory_mips_v2p.cc
mips_cpu::cache_mask
int cache_mask[2]
Definition: cpu_mips.h:271
MEM_READ
#define MEM_READ
Definition: memory.h:116
addr
uint32_t addr
Definition: tmp_arm_multi.cc:52
mips_cpu::cache_last_paddr
uint64_t cache_last_paddr[2]
Definition: cpu_mips.h:268
MIPS1_ISOL_CACHES
#define MIPS1_ISOL_CACHES
Definition: mips_cpuregs.h:180
cpu::mips
struct mips_cpu mips
Definition: cpu.h:443
memory_cache_R3000
int memory_cache_R3000(struct cpu *cpu, int cache, uint64_t paddr, int writeflag, size_t len, unsigned char *data)
Definition: memory_mips.cc:43
MIPS1_CACHE_MISS
#define MIPS1_CACHE_MISS
Definition: mips_cpuregs.h:177
CACHE_NONE
#define CACHE_NONE
Definition: memory.h:123
cpu::cd
union cpu::@1 cd
mips_cpu::cache
unsigned char * cache[2]
Definition: cpu_mips.h:266
CACHE_DATA
#define CACHE_DATA
Definition: memory.h:121
cpu
Definition: cpu.h:326
COP0_STATUS
#define COP0_STATUS
Definition: cop0.h:109

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