luna88k_board.h Source File

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luna88k_board.h
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1 /* Imported into GXemul 2018-02-03 from OpenBSD 6.2. */
2 
3 /* $OpenBSD: board.h,v 1.14 2017/03/20 19:40:47 miod Exp $ */
4 /*
5  * Mach Operating System
6  * Copyright (c) 1993-1991 Carnegie Mellon University
7  * Copyright (c) 1991 OMRON Corporation
8  * All Rights Reserved.
9  *
10  * Permission to use, copy, modify and distribute this software and its
11  * documentation is hereby granted, provided that both the copyright
12  * notice and this permission notice appear in all copies of the
13  * software, derivative works or modified versions, and any portions
14  * thereof, and that both notices appear in supporting documentation.
15  *
16  * CARNEGIE MELLON AND OMRON ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17  * CONDITION. CARNEGIE MELLON AND OMRON DISCLAIM ANY LIABILITY OF ANY KIND
18  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19  *
20  * Carnegie Mellon requests users of this software to return to
21  *
22  * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23  * School of Computer Science
24  * Carnegie Mellon University
25  * Pittsburgh PA 15213-3890
26  *
27  * any improvements or extensions that they make and grant Carnegie the
28  * rights to redistribute these changes.
29  */
30 
31 #ifndef _MACHINE_BOARD_H_
32 #define _MACHINE_BOARD_H_
33 
34 /*
35  * OMRON SX9100DT CPU board constants
36  */
37 
38 /*
39  * Something to put append a 'U' to a long constant if it's C so that
40  * it'll be unsigned in both ANSI and traditional.
41  */
42 #if defined(_LOCORE)
43 #define U(num) num
44 #elif defined(__STDC__)
45 #define U(num) num ## U
46 #else
47 #define U(num) num/**/U
48 #endif
49 
50 /* machtype values */
51 #define LUNA_88K 0x1
52 #define LUNA_88K2 0x2
53 
54 #define MAXPHYSMEM U(0x10000000) /* max physical memory */
55 
56 #define PROM_ADDR U(0x41000000) /* PROM */
57 #define PROM_SPACE U(0x00040000)
58 #define NVRAM_ADDR U(0x45000000) /* Non Volatile */
59 #define NVRAM_SPACE U(0x00001FDC)
60 #define FUSE_ROM_ADDR U(0x43000000) /* FUSE_ROM */
61 #define FUSE_ROM_SPACE 1024
62 #define OBIO_CAL_CTL U(0x45001FE0) /* calendar control register */
63 #define OBIO_CAL_SEC U(0x45001FE4) /* seconds */
64 #define OBIO_CAL_MIN U(0x45001FE8) /* minutes */
65 #define OBIO_CAL_HOUR U(0x45001FEC) /* hours */
66 #define OBIO_CAL_DOW U(0x45001FF0) /* Day Of the Week */
67 #define OBIO_CAL_DAY U(0x45001FF4) /* days */
68 #define OBIO_CAL_MON U(0x45001FF8) /* months */
69 #define OBIO_CAL_YEAR U(0x45001FFC) /* years */
70 #define NVRAM_ADDR_88K2 U(0x47000000) /* Non Volatile RAM area for LUNA-88K2 */
71 #define OBIO_PIO0_BASE U(0x49000000) /* PIO-0 */
72 #define OBIO_PIO0_SPACE U(0x0000000C)
73 #define OBIO_PIO0A U(0x49000000) /* PIO-0 port A */
74 #define OBIO_PIO0B U(0x49000004) /* PIO-0 port B */
75 #define OBIO_PIO0C U(0x49000008) /* PIO-0 port C*/
76 #define OBIO_PIO0 U(0x4900000C) /* PIO-0 control */
77 #define OBIO_PIO1_BASE U(0x4D000000) /* PIO-1 */
78 #define OBIO_PIO1_SPACE U(0x0000000C)
79 #define OBIO_PIO1A U(0x4D000000) /* PIO-1 port A */
80 #define OBIO_PIO1B U(0x4D000004) /* PIO-1 port B */
81 #define OBIO_PIO1C U(0x4D000008) /* PIO-1 port C*/
82 #define OBIO_PIO1 U(0x4D00000C) /* PIO-1 control */
83 #define OBIO_SIO U(0x51000000) /* SIO */
84 #define OBIO_TAS U(0x61000000) /* TAS register */
85 #define OBIO_CLOCK0 U(0x63000000) /* system clock CPU 0 */
86 #define OBIO_CLOCK1 U(0x63000004) /* system clock CPU 1 */
87 #define OBIO_CLOCK2 U(0x63000008) /* system clock CPU 2 */
88 #define OBIO_CLOCK3 U(0x6300000C) /* system clock CPU 3 */
89 #define OBIO_CLK_INTR 31 /* system clock interrupt flag */
90 #define INT_ST_MASK0 U(0x65000000) /* interrupt status register CPU 0 */
91 #define INT_ST_MASK1 U(0x65000004) /* interrupt status register CPU 1 */
92 #define INT_ST_MASK2 U(0x65000008) /* interrupt status register CPU 2 */
93 #define INT_ST_MASK3 U(0x6500000C) /* interrupt status register CPU 3 */
94 #define INT_LEVEL 8 /* # of interrupt level + 1 */
95 #define INT_SET_LV7 U(0x00000000) /* disable interrupts */
96 #define INT_SET_LV6 U(0x00000000) /* enable level 7 */
97 #define INT_SET_LV5 U(0x84000000) /* enable level 7-6 */
98 #define INT_SET_LV4 U(0xC4000000) /* enable level 7-5 */
99 #define INT_SET_LV3 U(0xE4000000) /* enable level 7-4 */
100 #define INT_SET_LV2 U(0xF4000000) /* enable level 7-3 */
101 #define INT_SET_LV1 U(0xFC000000) /* enable level 7-2 */
102 #define INT_SET_LV0 U(0xFC000000) /* enable interrupts */
103 #define INT_SLAVE_MASK U(0x84000000) /* slave can only enable 6 and 1 */
104 
105 #define SOFT_INT0 U(0x69000000) /* software interrupt CPU 0 */
106 #define SOFT_INT1 U(0x69000004) /* software interrupt CPU 1 */
107 #define SOFT_INT2 U(0x69000008) /* software interrupt CPU 2 */
108 #define SOFT_INT3 U(0x6900000C) /* software interrupt CPU 3 */
109 #define SOFT_INT_FLAG0 U(0x6B000000) /* software interrupt flag CPU 0 */
110 #define SOFT_INT_FLAG1 U(0x6B000000) /* software interrupt flag CPU 1 */
111 #define SOFT_INT_FLAG2 U(0x6B000000) /* software interrupt flag CPU 2 */
112 #define SOFT_INT_FLAG3 U(0x6B000000) /* software interrupt flag CPU 3 */
113 #define RESET_CPU0 U(0x6D000000) /* reset CPU 0 */
114 #define RESET_CPU1 U(0x6D000004) /* reset CPU 1 */
115 #define RESET_CPU2 U(0x6D000008) /* reset CPU 2 */
116 #define RESET_CPU3 U(0x6D00000C) /* reset CPU 3 */
117 #define RESET_CPU_ALL U(0x6D000010) /* reset ALL CPUs */
118 #define TRI_PORT_RAM U(0x71000000) /* 3 port RAM */
119 #define TRI_PORT_RAM_SPACE 0x20000
120 #define EXT_A_ADDR U(0x81000000) /* extension board A */
121 #define EXT_A_SPACE U(0x02000000)
122 #define EXT_B_ADDR U(0x83000000) /* extension board B */
123 #define EXT_B_SPACE U(0x01000000)
124 #define PC_BASE U(0x90000000) /* pc-98 extension board */
125 #define PC_SPACE U(0x02000000)
126 
127 #define MROM_ADDR U(0xA1000000) /* Mask ROM address */
128 #define MROM_SPACE 0x400000
129 #define BMAP_START U(0xB1000000) /* Bitmap start address */
130 #define BMAP_SPACE (BMAP_END - BMAP_START)
131 #define BMAP_RFCNT U(0xB1000000) /* RFCNT register */
132 #define BMAP_BMSEL U(0xB1040000) /* BMSEL register */
133 #define BMAP_BMP U(0xB1080000) /* common bitmap plane */
134 #define BMAP_BMAP0 U(0xB10C0000) /* bitmap plane 0 */
135 #define BMAP_BMAP1 U(0xB1100000) /* bitmap plane 1 */
136 #define BMAP_BMAP2 U(0xB1140000) /* bitmap plane 2 */
137 #define BMAP_BMAP3 U(0xB1180000) /* bitmap plane 3 */
138 #define BMAP_BMAP4 U(0xB11C0000) /* bitmap plane 4 */
139 #define BMAP_BMAP5 U(0xB1200000) /* bitmap plane 5 */
140 #define BMAP_BMAP6 U(0xB1240000) /* bitmap plane 6 */
141 #define BMAP_BMAP7 U(0xB1280000) /* bitmap plane 7 */
142 #define BMAP_FN U(0xB12C0000) /* common bitmap function */
143 #define BMAP_FN0 U(0xB1300000) /* bitmap function 0 */
144 #define BMAP_FN1 U(0xB1340000) /* bitmap function 1 */
145 #define BMAP_FN2 U(0xB1380000) /* bitmap function 2 */
146 #define BMAP_FN3 U(0xB13C0000) /* bitmap function 3 */
147 #define BMAP_FN4 U(0xB1400000) /* bitmap function 4 */
148 #define BMAP_FN5 U(0xB1440000) /* bitmap function 5 */
149 #define BMAP_FN6 U(0xB1480000) /* bitmap function 6 */
150 #define BMAP_FN7 U(0xB14C0000) /* bitmap function 7 */
151 #define BMAP_END U(0xB1500000)
152 #define BMAP_END24P U(0xB1800000) /* end of 24p framemem */
153 #define BMAP_PALLET0 U(0xC0000000) /* color pallet */
154 #define BMAP_PALLET1 U(0xC1000000) /* color pallet */
155 #define BMAP_PALLET2 U(0xC1100000) /* color pallet */
156 #define BOARD_CHECK_REG U(0xD0000000) /* board check register */
157 #define BMAP_CRTC U(0xD1000000) /* CRTC-II */
158 #define BMAP_IDENTROM U(0xD1800000) /* bitmap-board identify ROM */
159 #define SCSI_ADDR U(0xE1000000) /* SCSI address */
160 #define LANCE_ADDR U(0xF1000000) /* LANCE */
161 
162 #define CMMU_I0 U(0xFFF07000) /* CMMU instruction cpu 0 */
163 #define CMMU_D0 U(0xFFF06000) /* CMMU data cpu 0 */
164 #define CMMU_I1 U(0xFFF05000) /* CMMU instruction cpu 1 */
165 #define CMMU_D1 U(0xFFF04000) /* CMMU data cpu 1 */
166 #define CMMU_I2 U(0xFFF03000) /* CMMU instruction cpu 2 */
167 #define CMMU_D2 U(0xFFF02000) /* CMMU data cpu 2 */
168 #define CMMU_I3 U(0xFFF01000) /* CMMU instruction cpu 3 */
169 #define CMMU_D3 U(0xFFF00000) /* CMMU data cpu 3 */
170 
171 #endif /* _MACHINE_BOARD_H_ */

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