cpu_arm_coproc.cc Source File
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51 int crn,
int crm,
int rd)
57 fatal(
"arm_coproc_15: opcode1 = %i, should be 0\n", opcode1);
61 fatal(
"arm_coproc_15: rd = PC\n");
76 fatal(
"[ arm_coproc_15: attempt to write "
77 "to the Main ID register? ]\n");
82 fatal(
"[ arm_coproc_15: attempt to write "
83 "to the Cache Type register? ]\n");
85 default:
fatal(
"[ arm_coproc_15: TODO: cr0, opcode2=%i ]\n",
99 default:
fatal(
"Unimplemented opcode2 = %i\n", opcode2);
100 fatal(
"(opcode1=%i crn=%i crm=%i rd=%i l=%i)\n",
101 opcode1, crn, crm, rd, l_bit);
113 debug(
"[ setting the minidata cache attribute"
119 debug(
"[ %s write buffer coalescing ]\n",
121 "Disabling" :
"Enabling");
124 }
else if (opcode2 != 0) {
125 fatal(
"Unimplemented write, opcode2 = %i\n", opcode2);
126 fatal(
"(opcode1=%i crn=%i crm=%i rd=%i l=%i)\n",
127 opcode1, crn, crm, rd, l_bit);
163 fatal(
"ERROR: Trying to switch endianness. Not "
181 fatal(
"[ WARNING! low bits of new TTB non-"
211 fatal(
"[ arm_coproc_15: attempt to read cr7? ]\n");
220 fatal(
"[ arm_coproc_15: attempt to read cr8? ]\n");
234 fatal(
"[ arm_coproc_15: cache lockdown: TODO ]\n");
240 fatal(
"[ arm_coproc_15: PID access, but opcode2 "
241 "= %i? (should be 0) ]\n", opcode2);
243 fatal(
"[ arm_coproc_15: PID access, but crm "
244 "= %i? (should be 0) ]\n", crm);
250 fatal(
"ARM TODO: pid!=0. Fast Context Switch"
251 " Extension not implemented yet\n");
273 default:
fatal(
"[ arm_coproc_15: TODO: IMPLEMENTATION "
279 default:
fatal(
"arm_coproc_15: unimplemented crn = %i\n", crn);
280 fatal(
"(opcode1=%i opcode2=%i crm=%i rd=%i l=%i)\n",
281 opcode1, opcode2, crm, rd, l_bit);
293 int crn,
int crm,
int rd)
297 case 0:
switch (crn) {
300 fatal(
"TODO: XScale read from inten?\n");
310 fatal(
"ARM xscale interrupt steering"
311 " is not yet implemented\n");
320 fatal(
"TODO: XScale int ack?\n");
324 default:
goto unknown;
395 default:
goto unknown;
399 default:
goto unknown;
405 fatal(
"arm_coproc_i80321_6: unimplemented opcode1=%i opcode2=%i crn="
406 "%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn, crm, rd, l_bit);
417 int crn,
int crm,
int rd)
420 fatal(
"TODO: opcode2 = %i\n", opcode2);
426 case 0:
switch (crn) {
450 default:
goto unknown;
454 case 1:
switch (crn) {
480 default:
goto unknown;
484 case 2:
switch (crn) {
505 default:
goto unknown;
509 default:
goto unknown;
515 fatal(
"arm_coproc_xscale_14: unimplemented opcode1=%i opcode2="
516 "%i crn=%i crm=%i rd=%i l=%i)\n", opcode1, opcode2, crn,
int arm_translate_v2p(struct cpu *cpu, uint64_t vaddr64, uint64_t *return_paddr, int flags)
#define ARM_CONTROL_CACHE
struct interrupt tmr1_irq
#define ARM_CONTROL_ALIGN
#define ARM_AUXCTRL_MD_SHIFT
void fatal(const char *fmt,...)
void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
struct interrupt tmr0_irq
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)
int(* translate_v2p)(struct cpu *, uint64_t vaddr, uint64_t *return_paddr, int flags)
void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
#define ARM_CONTROL_WBUFFER
struct arm_cpu_type_def cpu_type
int arm_translate_v2p_mmu(struct cpu *cpu, uint64_t vaddr64, uint64_t *return_paddr, int flags)
#define INTERRUPT_DEASSERT(istruct)
void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, int crn, int crm, int rd)
#define ARM_CONTROL_ICACHE
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