10 uint32_t index0 = addr0 >> 12;
11 uint32_t index1 = addr1 >> 12;
14 page == NULL || (addr0 & 3) || (addr1 & 3)
15 || index1 != index0) {
16 mips32_loadstore[5](
cpu,
ic);
19 addr0 = (addr0 >> 2) & 0x3ff;
20 addr1 = (addr1 >> 2) & 0x3ff;
25 reg(
ic[0].arg[0]) = r0;
26 reg(
ic[1].arg[0]) = r1;
38 uint32_t index0 = addr0 >> 12;
39 uint32_t index1 = addr1 >> 12;
40 uint32_t index2 = addr2 >> 12;
43 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
44 || index1 != index0 || index2 != index0) {
45 mips32_loadstore[5](
cpu,
ic);
48 addr0 = (addr0 >> 2) & 0x3ff;
49 addr1 = (addr1 >> 2) & 0x3ff;
50 addr2 = (addr2 >> 2) & 0x3ff;
57 reg(
ic[0].arg[0]) = r0;
58 reg(
ic[1].arg[0]) = r1;
59 reg(
ic[2].arg[0]) = r2;
72 uint32_t index0 = addr0 >> 12;
73 uint32_t index1 = addr1 >> 12;
74 uint32_t index2 = addr2 >> 12;
75 uint32_t index3 = addr3 >> 12;
78 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
79 || index1 != index0 || index2 != index0 || index3 != index0) {
80 mips32_loadstore[5](
cpu,
ic);
83 addr0 = (addr0 >> 2) & 0x3ff;
84 addr1 = (addr1 >> 2) & 0x3ff;
85 addr2 = (addr2 >> 2) & 0x3ff;
86 addr3 = (addr3 >> 2) & 0x3ff;
95 reg(
ic[0].arg[0]) = r0;
96 reg(
ic[1].arg[0]) = r1;
97 reg(
ic[2].arg[0]) = r2;
98 reg(
ic[3].arg[0]) = r3;
109 uint32_t index0 = addr0 >> 12;
110 uint32_t index1 = addr1 >> 12;
113 page == NULL || (addr0 & 3) || (addr1 & 3)
114 || index1 != index0) {
115 mips32_loadstore[12](
cpu,
ic);
118 addr0 = (addr0 >> 2) & 0x3ff;
119 addr1 = (addr1 >> 2) & 0x3ff;
120 r0 =
reg(
ic[0].arg[0]);
121 r1 =
reg(
ic[1].arg[0]);
137 uint32_t index0 = addr0 >> 12;
138 uint32_t index1 = addr1 >> 12;
139 uint32_t index2 = addr2 >> 12;
142 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
143 || index1 != index0 || index2 != index0) {
144 mips32_loadstore[12](
cpu,
ic);
147 addr0 = (addr0 >> 2) & 0x3ff;
148 addr1 = (addr1 >> 2) & 0x3ff;
149 addr2 = (addr2 >> 2) & 0x3ff;
150 r0 =
reg(
ic[0].arg[0]);
151 r1 =
reg(
ic[1].arg[0]);
152 r2 =
reg(
ic[2].arg[0]);
171 uint32_t index0 = addr0 >> 12;
172 uint32_t index1 = addr1 >> 12;
173 uint32_t index2 = addr2 >> 12;
174 uint32_t index3 = addr3 >> 12;
177 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
178 || index1 != index0 || index2 != index0 || index3 != index0) {
179 mips32_loadstore[12](
cpu,
ic);
182 addr0 = (addr0 >> 2) & 0x3ff;
183 addr1 = (addr1 >> 2) & 0x3ff;
184 addr2 = (addr2 >> 2) & 0x3ff;
185 addr3 = (addr3 >> 2) & 0x3ff;
186 r0 =
reg(
ic[0].arg[0]);
187 r1 =
reg(
ic[1].arg[0]);
188 r2 =
reg(
ic[2].arg[0]);
189 r3 =
reg(
ic[3].arg[0]);
208 uint32_t index0 = addr0 >> 12;
209 uint32_t index1 = addr1 >> 12;
212 page == NULL || (addr0 & 3) || (addr1 & 3)
213 || index1 != index0) {
214 mips32_loadstore[21](
cpu,
ic);
217 addr0 = (addr0 >> 2) & 0x3ff;
218 addr1 = (addr1 >> 2) & 0x3ff;
223 reg(
ic[0].arg[0]) = r0;
224 reg(
ic[1].arg[0]) = r1;
236 uint32_t index0 = addr0 >> 12;
237 uint32_t index1 = addr1 >> 12;
238 uint32_t index2 = addr2 >> 12;
241 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
242 || index1 != index0 || index2 != index0) {
243 mips32_loadstore[21](
cpu,
ic);
246 addr0 = (addr0 >> 2) & 0x3ff;
247 addr1 = (addr1 >> 2) & 0x3ff;
248 addr2 = (addr2 >> 2) & 0x3ff;
255 reg(
ic[0].arg[0]) = r0;
256 reg(
ic[1].arg[0]) = r1;
257 reg(
ic[2].arg[0]) = r2;
270 uint32_t index0 = addr0 >> 12;
271 uint32_t index1 = addr1 >> 12;
272 uint32_t index2 = addr2 >> 12;
273 uint32_t index3 = addr3 >> 12;
276 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
277 || index1 != index0 || index2 != index0 || index3 != index0) {
278 mips32_loadstore[21](
cpu,
ic);
281 addr0 = (addr0 >> 2) & 0x3ff;
282 addr1 = (addr1 >> 2) & 0x3ff;
283 addr2 = (addr2 >> 2) & 0x3ff;
284 addr3 = (addr3 >> 2) & 0x3ff;
293 reg(
ic[0].arg[0]) = r0;
294 reg(
ic[1].arg[0]) = r1;
295 reg(
ic[2].arg[0]) = r2;
296 reg(
ic[3].arg[0]) = r3;
307 uint32_t index0 = addr0 >> 12;
308 uint32_t index1 = addr1 >> 12;
311 page == NULL || (addr0 & 3) || (addr1 & 3)
312 || index1 != index0) {
313 mips32_loadstore[28](
cpu,
ic);
316 addr0 = (addr0 >> 2) & 0x3ff;
317 addr1 = (addr1 >> 2) & 0x3ff;
318 r0 =
reg(
ic[0].arg[0]);
319 r1 =
reg(
ic[1].arg[0]);
335 uint32_t index0 = addr0 >> 12;
336 uint32_t index1 = addr1 >> 12;
337 uint32_t index2 = addr2 >> 12;
340 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3)
341 || index1 != index0 || index2 != index0) {
342 mips32_loadstore[28](
cpu,
ic);
345 addr0 = (addr0 >> 2) & 0x3ff;
346 addr1 = (addr1 >> 2) & 0x3ff;
347 addr2 = (addr2 >> 2) & 0x3ff;
348 r0 =
reg(
ic[0].arg[0]);
349 r1 =
reg(
ic[1].arg[0]);
350 r2 =
reg(
ic[2].arg[0]);
369 uint32_t index0 = addr0 >> 12;
370 uint32_t index1 = addr1 >> 12;
371 uint32_t index2 = addr2 >> 12;
372 uint32_t index3 = addr3 >> 12;
375 page == NULL || (addr0 & 3) || (addr1 & 3) || (addr2 & 3) || (addr3 & 3)
376 || index1 != index0 || index2 != index0 || index3 != index0) {
377 mips32_loadstore[28](
cpu,
ic);
380 addr0 = (addr0 >> 2) & 0x3ff;
381 addr1 = (addr1 >> 2) & 0x3ff;
382 addr2 = (addr2 >> 2) & 0x3ff;
383 addr3 = (addr3 >> 2) & 0x3ff;
384 r0 =
reg(
ic[0].arg[0]);
385 r1 =
reg(
ic[1].arg[0]);
386 r2 =
reg(
ic[2].arg[0]);
387 r3 =
reg(
ic[3].arg[0]);