73 #define DEC21143_TICK_SHIFT 16
123 #define MII_STATE_RESET 0
124 #define MII_STATE_START_WAIT 1
125 #define MII_STATE_READ_OP 2
126 #define MII_STATE_READ_PHYADDR_REGADDR 3
127 #define MII_STATE_A 4
128 #define MII_STATE_D 5
129 #define MII_STATE_IDLE 6
142 unsigned char descr[16];
143 uint32_t rdes0, rdes1, rdes2, rdes3;
144 int bufsize, buf1_size, buf2_size, i, writeback_len = 4, to_xfer;
172 fatal(
"[ dec21143_rx: memory_rw failed! ]\n");
176 rdes0 = descr[0] + (descr[1]<<8) + (descr[2]<<16) + (descr[3]<<24);
187 fatal(
"[ dec21143_rx: memory_rw failed! ]\n");
191 rdes1 = descr[4] + (descr[5]<<8) + (descr[6]<<16) + (descr[7]<<24);
192 rdes2 = descr[8] + (descr[9]<<8) + (descr[10]<<16) + (descr[11]<<24);
193 rdes3 = descr[12] + (descr[13]<<8) + (descr[14]<<16) + (descr[15]<<24);
197 bufaddr = buf1_size? rdes2 : rdes3;
198 bufsize = buf1_size? buf1_size : buf2_size;
211 debug(
"{ RX (%llx): 0x%08x 0x%08x 0x%x 0x%x: buf %i bytes at 0x%x }\n",
212 (
long long)
addr, rdes0, rdes1, rdes2, rdes3, bufsize, (
int)bufaddr);
213 bufaddr &= 0x7fffffff;
219 if (to_xfer > bufsize)
223 for (i=0; i<to_xfer; i++) {
256 descr[ 0] = rdes0; descr[ 1] = rdes0 >> 8;
257 descr[ 2] = rdes0 >> 16; descr[ 3] = rdes0 >> 24;
258 if (writeback_len > 1) {
259 descr[ 4] = rdes1; descr[ 5] = rdes1 >> 8;
260 descr[ 6] = rdes1 >> 16; descr[ 7] = rdes1 >> 24;
261 descr[ 8] = rdes2; descr[ 9] = rdes2 >> 8;
262 descr[10] = rdes2 >> 16; descr[11] = rdes2 >> 24;
263 descr[12] = rdes3; descr[13] = rdes3 >> 8;
264 descr[14] = rdes3 >> 16; descr[15] = rdes3 >> 24;
269 fatal(
"[ dec21143_rx: memory_rw failed! ]\n");
286 unsigned char descr[16];
287 uint32_t tdes0, tdes1, tdes2, tdes3;
288 int bufsize, buf1_size, buf2_size, i;
294 fatal(
"[ dec21143_tx: memory_rw failed! ]\n");
298 tdes0 = descr[0] + (descr[1]<<8) + (descr[2]<<16) + (descr[3]<<24);
316 fatal(
"[ dec21143_tx: memory_rw failed! ]\n");
320 tdes1 = descr[4] + (descr[5]<<8) + (descr[6]<<16) + (descr[7]<<24);
321 tdes2 = descr[8] + (descr[9]<<8) + (descr[10]<<16) + (descr[11]<<24);
322 tdes3 = descr[12] + (descr[13]<<8) + (descr[14]<<16) + (descr[15]<<24);
326 bufaddr = buf1_size? tdes2 : tdes3;
327 bufsize = buf1_size? buf1_size : buf2_size;
344 bufaddr &= 0x7fffffff;
358 fatal(
"[ dec21143: setup packet len = %i, should be"
359 " 192! ]\n", (
int)bufsize);
363 tdes0 = 0x7fffffff; tdes1 = 0xffffffff;
364 tdes2 = 0xffffffff; tdes3 = 0xffffffff;
382 fatal(
"[ dec21143: WARNING! tx: middle "
383 "segment, but no first segment?! ]\n");
390 for (i=0; i<bufsize; i++) {
403 if (d->
net != NULL) {
409 fatal(
"[ dec21143: WARNING! Not "
410 "connected to a network! ]\n");
433 descr[ 0] = tdes0; descr[ 1] = tdes0 >> 8;
434 descr[ 2] = tdes0 >> 16; descr[ 3] = tdes0 >> 24;
435 descr[ 4] = tdes1; descr[ 5] = tdes1 >> 8;
436 descr[ 6] = tdes1 >> 16; descr[ 7] = tdes1 >> 24;
437 descr[ 8] = tdes2; descr[ 9] = tdes2 >> 8;
438 descr[10] = tdes2 >> 16; descr[11] = tdes2 >> 24;
439 descr[12] = tdes3; descr[13] = tdes3 >> 8;
440 descr[14] = tdes3 >> 16; descr[15] = tdes3 >> 24;
444 fatal(
"[ dec21143_tx: memory_rw failed! ]\n");
502 uint32_t oldreg, uint32_t idata)
517 fatal(
"[ mii_access(): MIIROM_BR: TODO ]\n");
526 fatal(
"[ mii_access(): bad dir? ]\n");
595 default:
debug(
"[ mii_access(): UNIMPLEMENTED MII opcode "
596 "%i (probably just a bug in GXemul's "
597 "MII data stream handling) ]\n", d->
mii_opcode);
607 fatal(
"[ mii_access(): write: bad dir? ]\n");
608 obit = obit? (0x8000 >> (d->
mii_bit - 14)) : 0;
613 debug(
"[ mii_access(): WRITE to phyaddr=0x%x "
624 debug(
"[ mii_access(): READ phyaddr=0x%x "
627 ibit = tmp & (0x8000 >> (d->
mii_bit - 13));
668 uint32_t oldreg, uint32_t idata)
715 debug(
"[ dec21143: ROM read from offset"
716 " 0x%03x: 0x%04x ]\n",
718 obit = romword & (0x8000 >>
722 default:
fatal(
"[ dec21243: unimplemented SROM/EEPROM "
761 memset(d->
reg, 0,
sizeof(uint32_t) *
N_REGS);
762 memset(d->
srom, 0,
sizeof(d->
srom));
795 leaf += d->
srom[leaf];
803 leaf += d->
srom[leaf];
817 uint64_t idata = 0, odata = 0;
819 int regnr = relative_addr >> 3;
824 if ((relative_addr & 7) == 0 && regnr <
N_REGS) {
826 odata = d->
reg[regnr];
828 oldreg = d->
reg[regnr];
831 d->
reg[regnr] &= ~(idata & 0x0c01ffff);
835 default:d->
reg[regnr] = idata;
839 fatal(
"[ dec21143: WARNING! unaligned access (0x%x) ]\n",
842 switch (relative_addr) {
848 dec21143_reset(
cpu, d);
856 fatal(
"[ dec21143: UNIMPLEMENTED READ from "
859 dev_dec21143_tick(
cpu, extra);
864 fatal(
"[ dec21143: UNIMPLEMENTED READ from "
866 dev_dec21143_tick(
cpu, extra);
871 debug(
"[ dec21143: setting RXLIST to 0x%x ]\n",
874 fatal(
"[ dec21143: WARNING! RXLIST not aligned"
875 "? (0x%llx) ]\n", (
long long)idata);
883 debug(
"[ dec21143: setting TXLIST to 0x%x ]\n",
886 fatal(
"[ dec21143: WARNING! TXLIST not aligned"
887 "? (0x%llx) ]\n", (
long long)idata);
897 dev_dec21143_tick(
cpu, extra);
903 if (idata & 0x02000000) {
905 idata &= ~0x02000000;
926 fatal(
"[ dec21143: UNIMPLEMENTED OPMODE bits"
927 ": 0x%08x ]\n", (
int)idata);
929 dev_dec21143_tick(
cpu, extra);
939 mii_access(
cpu, d, oldreg, idata);
941 srom_access(
cpu, d, oldreg, idata);
961 fatal(
"[ dec21143: read from unimplemented 0x%02x ]\n",
964 fatal(
"[ dec21143: write to unimplemented 0x%02x: "
965 "0x%02x ]\n", (
int)relative_addr, (
int)idata);
992 snprintf(name2,
sizeof(name2),
"%s [%02x:%02x:%02x:%02x:%02x:%02x]",