i82365reg.h File Reference

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Macros
i82365reg.h File Reference

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Macros

#define PCIC_IOSIZE   2
 
#define PCIC_REG_INDEX   0
 
#define PCIC_REG_DATA   1
 
#define PCIC_CHIP_OFFSET   0x80
 
#define PCIC_SOCKET_OFFSET   0x40
 
#define PCIC_IDENT   0x00 /* RO */
 
#define PCIC_IDENT_IFTYPE_MASK   0xC0
 
#define PCIC_IDENT_IFTYPE_IO_ONLY   0x00
 
#define PCIC_IDENT_IFTYPE_MEM_ONLY   0x40
 
#define PCIC_IDENT_IFTYPE_MEM_AND_IO   0x80
 
#define PCIC_IDENT_IFTYPE_RESERVED   0xC0
 
#define PCIC_IDENT_ZERO   0x30
 
#define PCIC_IDENT_REV_MASK   0x0F
 
#define PCIC_IDENT_REV_I82365SLR0   0x02
 
#define PCIC_IDENT_REV_I82365SLR1   0x03
 
#define PCIC_IDENT_ID_INTEL0   0x82
 
#define PCIC_IDENT_ID_INTEL1   0x83
 
#define PCIC_IDENT_ID_INTEL2   0x84
 
#define PCIC_IDENT_ID_IBM1   0x88
 
#define PCIC_IDENT_ID_IBM2   0x89
 
#define PCIC_IDENT_ID_IBM3   0x8A
 
#define PCIC_IF_STATUS   0x01 /* RO */
 
#define PCIC_IF_STATUS_GPI   0x80 /* General Purpose Input */
 
#define PCIC_IF_STATUS_POWERACTIVE   0x40
 
#define PCIC_IF_STATUS_READY   0x20 /* really READY/!BUSY */
 
#define PCIC_IF_STATUS_MEM_WP   0x10
 
#define PCIC_IF_STATUS_CARDDETECT_MASK   0x0C
 
#define PCIC_IF_STATUS_CARDDETECT_PRESENT   0x0C
 
#define PCIC_IF_STATUS_BATTERY_MASK   0x03
 
#define PCIC_IF_STATUS_BATTERY_DEAD1   0x00
 
#define PCIC_IF_STATUS_BATTERY_DEAD2   0x01
 
#define PCIC_IF_STATUS_BATTERY_WARNING   0x02
 
#define PCIC_IF_STATUS_BATTERY_GOOD   0x03
 
#define PCIC_PWRCTL   0x02 /* RW */
 
#define PCIC_PWRCTL_OE   0x80 /* output enable */
 
#define PCIC_PWRCTL_DISABLE_RESETDRV   0x40
 
#define PCIC_PWRCTL_AUTOSWITCH_ENABLE   0x20
 
#define PCIC_PWRCTL_PWR_ENABLE   0x10
 
#define PCIC_PWRCTL_VPP2_MASK   0x0C
 
#define PCIC_PWRCTL_VPP2_RESERVED   0x0C
 
#define PCIC_PWRCTL_VPP2_12V   0x08
 
#define PCIC_PWRCTL_VPP2_VCC   0x04
 
#define PCIC_PWRCTL_VPP2_OFF   0x00
 
#define PCIC_PWRCTL_VPP1_MASK   0x03
 
#define PCIC_PWRCTL_VPP1_RESERVED   0x03
 
#define PCIC_PWRCTL_VPP1_12V   0x02
 
#define PCIC_PWRCTL_VPP1_VCC   0x01
 
#define PCIC_PWRCTL_VPP1_OFF   0x00
 
#define PCIC_CSC   0x04 /* RO */
 
#define PCIC_CSC_ZERO   0xE0
 
#define PCIC_CSC_GPI   0x10
 
#define PCIC_CSC_CD   0x08 /* Card Detect Change */
 
#define PCIC_CSC_READY   0x04
 
#define PCIC_CSC_BATTWARN   0x02
 
#define PCIC_CSC_BATTDEAD   0x01 /* for memory cards */
 
#define PCIC_CSC_RI   0x01 /* for i/o cards */
 
#define PCIC_ADDRWIN_ENABLE   0x06 /* RW */
 
#define PCIC_ADDRWIN_ENABLE_IO1   0x80
 
#define PCIC_ADDRWIN_ENABLE_IO0   0x40
 
#define PCIC_ADDRWIN_ENABLE_MEMCS16   0x20 /* rtfds if you care */
 
#define PCIC_ADDRWIN_ENABLE_MEM4   0x10
 
#define PCIC_ADDRWIN_ENABLE_MEM3   0x08
 
#define PCIC_ADDRWIN_ENABLE_MEM2   0x04
 
#define PCIC_ADDRWIN_ENABLE_MEM1   0x02
 
#define PCIC_ADDRWIN_ENABLE_MEM0   0x01
 
#define PCIC_CARD_DETECT   0x16 /* RW */
 
#define PCIC_CARD_DETECT_RESERVED   0xC0
 
#define PCIC_CARD_DETECT_SW_INTR   0x20
 
#define PCIC_CARD_DETECT_RESUME_ENABLE   0x10
 
#define PCIC_CARD_DETECT_GPI_TRANSCTL   0x08
 
#define PCIC_CARD_DETECT_GPI_ENABLE   0x04
 
#define PCIC_CARD_DETECT_CFGRST_ENABLE   0x02
 
#define PCIC_CARD_DETECT_MEMDLY_INHIBIT   0x01
 
#define PCIC_INTR   0x03 /* RW */
 
#define PCIC_INTR_RI_ENABLE   0x80
 
#define PCIC_INTR_RESET   0x40 /* active low (zero) */
 
#define PCIC_INTR_CARDTYPE_MASK   0x20
 
#define PCIC_INTR_CARDTYPE_IO   0x20
 
#define PCIC_INTR_CARDTYPE_MEM   0x00
 
#define PCIC_INTR_ENABLE   0x10
 
#define PCIC_INTR_IRQ_MASK   0x0F
 
#define PCIC_INTR_IRQ_SHIFT   0
 
#define PCIC_INTR_IRQ_NONE   0x00
 
#define PCIC_INTR_IRQ_RESERVED1   0x01
 
#define PCIC_INTR_IRQ_RESERVED2   0x02
 
#define PCIC_INTR_IRQ3   0x03
 
#define PCIC_INTR_IRQ4   0x04
 
#define PCIC_INTR_IRQ5   0x05
 
#define PCIC_INTR_IRQ_RESERVED6   0x06
 
#define PCIC_INTR_IRQ7   0x07
 
#define PCIC_INTR_IRQ_RESERVED8   0x08
 
#define PCIC_INTR_IRQ9   0x09
 
#define PCIC_INTR_IRQ10   0x0A
 
#define PCIC_INTR_IRQ11   0x0B
 
#define PCIC_INTR_IRQ12   0x0C
 
#define PCIC_INTR_IRQ_RESERVED13   0x0D
 
#define PCIC_INTR_IRQ14   0x0E
 
#define PCIC_INTR_IRQ15   0x0F
 
#define PCIC_INTR_IRQ_VALIDMASK   0xDEB8 /* 1101 1110 1011 1000 */
 
#define PCIC_CSC_INTR   0x05 /* RW */
 
#define PCIC_CSC_INTR_IRQ_MASK   0xF0
 
#define PCIC_CSC_INTR_IRQ_SHIFT   4
 
#define PCIC_CSC_INTR_IRQ_NONE   0x00
 
#define PCIC_CSC_INTR_IRQ_RESERVED1   0x10
 
#define PCIC_CSC_INTR_IRQ_RESERVED2   0x20
 
#define PCIC_CSC_INTR_IRQ3   0x30
 
#define PCIC_CSC_INTR_IRQ4   0x40
 
#define PCIC_CSC_INTR_IRQ5   0x50
 
#define PCIC_CSC_INTR_IRQ_RESERVED6   0x60
 
#define PCIC_CSC_INTR_IRQ7   0x70
 
#define PCIC_CSC_INTR_IRQ_RESERVED8   0x80
 
#define PCIC_CSC_INTR_IRQ9   0x90
 
#define PCIC_CSC_INTR_IRQ10   0xA0
 
#define PCIC_CSC_INTR_IRQ11   0xB0
 
#define PCIC_CSC_INTR_IRQ12   0xC0
 
#define PCIC_CSC_INTR_IRQ_RESERVED13   0xD0
 
#define PCIC_CSC_INTR_IRQ14   0xE0
 
#define PCIC_CSC_INTR_IRQ15   0xF0
 
#define PCIC_CSC_INTR_CD_ENABLE   0x08
 
#define PCIC_CSC_INTR_READY_ENABLE   0x04
 
#define PCIC_CSC_INTR_BATTWARN_ENABLE   0x02
 
#define PCIC_CSC_INTR_BATTDEAD_ENABLE   0x01 /* for memory cards */
 
#define PCIC_CSC_INTR_RI_ENABLE   0x01 /* for I/O cards */
 
#define PCIC_CSC_INTR_FORMAT
 
#define PCIC_CSC_INTR_IRQ_VALIDMASK   0xDEB8 /* 1101 1110 1011 1000 */
 
#define PCIC_IO_WINS   2
 
#define PCIC_IOCTL   0x07 /* RW */
 
#define PCIC_IOCTL_IO1_WAITSTATE   0x80
 
#define PCIC_IOCTL_IO1_ZEROWAIT   0x40
 
#define PCIC_IOCTL_IO1_IOCS16SRC_MASK   0x20
 
#define PCIC_IOCTL_IO1_IOCS16SRC_CARD   0x20
 
#define PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE   0x00
 
#define PCIC_IOCTL_IO1_DATASIZE_MASK   0x10
 
#define PCIC_IOCTL_IO1_DATASIZE_16BIT   0x10
 
#define PCIC_IOCTL_IO1_DATASIZE_8BIT   0x00
 
#define PCIC_IOCTL_IO0_WAITSTATE   0x08
 
#define PCIC_IOCTL_IO0_ZEROWAIT   0x04
 
#define PCIC_IOCTL_IO0_IOCS16SRC_MASK   0x02
 
#define PCIC_IOCTL_IO0_IOCS16SRC_CARD   0x02
 
#define PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE   0x00
 
#define PCIC_IOCTL_IO0_DATASIZE_MASK   0x01
 
#define PCIC_IOCTL_IO0_DATASIZE_16BIT   0x01
 
#define PCIC_IOCTL_IO0_DATASIZE_8BIT   0x00
 
#define PCIC_IOADDR0_START_LSB   0x08
 
#define PCIC_IOADDR0_START_MSB   0x09
 
#define PCIC_IOADDR0_STOP_LSB   0x0A
 
#define PCIC_IOADDR0_STOP_MSB   0x0B
 
#define PCIC_IOADDR1_START_LSB   0x0C
 
#define PCIC_IOADDR1_START_MSB   0x0D
 
#define PCIC_IOADDR1_STOP_LSB   0x0E
 
#define PCIC_IOADDR1_STOP_MSB   0x0F
 
#define PCIC_MEM_WINS   5
 
#define PCIC_MEM_SHIFT   12
 
#define PCIC_MEM_PAGESIZE   (1<<PCIC_MEM_SHIFT)
 
#define PCIC_SYSMEM_ADDRX_SHIFT   PCIC_MEM_SHIFT
 
#define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK   0x80
 
#define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT   0x80
 
#define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT   0x00
 
#define PCIC_SYSMEM_ADDRX_START_MSB_ZEROWAIT   0x40
 
#define PCIC_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK   0x30
 
#define PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK   0x0F
 
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK   0xC0
 
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT0   0x00
 
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT1   0x40
 
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2   0x80
 
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT3   0xC0
 
#define PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK   0x0F
 
#define PCIC_CARDMEM_ADDRX_SHIFT   PCIC_MEM_SHIFT
 
#define PCIC_CARDMEM_ADDRX_MSB_WP   0x80
 
#define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_MASK   0x40
 
#define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR   0x40
 
#define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON   0x00
 
#define PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK   0x3F
 
#define PCIC_SYSMEM_ADDR0_START_LSB   0x10
 
#define PCIC_SYSMEM_ADDR0_START_MSB   0x11
 
#define PCIC_SYSMEM_ADDR0_STOP_LSB   0x12
 
#define PCIC_SYSMEM_ADDR0_STOP_MSB   0x13
 
#define PCIC_CARDMEM_ADDR0_LSB   0x14
 
#define PCIC_CARDMEM_ADDR0_MSB   0x15
 
#define PCIC_SYSMEM_ADDR1_START_LSB   0x18
 
#define PCIC_SYSMEM_ADDR1_START_MSB   0x19
 
#define PCIC_SYSMEM_ADDR1_STOP_LSB   0x1A
 
#define PCIC_SYSMEM_ADDR1_STOP_MSB   0x1B
 
#define PCIC_CARDMEM_ADDR1_LSB   0x1C
 
#define PCIC_CARDMEM_ADDR1_MSB   0x1D
 
#define PCIC_SYSMEM_ADDR2_START_LSB   0x20
 
#define PCIC_SYSMEM_ADDR2_START_MSB   0x21
 
#define PCIC_SYSMEM_ADDR2_STOP_LSB   0x22
 
#define PCIC_SYSMEM_ADDR2_STOP_MSB   0x23
 
#define PCIC_CARDMEM_ADDR2_LSB   0x24
 
#define PCIC_CARDMEM_ADDR2_MSB   0x25
 
#define PCIC_SYSMEM_ADDR3_START_LSB   0x28
 
#define PCIC_SYSMEM_ADDR3_START_MSB   0x29
 
#define PCIC_SYSMEM_ADDR3_STOP_LSB   0x2A
 
#define PCIC_SYSMEM_ADDR3_STOP_MSB   0x2B
 
#define PCIC_CARDMEM_ADDR3_LSB   0x2C
 
#define PCIC_CARDMEM_ADDR3_MSB   0x2D
 
#define PCIC_SYSMEM_ADDR4_START_LSB   0x30
 
#define PCIC_SYSMEM_ADDR4_START_MSB   0x31
 
#define PCIC_SYSMEM_ADDR4_STOP_LSB   0x32
 
#define PCIC_SYSMEM_ADDR4_STOP_MSB   0x33
 
#define PCIC_CARDMEM_ADDR4_LSB   0x34
 
#define PCIC_CARDMEM_ADDR4_MSB   0x35
 
#define PCIC_INTEL_GLOBAL_CTL   0x1E /* RW */
 
#define PCIC_INTEL_GLOBAL_CTL_RESERVED   0xF0
 
#define PCIC_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE   0x08
 
#define PCIC_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK   0x04
 
#define PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE   0x02
 
#define PCIC_INTEL_GLOBAL_CTL_POWERDOWN   0x01
 
#define PCIC_CIRRUS_MISC_CTL_1   0x16 /* RW */
 
#define PCIC_CIRRUS_MISC_CTL_1_SPKR_ENABLE   0x10
 
#define PCIC_CIRRUS_FIFO_CTL   0x17 /* RW */
 
#define PCIC_CIRRUS_FIFO_CTL_EMPTY   0x80 /* I/O read */
 
#define PCIC_CIRRUS_FIFO_CTL_FLUSH   0x80 /* I/O write */
 
#define PCIC_CIRRUS_MISC_CTL_2   0x1E /* RW */
 
#define PCIC_CIRRUS_MISC_CTL_2_SUSPEND   0x04
 
#define PCIC_CIRRUS_MISC_CTL_2_LP_DYNAMIC_MODE   0x02
 
#define PCIC_CIRRUS_CHIP_INFO   0x1F
 
#define PCIC_CIRRUS_CHIP_INFO_CHIP_ID   0xC0
 
#define PCIC_CIRRUS_CHIP_INFO_SLOTS   0x20
 
#define PCIC_CIRRUS_CHIP_INFO_REV   0x1F
 
#define PCIC_CIRRUS_EXTENDED_INDEX   0x2E
 
#define PCIC_CIRRUS_EXTENDED_DATA   0x2F
 
#define PCIC_CIRRUS_EXT_CONTROL_1   0x03
 
#define PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK   0x18
 
#define PCIC_CIRRUS_PROD_ID   0x35 /* RO */
 
#define PCIC_CIRRUS_PROD_ID_FAM_MASK   0xF0
 
#define PCIC_CIRRUS_PROD_ID_FAM_PD6729   0x20
 
#define PCIC_CIRRUS_PROD_ID_PROD_MASK   0x0F
 
#define PCIC_CIRRUS_PROD_ID_PROD_PD6729   0x00
 
#define PCIC_RICOH_REG_CHIP_ID   0x3A
 
#define PCIC_RICOH_CHIP_ID_5C296   0x32
 
#define PCIC_RICOH_CHIP_ID_5C396   0xB2
 
#define PCIC_RICOH_REG_MCR2   0x2F
 
#define PCIC_RICOH_MCR2_VCC_DIRECT   0x08
 
#define PCIC_RICOH_MCR2_VCC_SEL_MASK   0x01
 
#define PCIC_RICOH_MCR2_VCC_SEL_3V   0x01
 
#define PCIC_RICOH_MCR2_VCC_SEL_5V   0x00
 

Macro Definition Documentation

◆ PCIC_ADDRWIN_ENABLE

#define PCIC_ADDRWIN_ENABLE   0x06 /* RW */

Definition at line 115 of file i82365reg.h.

◆ PCIC_ADDRWIN_ENABLE_IO0

#define PCIC_ADDRWIN_ENABLE_IO0   0x40

Definition at line 117 of file i82365reg.h.

◆ PCIC_ADDRWIN_ENABLE_IO1

#define PCIC_ADDRWIN_ENABLE_IO1   0x80

Definition at line 116 of file i82365reg.h.

◆ PCIC_ADDRWIN_ENABLE_MEM0

#define PCIC_ADDRWIN_ENABLE_MEM0   0x01

Definition at line 123 of file i82365reg.h.

◆ PCIC_ADDRWIN_ENABLE_MEM1

#define PCIC_ADDRWIN_ENABLE_MEM1   0x02

Definition at line 122 of file i82365reg.h.

◆ PCIC_ADDRWIN_ENABLE_MEM2

#define PCIC_ADDRWIN_ENABLE_MEM2   0x04

Definition at line 121 of file i82365reg.h.

◆ PCIC_ADDRWIN_ENABLE_MEM3

#define PCIC_ADDRWIN_ENABLE_MEM3   0x08

Definition at line 120 of file i82365reg.h.

◆ PCIC_ADDRWIN_ENABLE_MEM4

#define PCIC_ADDRWIN_ENABLE_MEM4   0x10

Definition at line 119 of file i82365reg.h.

◆ PCIC_ADDRWIN_ENABLE_MEMCS16

#define PCIC_ADDRWIN_ENABLE_MEMCS16   0x20 /* rtfds if you care */

Definition at line 118 of file i82365reg.h.

◆ PCIC_CARD_DETECT

#define PCIC_CARD_DETECT   0x16 /* RW */

Definition at line 126 of file i82365reg.h.

◆ PCIC_CARD_DETECT_CFGRST_ENABLE

#define PCIC_CARD_DETECT_CFGRST_ENABLE   0x02

Definition at line 132 of file i82365reg.h.

◆ PCIC_CARD_DETECT_GPI_ENABLE

#define PCIC_CARD_DETECT_GPI_ENABLE   0x04

Definition at line 131 of file i82365reg.h.

◆ PCIC_CARD_DETECT_GPI_TRANSCTL

#define PCIC_CARD_DETECT_GPI_TRANSCTL   0x08

Definition at line 130 of file i82365reg.h.

◆ PCIC_CARD_DETECT_MEMDLY_INHIBIT

#define PCIC_CARD_DETECT_MEMDLY_INHIBIT   0x01

Definition at line 133 of file i82365reg.h.

◆ PCIC_CARD_DETECT_RESERVED

#define PCIC_CARD_DETECT_RESERVED   0xC0

Definition at line 127 of file i82365reg.h.

◆ PCIC_CARD_DETECT_RESUME_ENABLE

#define PCIC_CARD_DETECT_RESUME_ENABLE   0x10

Definition at line 129 of file i82365reg.h.

◆ PCIC_CARD_DETECT_SW_INTR

#define PCIC_CARD_DETECT_SW_INTR   0x20

Definition at line 128 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDR0_LSB

#define PCIC_CARDMEM_ADDR0_LSB   0x14

Definition at line 275 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDR0_MSB

#define PCIC_CARDMEM_ADDR0_MSB   0x15

Definition at line 276 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDR1_LSB

#define PCIC_CARDMEM_ADDR1_LSB   0x1C

Definition at line 285 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDR1_MSB

#define PCIC_CARDMEM_ADDR1_MSB   0x1D

Definition at line 286 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDR2_LSB

#define PCIC_CARDMEM_ADDR2_LSB   0x24

Definition at line 293 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDR2_MSB

#define PCIC_CARDMEM_ADDR2_MSB   0x25

Definition at line 294 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDR3_LSB

#define PCIC_CARDMEM_ADDR3_LSB   0x2C

Definition at line 304 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDR3_MSB

#define PCIC_CARDMEM_ADDR3_MSB   0x2D

Definition at line 305 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDR4_LSB

#define PCIC_CARDMEM_ADDR4_LSB   0x34

Definition at line 315 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDR4_MSB

#define PCIC_CARDMEM_ADDR4_MSB   0x35

Definition at line 316 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK

#define PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK   0x3F

Definition at line 268 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR

#define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR   0x40

Definition at line 266 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON

#define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON   0x00

Definition at line 267 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_MASK

#define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_MASK   0x40

Definition at line 265 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDRX_MSB_WP

#define PCIC_CARDMEM_ADDRX_MSB_WP   0x80

Definition at line 264 of file i82365reg.h.

◆ PCIC_CARDMEM_ADDRX_SHIFT

#define PCIC_CARDMEM_ADDRX_SHIFT   PCIC_MEM_SHIFT

Definition at line 263 of file i82365reg.h.

◆ PCIC_CHIP_OFFSET

#define PCIC_CHIP_OFFSET   0x80

Definition at line 54 of file i82365reg.h.

◆ PCIC_CIRRUS_CHIP_INFO

#define PCIC_CIRRUS_CHIP_INFO   0x1F

Definition at line 349 of file i82365reg.h.

◆ PCIC_CIRRUS_CHIP_INFO_CHIP_ID

#define PCIC_CIRRUS_CHIP_INFO_CHIP_ID   0xC0

Definition at line 350 of file i82365reg.h.

◆ PCIC_CIRRUS_CHIP_INFO_REV

#define PCIC_CIRRUS_CHIP_INFO_REV   0x1F

Definition at line 352 of file i82365reg.h.

◆ PCIC_CIRRUS_CHIP_INFO_SLOTS

#define PCIC_CIRRUS_CHIP_INFO_SLOTS   0x20

Definition at line 351 of file i82365reg.h.

◆ PCIC_CIRRUS_EXT_CONTROL_1

#define PCIC_CIRRUS_EXT_CONTROL_1   0x03

Definition at line 357 of file i82365reg.h.

◆ PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK

#define PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK   0x18

Definition at line 358 of file i82365reg.h.

◆ PCIC_CIRRUS_EXTENDED_DATA

#define PCIC_CIRRUS_EXTENDED_DATA   0x2F

Definition at line 355 of file i82365reg.h.

◆ PCIC_CIRRUS_EXTENDED_INDEX

#define PCIC_CIRRUS_EXTENDED_INDEX   0x2E

Definition at line 354 of file i82365reg.h.

◆ PCIC_CIRRUS_FIFO_CTL

#define PCIC_CIRRUS_FIFO_CTL   0x17 /* RW */

Definition at line 341 of file i82365reg.h.

◆ PCIC_CIRRUS_FIFO_CTL_EMPTY

#define PCIC_CIRRUS_FIFO_CTL_EMPTY   0x80 /* I/O read */

Definition at line 342 of file i82365reg.h.

◆ PCIC_CIRRUS_FIFO_CTL_FLUSH

#define PCIC_CIRRUS_FIFO_CTL_FLUSH   0x80 /* I/O write */

Definition at line 343 of file i82365reg.h.

◆ PCIC_CIRRUS_MISC_CTL_1

#define PCIC_CIRRUS_MISC_CTL_1   0x16 /* RW */

Definition at line 338 of file i82365reg.h.

◆ PCIC_CIRRUS_MISC_CTL_1_SPKR_ENABLE

#define PCIC_CIRRUS_MISC_CTL_1_SPKR_ENABLE   0x10

Definition at line 339 of file i82365reg.h.

◆ PCIC_CIRRUS_MISC_CTL_2

#define PCIC_CIRRUS_MISC_CTL_2   0x1E /* RW */

Definition at line 345 of file i82365reg.h.

◆ PCIC_CIRRUS_MISC_CTL_2_LP_DYNAMIC_MODE

#define PCIC_CIRRUS_MISC_CTL_2_LP_DYNAMIC_MODE   0x02

Definition at line 347 of file i82365reg.h.

◆ PCIC_CIRRUS_MISC_CTL_2_SUSPEND

#define PCIC_CIRRUS_MISC_CTL_2_SUSPEND   0x04

Definition at line 346 of file i82365reg.h.

◆ PCIC_CIRRUS_PROD_ID

#define PCIC_CIRRUS_PROD_ID   0x35 /* RO */

Definition at line 360 of file i82365reg.h.

◆ PCIC_CIRRUS_PROD_ID_FAM_MASK

#define PCIC_CIRRUS_PROD_ID_FAM_MASK   0xF0

Definition at line 361 of file i82365reg.h.

◆ PCIC_CIRRUS_PROD_ID_FAM_PD6729

#define PCIC_CIRRUS_PROD_ID_FAM_PD6729   0x20

Definition at line 362 of file i82365reg.h.

◆ PCIC_CIRRUS_PROD_ID_PROD_MASK

#define PCIC_CIRRUS_PROD_ID_PROD_MASK   0x0F

Definition at line 363 of file i82365reg.h.

◆ PCIC_CIRRUS_PROD_ID_PROD_PD6729

#define PCIC_CIRRUS_PROD_ID_PROD_PD6729   0x00

Definition at line 364 of file i82365reg.h.

◆ PCIC_CSC

#define PCIC_CSC   0x04 /* RO */

Definition at line 106 of file i82365reg.h.

◆ PCIC_CSC_BATTDEAD

#define PCIC_CSC_BATTDEAD   0x01 /* for memory cards */

Definition at line 112 of file i82365reg.h.

◆ PCIC_CSC_BATTWARN

#define PCIC_CSC_BATTWARN   0x02

Definition at line 111 of file i82365reg.h.

◆ PCIC_CSC_CD

#define PCIC_CSC_CD   0x08 /* Card Detect Change */

Definition at line 109 of file i82365reg.h.

◆ PCIC_CSC_GPI

#define PCIC_CSC_GPI   0x10

Definition at line 108 of file i82365reg.h.

◆ PCIC_CSC_INTR

#define PCIC_CSC_INTR   0x05 /* RW */

Definition at line 165 of file i82365reg.h.

◆ PCIC_CSC_INTR_BATTDEAD_ENABLE

#define PCIC_CSC_INTR_BATTDEAD_ENABLE   0x01 /* for memory cards */

Definition at line 187 of file i82365reg.h.

◆ PCIC_CSC_INTR_BATTWARN_ENABLE

#define PCIC_CSC_INTR_BATTWARN_ENABLE   0x02

Definition at line 186 of file i82365reg.h.

◆ PCIC_CSC_INTR_CD_ENABLE

#define PCIC_CSC_INTR_CD_ENABLE   0x08

Definition at line 184 of file i82365reg.h.

◆ PCIC_CSC_INTR_FORMAT

#define PCIC_CSC_INTR_FORMAT
Value:
"\177\020" "f\4\4CSC_INTR_IRQ\0" \
"b\0RI\0" \
"b\1BATTWARN\0" \
"b\2READY\0" \
"b\3CD\0"

Definition at line 190 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ10

#define PCIC_CSC_INTR_IRQ10   0xA0

Definition at line 178 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ11

#define PCIC_CSC_INTR_IRQ11   0xB0

Definition at line 179 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ12

#define PCIC_CSC_INTR_IRQ12   0xC0

Definition at line 180 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ14

#define PCIC_CSC_INTR_IRQ14   0xE0

Definition at line 182 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ15

#define PCIC_CSC_INTR_IRQ15   0xF0

Definition at line 183 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ3

#define PCIC_CSC_INTR_IRQ3   0x30

Definition at line 171 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ4

#define PCIC_CSC_INTR_IRQ4   0x40

Definition at line 172 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ5

#define PCIC_CSC_INTR_IRQ5   0x50

Definition at line 173 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ7

#define PCIC_CSC_INTR_IRQ7   0x70

Definition at line 175 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ9

#define PCIC_CSC_INTR_IRQ9   0x90

Definition at line 177 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ_MASK

#define PCIC_CSC_INTR_IRQ_MASK   0xF0

Definition at line 166 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ_NONE

#define PCIC_CSC_INTR_IRQ_NONE   0x00

Definition at line 168 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ_RESERVED1

#define PCIC_CSC_INTR_IRQ_RESERVED1   0x10

Definition at line 169 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ_RESERVED13

#define PCIC_CSC_INTR_IRQ_RESERVED13   0xD0

Definition at line 181 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ_RESERVED2

#define PCIC_CSC_INTR_IRQ_RESERVED2   0x20

Definition at line 170 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ_RESERVED6

#define PCIC_CSC_INTR_IRQ_RESERVED6   0x60

Definition at line 174 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ_RESERVED8

#define PCIC_CSC_INTR_IRQ_RESERVED8   0x80

Definition at line 176 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ_SHIFT

#define PCIC_CSC_INTR_IRQ_SHIFT   4

Definition at line 167 of file i82365reg.h.

◆ PCIC_CSC_INTR_IRQ_VALIDMASK

#define PCIC_CSC_INTR_IRQ_VALIDMASK   0xDEB8 /* 1101 1110 1011 1000 */

Definition at line 196 of file i82365reg.h.

◆ PCIC_CSC_INTR_READY_ENABLE

#define PCIC_CSC_INTR_READY_ENABLE   0x04

Definition at line 185 of file i82365reg.h.

◆ PCIC_CSC_INTR_RI_ENABLE

#define PCIC_CSC_INTR_RI_ENABLE   0x01 /* for I/O cards */

Definition at line 188 of file i82365reg.h.

◆ PCIC_CSC_READY

#define PCIC_CSC_READY   0x04

Definition at line 110 of file i82365reg.h.

◆ PCIC_CSC_RI

#define PCIC_CSC_RI   0x01 /* for i/o cards */

Definition at line 113 of file i82365reg.h.

◆ PCIC_CSC_ZERO

#define PCIC_CSC_ZERO   0xE0

Definition at line 107 of file i82365reg.h.

◆ PCIC_IDENT

#define PCIC_IDENT   0x00 /* RO */

Definition at line 59 of file i82365reg.h.

◆ PCIC_IDENT_ID_IBM1

#define PCIC_IDENT_ID_IBM1   0x88

Definition at line 73 of file i82365reg.h.

◆ PCIC_IDENT_ID_IBM2

#define PCIC_IDENT_ID_IBM2   0x89

Definition at line 74 of file i82365reg.h.

◆ PCIC_IDENT_ID_IBM3

#define PCIC_IDENT_ID_IBM3   0x8A

Definition at line 75 of file i82365reg.h.

◆ PCIC_IDENT_ID_INTEL0

#define PCIC_IDENT_ID_INTEL0   0x82

Definition at line 70 of file i82365reg.h.

◆ PCIC_IDENT_ID_INTEL1

#define PCIC_IDENT_ID_INTEL1   0x83

Definition at line 71 of file i82365reg.h.

◆ PCIC_IDENT_ID_INTEL2

#define PCIC_IDENT_ID_INTEL2   0x84

Definition at line 72 of file i82365reg.h.

◆ PCIC_IDENT_IFTYPE_IO_ONLY

#define PCIC_IDENT_IFTYPE_IO_ONLY   0x00

Definition at line 61 of file i82365reg.h.

◆ PCIC_IDENT_IFTYPE_MASK

#define PCIC_IDENT_IFTYPE_MASK   0xC0

Definition at line 60 of file i82365reg.h.

◆ PCIC_IDENT_IFTYPE_MEM_AND_IO

#define PCIC_IDENT_IFTYPE_MEM_AND_IO   0x80

Definition at line 63 of file i82365reg.h.

◆ PCIC_IDENT_IFTYPE_MEM_ONLY

#define PCIC_IDENT_IFTYPE_MEM_ONLY   0x40

Definition at line 62 of file i82365reg.h.

◆ PCIC_IDENT_IFTYPE_RESERVED

#define PCIC_IDENT_IFTYPE_RESERVED   0xC0

Definition at line 64 of file i82365reg.h.

◆ PCIC_IDENT_REV_I82365SLR0

#define PCIC_IDENT_REV_I82365SLR0   0x02

Definition at line 67 of file i82365reg.h.

◆ PCIC_IDENT_REV_I82365SLR1

#define PCIC_IDENT_REV_I82365SLR1   0x03

Definition at line 68 of file i82365reg.h.

◆ PCIC_IDENT_REV_MASK

#define PCIC_IDENT_REV_MASK   0x0F

Definition at line 66 of file i82365reg.h.

◆ PCIC_IDENT_ZERO

#define PCIC_IDENT_ZERO   0x30

Definition at line 65 of file i82365reg.h.

◆ PCIC_IF_STATUS

#define PCIC_IF_STATUS   0x01 /* RO */

Definition at line 77 of file i82365reg.h.

◆ PCIC_IF_STATUS_BATTERY_DEAD1

#define PCIC_IF_STATUS_BATTERY_DEAD1   0x00

Definition at line 85 of file i82365reg.h.

◆ PCIC_IF_STATUS_BATTERY_DEAD2

#define PCIC_IF_STATUS_BATTERY_DEAD2   0x01

Definition at line 86 of file i82365reg.h.

◆ PCIC_IF_STATUS_BATTERY_GOOD

#define PCIC_IF_STATUS_BATTERY_GOOD   0x03

Definition at line 88 of file i82365reg.h.

◆ PCIC_IF_STATUS_BATTERY_MASK

#define PCIC_IF_STATUS_BATTERY_MASK   0x03

Definition at line 84 of file i82365reg.h.

◆ PCIC_IF_STATUS_BATTERY_WARNING

#define PCIC_IF_STATUS_BATTERY_WARNING   0x02

Definition at line 87 of file i82365reg.h.

◆ PCIC_IF_STATUS_CARDDETECT_MASK

#define PCIC_IF_STATUS_CARDDETECT_MASK   0x0C

Definition at line 82 of file i82365reg.h.

◆ PCIC_IF_STATUS_CARDDETECT_PRESENT

#define PCIC_IF_STATUS_CARDDETECT_PRESENT   0x0C

Definition at line 83 of file i82365reg.h.

◆ PCIC_IF_STATUS_GPI

#define PCIC_IF_STATUS_GPI   0x80 /* General Purpose Input */

Definition at line 78 of file i82365reg.h.

◆ PCIC_IF_STATUS_MEM_WP

#define PCIC_IF_STATUS_MEM_WP   0x10

Definition at line 81 of file i82365reg.h.

◆ PCIC_IF_STATUS_POWERACTIVE

#define PCIC_IF_STATUS_POWERACTIVE   0x40

Definition at line 79 of file i82365reg.h.

◆ PCIC_IF_STATUS_READY

#define PCIC_IF_STATUS_READY   0x20 /* really READY/!BUSY */

Definition at line 80 of file i82365reg.h.

◆ PCIC_INTEL_GLOBAL_CTL

#define PCIC_INTEL_GLOBAL_CTL   0x1E /* RW */

Definition at line 331 of file i82365reg.h.

◆ PCIC_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK

#define PCIC_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK   0x04

Definition at line 334 of file i82365reg.h.

◆ PCIC_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE

#define PCIC_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE   0x08

Definition at line 333 of file i82365reg.h.

◆ PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE

#define PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE   0x02

Definition at line 335 of file i82365reg.h.

◆ PCIC_INTEL_GLOBAL_CTL_POWERDOWN

#define PCIC_INTEL_GLOBAL_CTL_POWERDOWN   0x01

Definition at line 336 of file i82365reg.h.

◆ PCIC_INTEL_GLOBAL_CTL_RESERVED

#define PCIC_INTEL_GLOBAL_CTL_RESERVED   0xF0

Definition at line 332 of file i82365reg.h.

◆ PCIC_INTR

#define PCIC_INTR   0x03 /* RW */

Definition at line 137 of file i82365reg.h.

◆ PCIC_INTR_CARDTYPE_IO

#define PCIC_INTR_CARDTYPE_IO   0x20

Definition at line 141 of file i82365reg.h.

◆ PCIC_INTR_CARDTYPE_MASK

#define PCIC_INTR_CARDTYPE_MASK   0x20

Definition at line 140 of file i82365reg.h.

◆ PCIC_INTR_CARDTYPE_MEM

#define PCIC_INTR_CARDTYPE_MEM   0x00

Definition at line 142 of file i82365reg.h.

◆ PCIC_INTR_ENABLE

#define PCIC_INTR_ENABLE   0x10

Definition at line 143 of file i82365reg.h.

◆ PCIC_INTR_IRQ10

#define PCIC_INTR_IRQ10   0x0A

Definition at line 156 of file i82365reg.h.

◆ PCIC_INTR_IRQ11

#define PCIC_INTR_IRQ11   0x0B

Definition at line 157 of file i82365reg.h.

◆ PCIC_INTR_IRQ12

#define PCIC_INTR_IRQ12   0x0C

Definition at line 158 of file i82365reg.h.

◆ PCIC_INTR_IRQ14

#define PCIC_INTR_IRQ14   0x0E

Definition at line 160 of file i82365reg.h.

◆ PCIC_INTR_IRQ15

#define PCIC_INTR_IRQ15   0x0F

Definition at line 161 of file i82365reg.h.

◆ PCIC_INTR_IRQ3

#define PCIC_INTR_IRQ3   0x03

Definition at line 149 of file i82365reg.h.

◆ PCIC_INTR_IRQ4

#define PCIC_INTR_IRQ4   0x04

Definition at line 150 of file i82365reg.h.

◆ PCIC_INTR_IRQ5

#define PCIC_INTR_IRQ5   0x05

Definition at line 151 of file i82365reg.h.

◆ PCIC_INTR_IRQ7

#define PCIC_INTR_IRQ7   0x07

Definition at line 153 of file i82365reg.h.

◆ PCIC_INTR_IRQ9

#define PCIC_INTR_IRQ9   0x09

Definition at line 155 of file i82365reg.h.

◆ PCIC_INTR_IRQ_MASK

#define PCIC_INTR_IRQ_MASK   0x0F

Definition at line 144 of file i82365reg.h.

◆ PCIC_INTR_IRQ_NONE

#define PCIC_INTR_IRQ_NONE   0x00

Definition at line 146 of file i82365reg.h.

◆ PCIC_INTR_IRQ_RESERVED1

#define PCIC_INTR_IRQ_RESERVED1   0x01

Definition at line 147 of file i82365reg.h.

◆ PCIC_INTR_IRQ_RESERVED13

#define PCIC_INTR_IRQ_RESERVED13   0x0D

Definition at line 159 of file i82365reg.h.

◆ PCIC_INTR_IRQ_RESERVED2

#define PCIC_INTR_IRQ_RESERVED2   0x02

Definition at line 148 of file i82365reg.h.

◆ PCIC_INTR_IRQ_RESERVED6

#define PCIC_INTR_IRQ_RESERVED6   0x06

Definition at line 152 of file i82365reg.h.

◆ PCIC_INTR_IRQ_RESERVED8

#define PCIC_INTR_IRQ_RESERVED8   0x08

Definition at line 154 of file i82365reg.h.

◆ PCIC_INTR_IRQ_SHIFT

#define PCIC_INTR_IRQ_SHIFT   0

Definition at line 145 of file i82365reg.h.

◆ PCIC_INTR_IRQ_VALIDMASK

#define PCIC_INTR_IRQ_VALIDMASK   0xDEB8 /* 1101 1110 1011 1000 */

Definition at line 163 of file i82365reg.h.

◆ PCIC_INTR_RESET

#define PCIC_INTR_RESET   0x40 /* active low (zero) */

Definition at line 139 of file i82365reg.h.

◆ PCIC_INTR_RI_ENABLE

#define PCIC_INTR_RI_ENABLE   0x80

Definition at line 138 of file i82365reg.h.

◆ PCIC_IO_WINS

#define PCIC_IO_WINS   2

Definition at line 200 of file i82365reg.h.

◆ PCIC_IOADDR0_START_LSB

#define PCIC_IOADDR0_START_LSB   0x08

Definition at line 220 of file i82365reg.h.

◆ PCIC_IOADDR0_START_MSB

#define PCIC_IOADDR0_START_MSB   0x09

Definition at line 221 of file i82365reg.h.

◆ PCIC_IOADDR0_STOP_LSB

#define PCIC_IOADDR0_STOP_LSB   0x0A

Definition at line 222 of file i82365reg.h.

◆ PCIC_IOADDR0_STOP_MSB

#define PCIC_IOADDR0_STOP_MSB   0x0B

Definition at line 223 of file i82365reg.h.

◆ PCIC_IOADDR1_START_LSB

#define PCIC_IOADDR1_START_LSB   0x0C

Definition at line 224 of file i82365reg.h.

◆ PCIC_IOADDR1_START_MSB

#define PCIC_IOADDR1_START_MSB   0x0D

Definition at line 225 of file i82365reg.h.

◆ PCIC_IOADDR1_STOP_LSB

#define PCIC_IOADDR1_STOP_LSB   0x0E

Definition at line 226 of file i82365reg.h.

◆ PCIC_IOADDR1_STOP_MSB

#define PCIC_IOADDR1_STOP_MSB   0x0F

Definition at line 227 of file i82365reg.h.

◆ PCIC_IOCTL

#define PCIC_IOCTL   0x07 /* RW */

Definition at line 202 of file i82365reg.h.

◆ PCIC_IOCTL_IO0_DATASIZE_16BIT

#define PCIC_IOCTL_IO0_DATASIZE_16BIT   0x01

Definition at line 217 of file i82365reg.h.

◆ PCIC_IOCTL_IO0_DATASIZE_8BIT

#define PCIC_IOCTL_IO0_DATASIZE_8BIT   0x00

Definition at line 218 of file i82365reg.h.

◆ PCIC_IOCTL_IO0_DATASIZE_MASK

#define PCIC_IOCTL_IO0_DATASIZE_MASK   0x01

Definition at line 216 of file i82365reg.h.

◆ PCIC_IOCTL_IO0_IOCS16SRC_CARD

#define PCIC_IOCTL_IO0_IOCS16SRC_CARD   0x02

Definition at line 214 of file i82365reg.h.

◆ PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE

#define PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE   0x00

Definition at line 215 of file i82365reg.h.

◆ PCIC_IOCTL_IO0_IOCS16SRC_MASK

#define PCIC_IOCTL_IO0_IOCS16SRC_MASK   0x02

Definition at line 213 of file i82365reg.h.

◆ PCIC_IOCTL_IO0_WAITSTATE

#define PCIC_IOCTL_IO0_WAITSTATE   0x08

Definition at line 211 of file i82365reg.h.

◆ PCIC_IOCTL_IO0_ZEROWAIT

#define PCIC_IOCTL_IO0_ZEROWAIT   0x04

Definition at line 212 of file i82365reg.h.

◆ PCIC_IOCTL_IO1_DATASIZE_16BIT

#define PCIC_IOCTL_IO1_DATASIZE_16BIT   0x10

Definition at line 209 of file i82365reg.h.

◆ PCIC_IOCTL_IO1_DATASIZE_8BIT

#define PCIC_IOCTL_IO1_DATASIZE_8BIT   0x00

Definition at line 210 of file i82365reg.h.

◆ PCIC_IOCTL_IO1_DATASIZE_MASK

#define PCIC_IOCTL_IO1_DATASIZE_MASK   0x10

Definition at line 208 of file i82365reg.h.

◆ PCIC_IOCTL_IO1_IOCS16SRC_CARD

#define PCIC_IOCTL_IO1_IOCS16SRC_CARD   0x20

Definition at line 206 of file i82365reg.h.

◆ PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE

#define PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE   0x00

Definition at line 207 of file i82365reg.h.

◆ PCIC_IOCTL_IO1_IOCS16SRC_MASK

#define PCIC_IOCTL_IO1_IOCS16SRC_MASK   0x20

Definition at line 205 of file i82365reg.h.

◆ PCIC_IOCTL_IO1_WAITSTATE

#define PCIC_IOCTL_IO1_WAITSTATE   0x80

Definition at line 203 of file i82365reg.h.

◆ PCIC_IOCTL_IO1_ZEROWAIT

#define PCIC_IOCTL_IO1_ZEROWAIT   0x40

Definition at line 204 of file i82365reg.h.

◆ PCIC_IOSIZE

#define PCIC_IOSIZE   2

Definition at line 42 of file i82365reg.h.

◆ PCIC_MEM_PAGESIZE

#define PCIC_MEM_PAGESIZE   (1<<PCIC_MEM_SHIFT)

Definition at line 240 of file i82365reg.h.

◆ PCIC_MEM_SHIFT

#define PCIC_MEM_SHIFT   12

Definition at line 239 of file i82365reg.h.

◆ PCIC_MEM_WINS

#define PCIC_MEM_WINS   5

Definition at line 237 of file i82365reg.h.

◆ PCIC_PWRCTL

#define PCIC_PWRCTL   0x02 /* RW */

Definition at line 90 of file i82365reg.h.

◆ PCIC_PWRCTL_AUTOSWITCH_ENABLE

#define PCIC_PWRCTL_AUTOSWITCH_ENABLE   0x20

Definition at line 93 of file i82365reg.h.

◆ PCIC_PWRCTL_DISABLE_RESETDRV

#define PCIC_PWRCTL_DISABLE_RESETDRV   0x40

Definition at line 92 of file i82365reg.h.

◆ PCIC_PWRCTL_OE

#define PCIC_PWRCTL_OE   0x80 /* output enable */

Definition at line 91 of file i82365reg.h.

◆ PCIC_PWRCTL_PWR_ENABLE

#define PCIC_PWRCTL_PWR_ENABLE   0x10

Definition at line 94 of file i82365reg.h.

◆ PCIC_PWRCTL_VPP1_12V

#define PCIC_PWRCTL_VPP1_12V   0x02

Definition at line 102 of file i82365reg.h.

◆ PCIC_PWRCTL_VPP1_MASK

#define PCIC_PWRCTL_VPP1_MASK   0x03

Definition at line 100 of file i82365reg.h.

◆ PCIC_PWRCTL_VPP1_OFF

#define PCIC_PWRCTL_VPP1_OFF   0x00

Definition at line 104 of file i82365reg.h.

◆ PCIC_PWRCTL_VPP1_RESERVED

#define PCIC_PWRCTL_VPP1_RESERVED   0x03

Definition at line 101 of file i82365reg.h.

◆ PCIC_PWRCTL_VPP1_VCC

#define PCIC_PWRCTL_VPP1_VCC   0x01

Definition at line 103 of file i82365reg.h.

◆ PCIC_PWRCTL_VPP2_12V

#define PCIC_PWRCTL_VPP2_12V   0x08

Definition at line 97 of file i82365reg.h.

◆ PCIC_PWRCTL_VPP2_MASK

#define PCIC_PWRCTL_VPP2_MASK   0x0C

Definition at line 95 of file i82365reg.h.

◆ PCIC_PWRCTL_VPP2_OFF

#define PCIC_PWRCTL_VPP2_OFF   0x00

Definition at line 99 of file i82365reg.h.

◆ PCIC_PWRCTL_VPP2_RESERVED

#define PCIC_PWRCTL_VPP2_RESERVED   0x0C

Definition at line 96 of file i82365reg.h.

◆ PCIC_PWRCTL_VPP2_VCC

#define PCIC_PWRCTL_VPP2_VCC   0x04

Definition at line 98 of file i82365reg.h.

◆ PCIC_REG_DATA

#define PCIC_REG_DATA   1

Definition at line 45 of file i82365reg.h.

◆ PCIC_REG_INDEX

#define PCIC_REG_INDEX   0

Definition at line 44 of file i82365reg.h.

◆ PCIC_RICOH_CHIP_ID_5C296

#define PCIC_RICOH_CHIP_ID_5C296   0x32

Definition at line 367 of file i82365reg.h.

◆ PCIC_RICOH_CHIP_ID_5C396

#define PCIC_RICOH_CHIP_ID_5C396   0xB2

Definition at line 368 of file i82365reg.h.

◆ PCIC_RICOH_MCR2_VCC_DIRECT

#define PCIC_RICOH_MCR2_VCC_DIRECT   0x08

Definition at line 370 of file i82365reg.h.

◆ PCIC_RICOH_MCR2_VCC_SEL_3V

#define PCIC_RICOH_MCR2_VCC_SEL_3V   0x01

Definition at line 372 of file i82365reg.h.

◆ PCIC_RICOH_MCR2_VCC_SEL_5V

#define PCIC_RICOH_MCR2_VCC_SEL_5V   0x00

Definition at line 373 of file i82365reg.h.

◆ PCIC_RICOH_MCR2_VCC_SEL_MASK

#define PCIC_RICOH_MCR2_VCC_SEL_MASK   0x01

Definition at line 371 of file i82365reg.h.

◆ PCIC_RICOH_REG_CHIP_ID

#define PCIC_RICOH_REG_CHIP_ID   0x3A

Definition at line 366 of file i82365reg.h.

◆ PCIC_RICOH_REG_MCR2

#define PCIC_RICOH_REG_MCR2   0x2F

Definition at line 369 of file i82365reg.h.

◆ PCIC_SOCKET_OFFSET

#define PCIC_SOCKET_OFFSET   0x40

Definition at line 55 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR0_START_LSB

#define PCIC_SYSMEM_ADDR0_START_LSB   0x10

Definition at line 270 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR0_START_MSB

#define PCIC_SYSMEM_ADDR0_START_MSB   0x11

Definition at line 271 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR0_STOP_LSB

#define PCIC_SYSMEM_ADDR0_STOP_LSB   0x12

Definition at line 272 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR0_STOP_MSB

#define PCIC_SYSMEM_ADDR0_STOP_MSB   0x13

Definition at line 273 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR1_START_LSB

#define PCIC_SYSMEM_ADDR1_START_LSB   0x18

Definition at line 280 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR1_START_MSB

#define PCIC_SYSMEM_ADDR1_START_MSB   0x19

Definition at line 281 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR1_STOP_LSB

#define PCIC_SYSMEM_ADDR1_STOP_LSB   0x1A

Definition at line 282 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR1_STOP_MSB

#define PCIC_SYSMEM_ADDR1_STOP_MSB   0x1B

Definition at line 283 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR2_START_LSB

#define PCIC_SYSMEM_ADDR2_START_LSB   0x20

Definition at line 288 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR2_START_MSB

#define PCIC_SYSMEM_ADDR2_START_MSB   0x21

Definition at line 289 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR2_STOP_LSB

#define PCIC_SYSMEM_ADDR2_STOP_LSB   0x22

Definition at line 290 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR2_STOP_MSB

#define PCIC_SYSMEM_ADDR2_STOP_MSB   0x23

Definition at line 291 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR3_START_LSB

#define PCIC_SYSMEM_ADDR3_START_LSB   0x28

Definition at line 299 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR3_START_MSB

#define PCIC_SYSMEM_ADDR3_START_MSB   0x29

Definition at line 300 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR3_STOP_LSB

#define PCIC_SYSMEM_ADDR3_STOP_LSB   0x2A

Definition at line 301 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR3_STOP_MSB

#define PCIC_SYSMEM_ADDR3_STOP_MSB   0x2B

Definition at line 302 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR4_START_LSB

#define PCIC_SYSMEM_ADDR4_START_LSB   0x30

Definition at line 310 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR4_START_MSB

#define PCIC_SYSMEM_ADDR4_START_MSB   0x31

Definition at line 311 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR4_STOP_LSB

#define PCIC_SYSMEM_ADDR4_STOP_LSB   0x32

Definition at line 312 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDR4_STOP_MSB

#define PCIC_SYSMEM_ADDR4_STOP_MSB   0x33

Definition at line 313 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDRX_SHIFT

#define PCIC_SYSMEM_ADDRX_SHIFT   PCIC_MEM_SHIFT

Definition at line 242 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK

#define PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK   0x0F

Definition at line 248 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT

#define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT   0x80

Definition at line 244 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT

#define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT   0x00

Definition at line 245 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK

#define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK   0x80

Definition at line 243 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK

#define PCIC_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK   0x30

Definition at line 247 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDRX_START_MSB_ZEROWAIT

#define PCIC_SYSMEM_ADDRX_START_MSB_ZEROWAIT   0x40

Definition at line 246 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK

#define PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK   0x0F

Definition at line 255 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT0

#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT0   0x00

Definition at line 251 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT1

#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT1   0x40

Definition at line 252 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2

#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2   0x80

Definition at line 253 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT3

#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT3   0xC0

Definition at line 254 of file i82365reg.h.

◆ PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK

#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK   0xC0

Definition at line 250 of file i82365reg.h.


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