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#define | SCC_CHANNEL_A 1 |
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#define | SCC_CHANNEL_B 0 |
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#define | SCC_INIT_REG(scc, chan) |
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#define | SCC_READ_REG(scc, chan, reg, val) |
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#define | SCC_READ_REG_ZERO(scc, chan, val) |
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#define | SCC_WRITE_REG(scc, chan, reg, val) |
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#define | SCC_WRITE_REG_ZERO(scc, chan, val) |
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#define | SCC_READ_DATA(scc, chan, val) |
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#define | SCC_WRITE_DATA(scc, chan, val) |
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#define | SCC_RR0 0 /* status register */ |
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#define | SCC_RR1 1 /* special receive conditions */ |
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#define | SCC_RR2 2 /* (modified) interrupt vector */ |
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#define | SCC_RR3 3 /* interrupts pending (cha A only) */ |
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#define | SCC_RR8 8 /* recv buffer (alias for data) */ |
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#define | SCC_RR10 10 /* sdlc status */ |
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#define | SCC_RR12 12 /* BRG constant, low part */ |
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#define | SCC_RR13 13 /* BRG constant, high part */ |
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#define | SCC_RR15 15 /* interrupts currently enabled */ |
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#define | SCC_WR0 0 /* reg select, and commands */ |
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#define | SCC_WR1 1 /* interrupt and DMA enables */ |
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#define | SCC_WR2 2 /* interrupt vector */ |
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#define | SCC_WR3 3 /* receiver params and enables */ |
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#define | SCC_WR4 4 /* clock/char/parity params */ |
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#define | SCC_WR5 5 /* xmit params and enables */ |
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#define | SCC_WR6 6 /* synchr SYNCH/address */ |
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#define | SCC_WR7 7 /* synchr SYNCH/flag */ |
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#define | SCC_WR8 8 /* xmit buffer (alias for data) */ |
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#define | SCC_WR9 9 /* vectoring and resets */ |
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#define | SCC_WR10 10 /* synchr params */ |
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#define | SCC_WR11 11 /* clocking definitions */ |
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#define | SCC_WR12 12 /* BRG constant, low part */ |
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#define | SCC_WR13 13 /* BRG constant, high part */ |
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#define | SCC_WR14 14 /* BRG enables and commands */ |
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#define | SCC_WR15 15 /* interrupt enables */ |
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#define | SCC_RR0_BREAK 0x80 /* break detected (rings twice), or */ |
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#define | SCC_RR0_ABORT 0x80 /* abort (synchr) */ |
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#define | SCC_RR0_TX_UNDERRUN 0x40 /* xmit buffer empty/end of message */ |
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#define | SCC_RR0_CTS |
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#define | SCC_RR0_SYNCH 0x10 /* SYNCH found/still hunting */ |
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#define | SCC_RR0_DCD 0x08 /* carrier-detect (same as CTS) */ |
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#define | SCC_RR0_TX_EMPTY 0x04 /* xmit buffer empty */ |
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#define | SCC_RR0_ZERO_COUNT 0x02 /* ? */ |
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#define | SCC_RR0_RX_AVAIL 0x01 /* recv fifo not empty */ |
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#define | SCC_RR1_EOF 0x80 /* end-of-frame, SDLC mode */ |
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#define | SCC_RR1_CRC_ERR 0x40 /* incorrect CRC or.. */ |
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#define | SCC_RR1_FRAME_ERR 0x40 /* ..bad frame */ |
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#define | SCC_RR1_RX_OVERRUN 0x20 /* rcv fifo overflow */ |
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#define | SCC_RR1_PARITY_ERR 0x10 /* incorrect parity in data */ |
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#define | SCC_RR1_RESIDUE0 0x08 |
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#define | SCC_RR1_RESIDUE1 0x04 |
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#define | SCC_RR1_RESIDUE2 0x02 |
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#define | SCC_RR1_ALL_SENT 0x01 |
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#define | SCC_RR2_STATUS(val) ((val)&0xf) |
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#define | SCC_RR2_B_XMIT_DONE 0x0 |
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#define | SCC_RR2_B_EXT_STATUS 0x2 |
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#define | SCC_RR2_B_RECV_DONE 0x4 |
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#define | SCC_RR2_B_RECV_SPECIAL 0x6 |
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#define | SCC_RR2_A_XMIT_DONE 0x8 |
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#define | SCC_RR2_A_EXT_STATUS 0xa |
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#define | SCC_RR2_A_RECV_DONE 0xc |
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#define | SCC_RR2_A_RECV_SPECIAL 0xe |
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#define | SCC_RR3_zero 0xc0 |
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#define | SCC_RR3_RX_IP_A 0x20 |
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#define | SCC_RR3_TX_IP_A 0x10 |
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#define | SCC_RR3_EXT_IP_A 0x08 |
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#define | SCC_RR3_RX_IP_B 0x04 |
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#define | SCC_RR3_TX_IP_B 0x02 |
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#define | SCC_RR3_EXT_IP_B 0x01 |
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#define | SCC_RECV_BUFFER SCC_RR8 |
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#define | SCC_RECV_FIFO_DEEP 3 |
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#define | SCC_RR10_1CLKS 0x80 |
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#define | SCC_RR10_2CLKS 0x40 |
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#define | SCC_RR10_zero 0x2d |
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#define | SCC_RR10_LOOP_SND 0x10 |
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#define | SCC_RR10_ON_LOOP 0x02 |
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#define | SCC_GET_TIMING_BASE(scc, chan, val) |
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#define | SCC_RR15_BREAK_IE 0x80 |
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#define | SCC_RR15_TX_UNDERRUN_IE 0x40 |
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#define | SCC_RR15_CTS_IE 0x20 |
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#define | SCC_RR15_SYNCH_IE 0x10 |
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#define | SCC_RR15_DCD_IE 0x08 |
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#define | SCC_RR15_zero 0x05 |
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#define | SCC_RR15_ZERO_COUNT_IE 0x02 |
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#define | SCC_RESET_TXURUN_LATCH 0xc0 |
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#define | SCC_RESET_TX_CRC 0x80 |
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#define | SCC_RESET_RX_CRC 0x40 |
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#define | SCC_RESET_HIGHEST_IUS 0x38 /* channel A only */ |
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#define | SCC_RESET_ERROR 0x30 |
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#define | SCC_RESET_TX_IP 0x28 |
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#define | SCC_IE_NEXT_CHAR 0x20 |
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#define | SCC_SEND_SDLC_ABORT 0x18 |
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#define | SCC_RESET_EXT_IP 0x10 |
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#define | SCC_WR1_DMA_ENABLE 0x80 /* dma control */ |
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#define | SCC_WR1_DMA_MODE 0x40 /* drive ~req for DMA controller */ |
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#define | SCC_WR1_DMA_RECV_DATA 0x20 /* from wire to host memory */ |
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#define | SCC_WR1_RXI_SPECIAL_O 0x18 /* on special only */ |
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#define | SCC_WR1_RXI_ALL_CHAR 0x10 /* on each char, or special */ |
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#define | SCC_WR1_RXI_FIRST_CHAR 0x08 /* on first char, or special */ |
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#define | SCC_WR1_RXI_DISABLE 0x00 /* never on recv */ |
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#define | SCC_WR1_PARITY_IE 0x04 /* on parity errors */ |
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#define | SCC_WR1_TX_IE 0x02 |
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#define | SCC_WR1_EXT_IE 0x01 |
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#define | SCC_WR3_RX_8_BITS 0xc0 |
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#define | SCC_WR3_RX_6_BITS 0x80 |
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#define | SCC_WR3_RX_7_BITS 0x40 |
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#define | SCC_WR3_RX_5_BITS 0x00 |
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#define | SCC_WR3_AUTO_ENABLE 0x20 |
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#define | SCC_WR3_HUNT_MODE 0x10 |
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#define | SCC_WR3_RX_CRC_ENABLE 0x08 |
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#define | SCC_WR3_SDLC_SRCH 0x04 |
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#define | SCC_WR3_INHIBIT_SYNCH 0x02 |
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#define | SCC_WR3_RX_ENABLE 0x01 |
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#define | SCC_WR4_CLK_x64 0xc0 /* clock divide factor */ |
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#define | SCC_WR4_CLK_x32 0x80 |
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#define | SCC_WR4_CLK_x16 0x40 |
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#define | SCC_WR4_CLK_x1 0x00 |
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#define | SCC_WR4_EXT_SYNCH_MODE 0x30 /* synch modes */ |
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#define | SCC_WR4_SDLC_MODE 0x20 |
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#define | SCC_WR4_16BIT_SYNCH 0x10 |
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#define | SCC_WR4_8BIT_SYNCH 0x00 |
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#define | SCC_WR4_2_STOP 0x0c /* asynch modes */ |
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#define | SCC_WR4_1_5_STOP 0x08 |
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#define | SCC_WR4_1_STOP 0x04 |
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#define | SCC_WR4_SYNCH_MODE 0x00 |
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#define | SCC_WR4_EVEN_PARITY 0x02 |
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#define | SCC_WR4_PARITY_ENABLE 0x01 |
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#define | SCC_WR5_DTR 0x80 /* drive DTR pin */ |
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#define | SCC_WR5_TX_8_BITS 0x60 |
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#define | SCC_WR5_TX_6_BITS 0x40 |
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#define | SCC_WR5_TX_7_BITS 0x20 |
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#define | SCC_WR5_TX_5_BITS 0x00 |
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#define | SCC_WR5_SEND_BREAK 0x10 |
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#define | SCC_WR5_TX_ENABLE 0x08 |
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#define | SCC_WR5_CRC_16 0x04 /* CRC if non zero, .. */ |
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#define | SCC_WR5_SDLC 0x00 /* ..SDLC otherwise */ |
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#define | SCC_WR5_RTS 0x02 /* drive RTS pin */ |
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#define | SCC_WR5_TX_CRC_ENABLE 0x01 |
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#define | SCC_WR6_BISYNCH_12 0x0f |
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#define | SCC_WR6_SDLC_RANGE_MASK 0x0f |
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#define | SCC_WR7_SDLC_FLAG 0x7e |
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#define | SCC_XMT_BUFFER SCC_WR8 |
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#define | SCC_WR9_HW_RESET 0xc0 /* force hardware reset */ |
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#define | SCC_WR9_RESET_CHA_A 0x80 |
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#define | SCC_WR9_RESET_CHA_B 0x40 |
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#define | SCC_WR9_NON_VECTORED 0x20 /* mbz for Zilog chip */ |
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#define | SCC_WR9_STATUS_HIGH 0x10 |
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#define | SCC_WR9_MASTER_IE 0x08 |
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#define | SCC_WR9_DLC 0x04 /* disable-lower-chain */ |
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#define | SCC_WR9_NV 0x02 /* no vector */ |
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#define | SCC_WR9_VIS 0x01 /* vector-includes-status */ |
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#define | SCC_WR10_CRC_PRESET 0x80 |
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#define | SCC_WR10_FM0 0x60 |
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#define | SCC_WR10_FM1 0x40 |
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#define | SCC_WR10_NRZI 0x20 |
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#define | SCC_WR10_NRZ 0x00 |
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#define | SCC_WR10_ACTIVE_ON_POLL 0x10 |
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#define | SCC_WR10_MARK_IDLE 0x08 /* flag if zero */ |
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#define | SCC_WR10_ABORT_ON_URUN 0x04 /* flag if zero */ |
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#define | SCC_WR10_LOOP_MODE 0x02 |
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#define | SCC_WR10_6BIT_SYNCH 0x01 |
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#define | SCC_WR10_8BIT_SYNCH 0x00 |
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#define | SCC_WR11_RTxC_XTAL 0x80 /* RTxC pin is input (ext oscill) */ |
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#define | SCC_WR11_RCLK_DPLL 0x60 /* clock received data on dpll */ |
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#define | SCC_WR11_RCLK_BAUDR 0x40 /* .. on BRG */ |
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#define | SCC_WR11_RCLK_TRc_PIN 0x20 /* .. on TRxC pin */ |
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#define | SCC_WR11_RCLK_RTc_PIN 0x00 /* .. on RTxC pin */ |
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#define | SCC_WR11_XTLK_DPLL 0x18 |
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#define | SCC_WR11_XTLK_BAUDR 0x10 |
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#define | SCC_WR11_XTLK_TRc_PIN 0x08 |
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#define | SCC_WR11_XTLK_RTc_PIN 0x00 |
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#define | SCC_WR11_TRc_OUT 0x04 /* drive TRxC pin as output from..*/ |
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#define | SCC_WR11_TRcOUT_DPLL 0x03 /* .. the dpll */ |
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#define | SCC_WR11_TRcOUT_BAUDR 0x02 /* .. the BRG */ |
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#define | SCC_WR11_TRcOUT_XMTCLK 0x01 /* .. the xmit clock */ |
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#define | SCC_WR11_TRcOUT_XTAL 0x00 /* .. the external oscillator */ |
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#define | SCC_SET_TIMING_BASE(scc, chan, val) |
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#define | SCC_WR14_NRZI_MODE 0xe0 /* synch modulations */ |
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#define | SCC_WR14_FM_MODE 0xc0 |
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#define | SCC_WR14_RTc_SOURCE 0xa0 /* clock is from pin .. */ |
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#define | SCC_WR14_BAUDR_SOURCE 0x80 /* .. or internal BRG */ |
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#define | SCC_WR14_DISABLE_DPLL 0x60 |
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#define | SCC_WR14_RESET_CLKMISS 0x40 |
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#define | SCC_WR14_SEARCH_MODE 0x20 |
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#define | SCC_WR14_LOCAL_LOOPB 0x10 |
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#define | SCC_WR14_AUTO_ECHO 0x08 |
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#define | SCC_WR14_DTR_REQUEST 0x04 |
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#define | SCC_WR14_BAUDR_SRC 0x02 |
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#define | SCC_WR14_BAUDR_ENABLE 0x01 |
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#define | SCC_WR15_BREAK_IE 0x80 |
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#define | SCC_WR15_TX_UNDERRUN_IE 0x40 |
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#define | SCC_WR15_CTS_IE 0x20 |
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#define | SCC_WR15_SYNCHUNT_IE 0x10 |
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#define | SCC_WR15_DCD_IE 0x08 |
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#define | SCC_WR15_zero 0x05 |
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#define | SCC_WR15_ZERO_COUNT_IE 0x02 |
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#define | DML_DSR 0000400 /* data set ready, not a real DM bit */ |
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#define | DML_RNG 0000200 /* ring */ |
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#define | DML_CAR 0000100 /* carrier detect */ |
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#define | DML_CTS 0000040 /* clear to send */ |
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#define | DML_SR 0000020 /* secondary receive */ |
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#define | DML_ST 0000010 /* secondary transmit */ |
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#define | DML_RTS 0000004 /* request to send */ |
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#define | DML_DTR 0000002 /* data terminal ready */ |
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#define | DML_LE 0000001 /* line enable */ |
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#define | SCCCOMM2_PORT 0x0 |
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#define | SCCMOUSE_PORT 0x1 |
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#define | SCCCOMM3_PORT 0x2 |
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#define | SCCKBD_PORT 0x3 |
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