pcireg.h Source File

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pcireg.h
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1 /* gxemul: $Id: pcireg.h,v 1.6 2005-11-17 13:53:43 debug Exp $ */
2 /* $NetBSD: pcireg.h,v 1.37 2002/03/22 20:03:20 drochner Exp $ */
3 
4 #ifndef _DEV_PCI_PCIREG_H_
5 #define _DEV_PCI_PCIREG_H_
6 
7 #ifdef __attribute__
8 #undef __attribute__
9 #endif
10 
11 #ifdef __noreturn__
12 #undef __noreturn__
13 #endif
14 
15 #define __attribute__(x) /* */
16 #define __noreturn__ /* */
17 
18 /*
19  * Copyright (c) 1995, 1996, 1999, 2000
20  * Christopher G. Demetriou. All rights reserved.
21  * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
22  *
23  * Redistribution and use in source and binary forms, with or without
24  * modification, are permitted provided that the following conditions
25  * are met:
26  * 1. Redistributions of source code must retain the above copyright
27  * notice, this list of conditions and the following disclaimer.
28  * 2. Redistributions in binary form must reproduce the above copyright
29  * notice, this list of conditions and the following disclaimer in the
30  * documentation and/or other materials provided with the distribution.
31  * 3. All advertising materials mentioning features or use of this software
32  * must display the following acknowledgement:
33  * This product includes software developed by Charles M. Hannum.
34  * 4. The name of the author may not be used to endorse or promote products
35  * derived from this software without specific prior written permission.
36  *
37  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
38  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
39  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
40  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
41  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
42  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
46  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47  */
48 
49 /*
50  * Standardized PCI configuration information
51  *
52  * XXX This is not complete.
53  */
54 
55 /*
56  * Device identification register; contains a vendor ID and a device ID.
57  */
58 #define PCI_ID_REG 0x00
59 
60 typedef u_int16_t pci_vendor_id_t;
61 typedef u_int16_t pci_product_id_t;
62 
63 #define PCI_VENDOR_SHIFT 0
64 #define PCI_VENDOR_MASK 0xffff
65 #define PCI_VENDOR(id) \
66  (((id) >> PCI_VENDOR_SHIFT) & PCI_VENDOR_MASK)
67 
68 #define PCI_PRODUCT_SHIFT 16
69 #define PCI_PRODUCT_MASK 0xffff
70 #define PCI_PRODUCT(id) \
71  (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
72 
73 #define PCI_ID_CODE(vid,pid) \
74  ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) | \
75  (((uint32_t)((pid) & PCI_PRODUCT_MASK)) << PCI_PRODUCT_SHIFT))
76 
77 /*
78  * Command and status register.
79  */
80 #define PCI_COMMAND_STATUS_REG 0x04
81 #define PCI_COMMAND_SHIFT 0
82 #define PCI_COMMAND_MASK 0xffff
83 #define PCI_STATUS_SHIFT 16
84 #define PCI_STATUS_MASK 0xffff
85 
86 #define PCI_COMMAND_STATUS_CODE(cmd,stat) \
87  ((((cmd) & PCI_COMMAND_MASK) >> PCI_COMMAND_SHIFT) | \
88  (((stat) & PCI_STATUS_MASK) >> PCI_STATUS_SHIFT))
89 
90 #define PCI_COMMAND_IO_ENABLE 0x00000001
91 #define PCI_COMMAND_MEM_ENABLE 0x00000002
92 #define PCI_COMMAND_MASTER_ENABLE 0x00000004
93 #define PCI_COMMAND_SPECIAL_ENABLE 0x00000008
94 #define PCI_COMMAND_INVALIDATE_ENABLE 0x00000010
95 #define PCI_COMMAND_PALETTE_ENABLE 0x00000020
96 #define PCI_COMMAND_PARITY_ENABLE 0x00000040
97 #define PCI_COMMAND_STEPPING_ENABLE 0x00000080
98 #define PCI_COMMAND_SERR_ENABLE 0x00000100
99 #define PCI_COMMAND_BACKTOBACK_ENABLE 0x00000200
100 
101 #define PCI_STATUS_CAPLIST_SUPPORT 0x00100000
102 #define PCI_STATUS_66MHZ_SUPPORT 0x00200000
103 #define PCI_STATUS_UDF_SUPPORT 0x00400000
104 #define PCI_STATUS_BACKTOBACK_SUPPORT 0x00800000
105 #define PCI_STATUS_PARITY_ERROR 0x01000000
106 #define PCI_STATUS_DEVSEL_FAST 0x00000000
107 #define PCI_STATUS_DEVSEL_MEDIUM 0x02000000
108 #define PCI_STATUS_DEVSEL_SLOW 0x04000000
109 #define PCI_STATUS_DEVSEL_MASK 0x06000000
110 #define PCI_STATUS_TARGET_TARGET_ABORT 0x08000000
111 #define PCI_STATUS_MASTER_TARGET_ABORT 0x10000000
112 #define PCI_STATUS_MASTER_ABORT 0x20000000
113 #define PCI_STATUS_SPECIAL_ERROR 0x40000000
114 #define PCI_STATUS_PARITY_DETECT 0x80000000
115 
116 /*
117  * PCI Class and Revision Register; defines type and revision of device.
118  */
119 #define PCI_CLASS_REG 0x08
120 
121 typedef u_int8_t pci_class_t;
122 typedef u_int8_t pci_subclass_t;
123 typedef u_int8_t pci_interface_t;
124 typedef u_int8_t pci_revision_t;
125 
126 #define PCI_CLASS_SHIFT 24
127 #define PCI_CLASS_MASK 0xff
128 #define PCI_CLASS(cr) \
129  (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
130 
131 #define PCI_SUBCLASS_SHIFT 16
132 #define PCI_SUBCLASS_MASK 0xff
133 #define PCI_SUBCLASS(cr) \
134  (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
135 
136 #define PCI_INTERFACE_SHIFT 8
137 #define PCI_INTERFACE_MASK 0xff
138 #define PCI_INTERFACE(cr) \
139  (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
140 
141 #define PCI_REVISION_SHIFT 0
142 #define PCI_REVISION_MASK 0xff
143 #define PCI_REVISION(cr) \
144  (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
145 
146 #define PCI_CLASS_CODE(mainclass, subclass, interface) \
147  ((((mainclass) & PCI_CLASS_MASK) << PCI_CLASS_SHIFT) | \
148  (((subclass) & PCI_SUBCLASS_MASK) << PCI_SUBCLASS_SHIFT) | \
149  (((interface) & PCI_INTERFACE_MASK) << PCI_INTERFACE_SHIFT))
150 
151 /* base classes */
152 #define PCI_CLASS_PREHISTORIC 0x00
153 #define PCI_CLASS_MASS_STORAGE 0x01
154 #define PCI_CLASS_NETWORK 0x02
155 #define PCI_CLASS_DISPLAY 0x03
156 #define PCI_CLASS_MULTIMEDIA 0x04
157 #define PCI_CLASS_MEMORY 0x05
158 #define PCI_CLASS_BRIDGE 0x06
159 #define PCI_CLASS_COMMUNICATIONS 0x07
160 #define PCI_CLASS_SYSTEM 0x08
161 #define PCI_CLASS_INPUT 0x09
162 #define PCI_CLASS_DOCK 0x0a
163 #define PCI_CLASS_PROCESSOR 0x0b
164 #define PCI_CLASS_SERIALBUS 0x0c
165 #define PCI_CLASS_WIRELESS 0x0d
166 #define PCI_CLASS_I2O 0x0e
167 #define PCI_CLASS_SATCOM 0x0f
168 #define PCI_CLASS_CRYPTO 0x10
169 #define PCI_CLASS_DASP 0x11
170 #define PCI_CLASS_UNDEFINED 0xff
171 
172 /* 0x00 prehistoric subclasses */
173 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00
174 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
175 
176 /* 0x01 mass storage subclasses */
177 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00
178 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01
179 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
180 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
181 #define PCI_SUBCLASS_MASS_STORAGE_RAID 0x04
182 #define PCI_SUBCLASS_MASS_STORAGE_ATA 0x05
183 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
184 
185 /* 0x02 network subclasses */
186 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
187 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01
188 #define PCI_SUBCLASS_NETWORK_FDDI 0x02
189 #define PCI_SUBCLASS_NETWORK_ATM 0x03
190 #define PCI_SUBCLASS_NETWORK_ISDN 0x04
191 #define PCI_SUBCLASS_NETWORK_WORLDFIP 0x05
192 #define PCI_SUBCLASS_NETWORK_PCIMGMULTICOMP 0x06
193 #define PCI_SUBCLASS_NETWORK_MISC 0x80
194 
195 /* 0x03 display subclasses */
196 #define PCI_SUBCLASS_DISPLAY_VGA 0x00
197 #define PCI_SUBCLASS_DISPLAY_XGA 0x01
198 #define PCI_SUBCLASS_DISPLAY_3D 0x02
199 #define PCI_SUBCLASS_DISPLAY_MISC 0x80
200 
201 /* 0x04 multimedia subclasses */
202 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00
203 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
204 #define PCI_SUBCLASS_MULTIMEDIA_TELEPHONY 0x02
205 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80
206 
207 /* 0x05 memory subclasses */
208 #define PCI_SUBCLASS_MEMORY_RAM 0x00
209 #define PCI_SUBCLASS_MEMORY_FLASH 0x01
210 #define PCI_SUBCLASS_MEMORY_MISC 0x80
211 
212 /* 0x06 bridge subclasses */
213 #define PCI_SUBCLASS_BRIDGE_HOST 0x00
214 #define PCI_SUBCLASS_BRIDGE_ISA 0x01
215 #define PCI_SUBCLASS_BRIDGE_EISA 0x02
216 #define PCI_SUBCLASS_BRIDGE_MC 0x03 /* XXX _MCA? */
217 #define PCI_SUBCLASS_BRIDGE_PCI 0x04
218 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05
219 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
220 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
221 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08
222 #define PCI_SUBCLASS_BRIDGE_STPCI 0x09
223 #define PCI_SUBCLASS_BRIDGE_INFINIBAND 0x0a
224 #define PCI_SUBCLASS_BRIDGE_MISC 0x80
225 
226 /* 0x07 communications subclasses */
227 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
228 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01
229 #define PCI_SUBCLASS_COMMUNICATIONS_MPSERIAL 0x02
230 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03
231 #define PCI_SUBCLASS_COMMUNICATIONS_GPIB 0x04
232 #define PCI_SUBCLASS_COMMUNICATIONS_SMARTCARD 0x05
233 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80
234 
235 /* 0x08 system subclasses */
236 #define PCI_SUBCLASS_SYSTEM_PIC 0x00
237 #define PCI_SUBCLASS_SYSTEM_DMA 0x01
238 #define PCI_SUBCLASS_SYSTEM_TIMER 0x02
239 #define PCI_SUBCLASS_SYSTEM_RTC 0x03
240 #define PCI_SUBCLASS_SYSTEM_PCIHOTPLUG 0x04
241 #define PCI_SUBCLASS_SYSTEM_MISC 0x80
242 
243 /* 0x09 input subclasses */
244 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
245 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01
246 #define PCI_SUBCLASS_INPUT_MOUSE 0x02
247 #define PCI_SUBCLASS_INPUT_SCANNER 0x03
248 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04
249 #define PCI_SUBCLASS_INPUT_MISC 0x80
250 
251 /* 0x0a dock subclasses */
252 #define PCI_SUBCLASS_DOCK_GENERIC 0x00
253 #define PCI_SUBCLASS_DOCK_MISC 0x80
254 
255 /* 0x0b processor subclasses */
256 #define PCI_SUBCLASS_PROCESSOR_386 0x00
257 #define PCI_SUBCLASS_PROCESSOR_486 0x01
258 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02
259 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10
260 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
261 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30
262 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
263 
264 /* 0x0c serial bus subclasses */
265 #define PCI_SUBCLASS_SERIALBUS_FIREWIRE 0x00
266 #define PCI_SUBCLASS_SERIALBUS_ACCESS 0x01
267 #define PCI_SUBCLASS_SERIALBUS_SSA 0x02
268 #define PCI_SUBCLASS_SERIALBUS_USB 0x03
269 #define PCI_SUBCLASS_SERIALBUS_FIBER 0x04 /* XXX _FIBRECHANNEL */
270 #define PCI_SUBCLASS_SERIALBUS_SMBUS 0x05
271 #define PCI_SUBCLASS_SERIALBUS_INFINIBAND 0x06
272 #define PCI_SUBCLASS_SERIALBUS_IPMI 0x07
273 #define PCI_SUBCLASS_SERIALBUS_SERCOS 0x08
274 #define PCI_SUBCLASS_SERIALBUS_CANBUS 0x09
275 
276 /* 0x0d wireless subclasses */
277 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00
278 #define PCI_SUBCLASS_WIRELESS_CONSUMERIR 0x01
279 #define PCI_SUBCLASS_WIRELESS_RF 0x10
280 #define PCI_SUBCLASS_WIRELESS_BLUETOOTH 0x11
281 #define PCI_SUBCLASS_WIRELESS_BROADBAND 0x12
282 #define PCI_SUBCLASS_WIRELESS_MISC 0x80
283 
284 /* 0x0e I2O (Intelligent I/O) subclasses */
285 #define PCI_SUBCLASS_I2O_STANDARD 0x00
286 
287 /* 0x0f satellite communication subclasses */
288 /* PCI_SUBCLASS_SATCOM_??? 0x00 / * XXX ??? */
289 #define PCI_SUBCLASS_SATCOM_TV 0x01
290 #define PCI_SUBCLASS_SATCOM_AUDIO 0x02
291 #define PCI_SUBCLASS_SATCOM_VOICE 0x03
292 #define PCI_SUBCLASS_SATCOM_DATA 0x04
293 
294 /* 0x10 encryption/decryption subclasses */
295 #define PCI_SUBCLASS_CRYPTO_NETCOMP 0x00
296 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10
297 #define PCI_SUBCLASS_CRYPTO_MISC 0x80
298 
299 /* 0x11 data acquisition and signal processing subclasses */
300 #define PCI_SUBCLASS_DASP_DPIO 0x00
301 #define PCI_SUBCLASS_DASP_TIMEFREQ 0x01
302 #define PCI_SUBCLASS_DASP_SYNC 0x10
303 #define PCI_SUBCLASS_DASP_MGMT 0x20
304 #define PCI_SUBCLASS_DASP_MISC 0x80
305 
306 /*
307  * PCI BIST/Header Type/Latency Timer/Cache Line Size Register.
308  */
309 #define PCI_BHLC_REG 0x0c
310 
311 #define PCI_BIST_SHIFT 24
312 #define PCI_BIST_MASK 0xff
313 #define PCI_BIST(bhlcr) \
314  (((bhlcr) >> PCI_BIST_SHIFT) & PCI_BIST_MASK)
315 
316 #define PCI_HDRTYPE_SHIFT 16
317 #define PCI_HDRTYPE_MASK 0xff
318 #define PCI_HDRTYPE(bhlcr) \
319  (((bhlcr) >> PCI_HDRTYPE_SHIFT) & PCI_HDRTYPE_MASK)
320 
321 #define PCI_HDRTYPE_TYPE(bhlcr) \
322  (PCI_HDRTYPE(bhlcr) & 0x7f)
323 #define PCI_HDRTYPE_MULTIFN(bhlcr) \
324  ((PCI_HDRTYPE(bhlcr) & 0x80) != 0)
325 
326 #define PCI_LATTIMER_SHIFT 8
327 #define PCI_LATTIMER_MASK 0xff
328 #define PCI_LATTIMER(bhlcr) \
329  (((bhlcr) >> PCI_LATTIMER_SHIFT) & PCI_LATTIMER_MASK)
330 
331 #define PCI_CACHELINE_SHIFT 0
332 #define PCI_CACHELINE_MASK 0xff
333 #define PCI_CACHELINE(bhlcr) \
334  (((bhlcr) >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK)
335 
336 #define PCI_BHLC_CODE(bist,type,multi,latency,cacheline) \
337  ((((bist) & PCI_BIST_MASK) << PCI_BIST_SHIFT) | \
338  (((type) & PCI_HDRTYPE_MASK) << PCI_HDRTYPE_SHIFT) | \
339  (((multi)?0x80:0) << PCI_HDRTYPE_SHIFT) | \
340  (((latency) & PCI_LATTIMER_MASK) << PCI_LATTIMER_SHIFT) | \
341  (((cacheline) & PCI_CACHELINE_MASK) << PCI_CACHELINE_SHIFT))
342 
343 /*
344  * Mapping registers
345  */
346 #define PCI_MAPREG_START 0x10
347 #define PCI_MAPREG_END 0x28
348 #define PCI_MAPREG_ROM 0x30
349 #define PCI_MAPREG_PPB_END 0x18
350 #define PCI_MAPREG_PCB_END 0x14
351 
352 #define PCI_MAPREG_TYPE(mr) \
353  ((mr) & PCI_MAPREG_TYPE_MASK)
354 #define PCI_MAPREG_TYPE_MASK 0x00000001
355 
356 #define PCI_MAPREG_TYPE_MEM 0x00000000
357 #define PCI_MAPREG_TYPE_IO 0x00000001
358 #define PCI_MAPREG_ROM_ENABLE 0x00000001
359 
360 #define PCI_MAPREG_MEM_TYPE(mr) \
361  ((mr) & PCI_MAPREG_MEM_TYPE_MASK)
362 #define PCI_MAPREG_MEM_TYPE_MASK 0x00000006
363 
364 #define PCI_MAPREG_MEM_TYPE_32BIT 0x00000000
365 #define PCI_MAPREG_MEM_TYPE_32BIT_1M 0x00000002
366 #define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004
367 
368 #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \
369  (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
370 #define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008
371 
372 #define PCI_MAPREG_MEM_ADDR(mr) \
373  ((mr) & PCI_MAPREG_MEM_ADDR_MASK)
374 #define PCI_MAPREG_MEM_SIZE(mr) \
375  (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
376 #define PCI_MAPREG_MEM_ADDR_MASK 0xfffffff0
377 
378 #define PCI_MAPREG_MEM64_ADDR(mr) \
379  ((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
380 #define PCI_MAPREG_MEM64_SIZE(mr) \
381  (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
382 #define PCI_MAPREG_MEM64_ADDR_MASK 0xfffffffffffffff0ULL
383 
384 #define PCI_MAPREG_IO_ADDR(mr) \
385  ((mr) & PCI_MAPREG_IO_ADDR_MASK)
386 #define PCI_MAPREG_IO_SIZE(mr) \
387  (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
388 #define PCI_MAPREG_IO_ADDR_MASK 0xfffffffc
389 
390 #define PCI_MAPREG_SIZE_TO_MASK(size) \
391  (-(size))
392 
393 #define PCI_MAPREG_NUM(offset) \
394  (((unsigned)(offset)-PCI_MAPREG_START)/4)
395 
396 
397 /*
398  * Cardbus CIS pointer (PCI rev. 2.1)
399  */
400 #define PCI_CARDBUS_CIS_REG 0x28
401 
402 /*
403  * Subsystem identification register; contains a vendor ID and a device ID.
404  * Types/macros for PCI_ID_REG apply.
405  * (PCI rev. 2.1)
406  */
407 #define PCI_SUBSYS_ID_REG 0x2c
408 
409 /*
410  * capabilities link list (PCI rev. 2.2)
411  */
412 #define PCI_CAPLISTPTR_REG 0x34 /* header type 0 */
413 #define PCI_CARDBUS_CAPLISTPTR_REG 0x14 /* header type 2 */
414 #define PCI_CAPLIST_PTR(cpr) ((cpr) & 0xff)
415 #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
416 #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
417 
418 #define PCI_CAP_RESERVED0 0x00
419 #define PCI_CAP_PWRMGMT 0x01
420 #define PCI_CAP_AGP 0x02
421 #define PCI_CAP_VPD 0x03
422 #define PCI_CAP_SLOTID 0x04
423 #define PCI_CAP_MBI 0x05
424 #define PCI_CAP_CPCI_HOTSWAP 0x06
425 #define PCI_CAP_PCIX 0x07
426 #define PCI_CAP_LDT 0x08
427 #define PCI_CAP_VENDSPEC 0x09
428 #define PCI_CAP_DEBUGPORT 0x0a
429 #define PCI_CAP_CPCI_RSRCCTL 0x0b
430 #define PCI_CAP_HOTPLUG 0x0c
431 
432 /*
433  * Power Management Control Status Register; access via capability pointer.
434  */
435 
436 #define PCI_PMCSR_STATE_MASK 0x03
437 #define PCI_PMCSR_STATE_D0 0x00
438 #define PCI_PMCSR_STATE_D1 0x01
439 #define PCI_PMCSR_STATE_D2 0x02
440 #define PCI_PMCSR_STATE_D3 0x03
441 
442 /*
443  * Interrupt Configuration Register; contains interrupt pin and line.
444  */
445 #define PCI_INTERRUPT_REG 0x3c
446 
447 typedef u_int8_t pci_intr_latency_t;
448 typedef u_int8_t pci_intr_grant_t;
449 typedef u_int8_t pci_intr_pin_t;
450 typedef u_int8_t pci_intr_line_t;
451 
452 #define PCI_MAX_LAT_SHIFT 24
453 #define PCI_MAX_LAT_MASK 0xff
454 #define PCI_MAX_LAT(icr) \
455  (((icr) >> PCI_MAX_LAT_SHIFT) & PCI_MAX_LAT_MASK)
456 
457 #define PCI_MIN_GNT_SHIFT 16
458 #define PCI_MIN_GNT_MASK 0xff
459 #define PCI_MIN_GNT(icr) \
460  (((icr) >> PCI_MIN_GNT_SHIFT) & PCI_MIN_GNT_MASK)
461 
462 #define PCI_INTERRUPT_GRANT_SHIFT 24
463 #define PCI_INTERRUPT_GRANT_MASK 0xff
464 #define PCI_INTERRUPT_GRANT(icr) \
465  (((icr) >> PCI_INTERRUPT_GRANT_SHIFT) & PCI_INTERRUPT_GRANT_MASK)
466 
467 #define PCI_INTERRUPT_LATENCY_SHIFT 16
468 #define PCI_INTERRUPT_LATENCY_MASK 0xff
469 #define PCI_INTERRUPT_LATENCY(icr) \
470  (((icr) >> PCI_INTERRUPT_LATENCY_SHIFT) & PCI_INTERRUPT_LATENCY_MASK)
471 
472 #define PCI_INTERRUPT_PIN_SHIFT 8
473 #define PCI_INTERRUPT_PIN_MASK 0xff
474 #define PCI_INTERRUPT_PIN(icr) \
475  (((icr) >> PCI_INTERRUPT_PIN_SHIFT) & PCI_INTERRUPT_PIN_MASK)
476 
477 #define PCI_INTERRUPT_LINE_SHIFT 0
478 #define PCI_INTERRUPT_LINE_MASK 0xff
479 #define PCI_INTERRUPT_LINE(icr) \
480  (((icr) >> PCI_INTERRUPT_LINE_SHIFT) & PCI_INTERRUPT_LINE_MASK)
481 
482 #define PCI_INTERRUPT_CODE(lat,gnt,pin,line) \
483  ((((lat)&PCI_INTERRUPT_LATENCY_MASK)<<PCI_INTERRUPT_LATENCY_SHIFT)| \
484  (((gnt)&PCI_INTERRUPT_GRANT_MASK) <<PCI_INTERRUPT_GRANT_SHIFT) | \
485  (((pin)&PCI_INTERRUPT_PIN_MASK) <<PCI_INTERRUPT_PIN_SHIFT) | \
486  (((line)&PCI_INTERRUPT_LINE_MASK) <<PCI_INTERRUPT_LINE_SHIFT))
487 
488 #define PCI_INTERRUPT_PIN_NONE 0x00
489 #define PCI_INTERRUPT_PIN_A 0x01
490 #define PCI_INTERRUPT_PIN_B 0x02
491 #define PCI_INTERRUPT_PIN_C 0x03
492 #define PCI_INTERRUPT_PIN_D 0x04
493 #define PCI_INTERRUPT_PIN_MAX 0x04
494 
495 /* Header Type 1 (Bridge) configuration registers */
496 #define PCI_BRIDGE_BUS_REG 0x18
497 #define PCI_BRIDGE_BUS_PRIMARY_SHIFT 0
498 #define PCI_BRIDGE_BUS_SECONDARY_SHIFT 8
499 #define PCI_BRIDGE_BUS_SUBORDINATE_SHIFT 16
500 
501 #define PCI_BRIDGE_STATIO_REG 0x1C
502 #define PCI_BRIDGE_STATIO_IOBASE_SHIFT 0
503 #define PCI_BRIDGE_STATIO_IOLIMIT_SHIFT 8
504 #define PCI_BRIDGE_STATIO_STATUS_SHIFT 16
505 #define PCI_BRIDGE_STATIO_IOBASE_MASK 0xf0
506 #define PCI_BRIDGE_STATIO_IOLIMIT_MASK 0xf0
507 #define PCI_BRIDGE_STATIO_STATUS_MASK 0xffff
508 #define PCI_BRIDGE_IO_32BITS(reg) (((reg) & 0xf) == 1)
509 
510 #define PCI_BRIDGE_MEMORY_REG 0x20
511 #define PCI_BRIDGE_MEMORY_BASE_SHIFT 4
512 #define PCI_BRIDGE_MEMORY_LIMIT_SHIFT 20
513 #define PCI_BRIDGE_MEMORY_BASE_MASK 0xffff
514 #define PCI_BRIDGE_MEMORY_LIMIT_MASK 0xffff
515 
516 #define PCI_BRIDGE_PREFETCHMEM_REG 0x24
517 #define PCI_BRIDGE_PREFETCHMEM_BASE_SHIFT 4
518 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_SHIFT 20
519 #define PCI_BRIDGE_PREFETCHMEM_BASE_MASK 0xffff
520 #define PCI_BRIDGE_PREFETCHMEM_LIMIT_MASK 0xffff
521 #define PCI_BRIDGE_PREFETCHMEM_64BITS(reg) ((reg) & 0xf)
522 
523 #define PCI_BRIDGE_PREFETCHBASE32_REG 0x28
524 #define PCI_BRIDGE_PREFETCHLIMIT32_REG 0x2C
525 
526 #define PCI_BRIDGE_IOHIGH_REG 0x30
527 #define PCI_BRIDGE_IOHIGH_BASE_SHIFT 0
528 #define PCI_BRIDGE_IOHIGH_LIMIT_SHIFT 16
529 #define PCI_BRIDGE_IOHIGH_BASE_MASK 0xffff
530 #define PCI_BRIDGE_IOHIGH_LIMIT_MASK 0xffff
531 
532 #define PCI_BRIDGE_CONTROL_REG 0x3C
533 #define PCI_BRIDGE_CONTROL_SHIFT 16
534 #define PCI_BRIDGE_CONTROL_MASK 0xffff
535 #define PCI_BRIDGE_CONTROL_PERE (1 << 0)
536 #define PCI_BRIDGE_CONTROL_SERR (1 << 1)
537 #define PCI_BRIDGE_CONTROL_ISA (1 << 2)
538 #define PCI_BRIDGE_CONTROL_VGA (1 << 3)
539 /* Reserved (1 << 4) */
540 #define PCI_BRIDGE_CONTROL_MABRT (1 << 5)
541 #define PCI_BRIDGE_CONTROL_SECBR (1 << 6)
542 #define PCI_BRIDGE_CONTROL_SECFASTB2B (1 << 7)
543 #define PCI_BRIDGE_CONTROL_PRI_DISC_TIMER (1 << 8)
544 #define PCI_BRIDGE_CONTROL_SEC_DISC_TIMER (1 << 9)
545 #define PCI_BRIDGE_CONTROL_DISC_TIMER_STAT (1 << 10)
546 #define PCI_BRIDGE_CONTROL_DISC_TIMER_SERR (1 << 11)
547 /* Reserved (1 << 12) - (1 << 15) */
548 
549 /*
550  * Vital Product Data resource tags.
551  */
553  uint8_t vpdres_byte0; /* length of data + tag */
554  /* Actual data. */
555 } __attribute__((__packed__));
556 
558  uint8_t vpdres_byte0;
559  uint8_t vpdres_len_lsb; /* length of data only */
560  uint8_t vpdres_len_msb;
561  /* Actual data. */
562 } __attribute__((__packed__));
563 
564 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
565 
566 #define PCI_VPDRES_SMALL_LENGTH(x) ((x) & 0x7)
567 #define PCI_VPDRES_SMALL_NAME(x) (((x) >> 3) & 0xf)
568 
569 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
570 
571 #define PCI_VPDRES_TYPE_COMPATIBLE_DEVICE_ID 0x3 /* small */
572 #define PCI_VPDRES_TYPE_VENDOR_DEFINED 0xe /* small */
573 #define PCI_VPDRES_TYPE_END_TAG 0xf /* small */
574 
575 #define PCI_VPDRES_TYPE_IDENTIFIER_STRING 0x02 /* large */
576 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */
577 
578 struct pci_vpd {
579  uint8_t vpd_key0;
580  uint8_t vpd_key1;
581  uint8_t vpd_len; /* length of data only */
582  /* Actual data. */
583 } __attribute__((__packed__));
584 
585 /*
586  * Recommended VPD fields:
587  *
588  * PN Part number of assembly
589  * FN FRU part number
590  * EC EC level of assembly
591  * MN Manufacture ID
592  * SN Serial Number
593  *
594  * Conditionally recommended VPD fields:
595  *
596  * LI Load ID
597  * RL ROM Level
598  * RM Alterable ROM Level
599  * NA Network Address
600  * DD Device Driver Level
601  * DG Diagnostic Level
602  * LL Loadable Microcode Level
603  * VI Vendor ID/Device ID
604  * FU Function Number
605  * SI Subsystem Vendor ID/Subsystem ID
606  *
607  * Additional VPD fields:
608  *
609  * Z0-ZZ User/Product Specific
610  */
611 
612 #endif /* _DEV_PCI_PCIREG_H_ */
pci_vpd::vpd_key1
uint8_t vpd_key1
Definition: pcireg.h:580
pci_intr_line_t
u_int8_t pci_intr_line_t
Definition: pcireg.h:450
pci_vpd_largeres::vpdres_byte0
uint8_t vpdres_byte0
Definition: pcireg.h:558
pci_vpd_largeres::vpdres_len_lsb
uint8_t vpdres_len_lsb
Definition: pcireg.h:559
pci_vpd_smallres
Definition: pcireg.h:552
pci_interface_t
u_int8_t pci_interface_t
Definition: pcireg.h:123
pci_vpd_smallres::vpdres_byte0
uint8_t vpdres_byte0
Definition: pcireg.h:553
pci_intr_latency_t
u_int8_t pci_intr_latency_t
Definition: pcireg.h:447
pci_subclass_t
u_int8_t pci_subclass_t
Definition: pcireg.h:122
pci_vpd
Definition: pcireg.h:578
pci_revision_t
u_int8_t pci_revision_t
Definition: pcireg.h:124
__attribute__
#define __attribute__(x)
Definition: pcireg.h:15
pci_product_id_t
u_int16_t pci_product_id_t
Definition: pcireg.h:61
pci_intr_grant_t
u_int8_t pci_intr_grant_t
Definition: pcireg.h:448
pci_class_t
u_int8_t pci_class_t
Definition: pcireg.h:121
pci_vpd_largeres
Definition: pcireg.h:557
pci_vpd_largeres::vpdres_len_msb
uint8_t vpdres_len_msb
Definition: pcireg.h:560
pci_vpd::vpd_key0
uint8_t vpd_key0
Definition: pcireg.h:579
pci_vpd::vpd_len
uint8_t vpd_len
Definition: pcireg.h:581
pci_vendor_id_t
u_int16_t pci_vendor_id_t
Definition: pcireg.h:60
pci_intr_pin_t
u_int8_t pci_intr_pin_t
Definition: pcireg.h:449

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