MainbusComponent.cc Source File

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MainbusComponent.cc
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1 /*
2  * Copyright (C) 2008-2010 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
29 #include "GXemul.h"
30 
31 
33  : Component("mainbus", "mainbus")
34  , m_memoryMapFailed(false)
35  , m_memoryMapValid(false)
36  , m_currentAddressDataBus(NULL)
37 {
38 }
39 
40 
42 {
43 }
44 
45 
47 {
48  return new MainbusComponent();
49 }
50 
51 
52 string MainbusComponent::GetAttribute(const string& attributeName)
53 {
54  if (attributeName == "stable")
55  return "yes";
56 
57  if (attributeName == "description")
58  return "A generic main bus.";
59 
60  return Component::GetAttribute(attributeName);
61 }
62 
63 
65 {
66  m_memoryMap.clear();
67  m_memoryMapValid = false;
68  m_memoryMapFailed = false;
69 
70  m_currentAddressDataBus = NULL;
71 
73 }
74 
75 
77 {
79  if (!MakeSureMemoryMapExists(gxemul)) {
80  gxemul->GetUI()->ShowDebugMessage(GenerateTreeDump(""));
81  return false;
82  }
83 
84  return true;
85 }
86 
87 
88 bool MainbusComponent::MakeSureMemoryMapExists(GXemul* gxemul)
89 {
90  if (m_memoryMapFailed)
91  return false;
92 
93  if (m_memoryMapValid)
94  return true;
95 
96  m_memoryMap.clear();
97 
98  m_memoryMapValid = true;
99  m_memoryMapFailed = false;
100 
101  // Build a memory map of all immediate children who implement the
102  // AddressDataBus interface:
103  Components children = GetChildren();
104  for (size_t i=0; i<children.size(); ++i) {
105  AddressDataBus* bus = children[i]->AsAddressDataBus();
106  if (bus == NULL)
107  continue;
108 
109  MemoryMapEntry mmEntry;
110  mmEntry.addressDataBus = bus;
111  mmEntry.addrMul = 1;
112  mmEntry.base = 0;
113 
114  const StateVariable* varBase =
115  children[i]->GetVariable("memoryMappedBase");
116  const StateVariable* varSize =
117  children[i]->GetVariable("memoryMappedSize");
118  const StateVariable* varAddrMul =
119  children[i]->GetVariable("memoryMappedAddrMul");
120 
121  if (varBase != NULL)
122  mmEntry.base = varBase->ToInteger();
123  if (varSize != NULL)
124  mmEntry.size = varSize->ToInteger();
125  if (varAddrMul != NULL)
126  mmEntry.addrMul = varAddrMul->ToInteger();
127 
128  // No base or size? Then skip this component.
129  if (varSize == NULL || varBase == NULL)
130  continue;
131 
132  // Treat the non-sensical addrMul value 0 as 1.
133  if (mmEntry.addrMul == 0)
134  mmEntry.addrMul = 1;
135 
136  // Empty memory mapped region? Then skip this component.
137  if (mmEntry.size == 0)
138  continue;
139 
140  // Check for overlaps against the already existing mappings.
141  //
142  // (Note: Current implementation results in O(n^2) time,
143  // but if the number of memory-mapped immediate childs are
144  // few, then this should not be a big problem.)
145  for (size_t j=0; j<m_memoryMap.size(); ++j) {
146  if (mmEntry.base+mmEntry.size <= m_memoryMap[j].base)
147  continue;
148 
149  if (mmEntry.base >= m_memoryMap[j].base +
150  m_memoryMap[j].size)
151  continue;
152 
153  // There is overlap!
154  if (gxemul != NULL)
155  gxemul->GetUI()->ShowDebugMessage(this,
156  "Error: the base and/or size of " +
157  children[i]->GenerateShortestPossiblePath() +
158  " conflicts with another memory mapped "
159  "component on this bus.\n");
160 
161  m_memoryMap.clear();
162  m_memoryMapValid = false;
163  m_memoryMapFailed = true;
164  return false;
165  }
166 
167  // Finally add the new mapping entry.
168  m_memoryMap.push_back(mmEntry);
169  }
170 
171  return true;
172 }
173 
174 
176 {
177  return this;
178 }
179 
180 
181 void MainbusComponent::AddressSelect(uint64_t address)
182 {
183  MakeSureMemoryMapExists();
184 
185  m_currentAddressDataBus = NULL;
186 
187  if (!m_memoryMapValid)
188  return;
189 
190  // Note: This is a linear O(n) scan of the list of memory-mapped
191  // components. For small n, this should be ok.
192  //
193  // In practice, my hope is that the bulk of all memory access will be
194  // using direct-mapped pages anyway, so this should not be that much
195  // of a problem.
196 
197  for (size_t i=0; i<m_memoryMap.size(); ++i) {
198  MemoryMapEntry& mmEntry = m_memoryMap[i];
199 
200  // If this memory map entry contains the address we wish to
201  // select, then...
202  if (address >= mmEntry.base &&
203  address < mmEntry.base + mmEntry.size) {
204  // ... tell the corresponding component which address
205  // within it we wish to select.
206  m_currentAddressDataBus = mmEntry.addressDataBus;
207  m_currentAddressDataBus->AddressSelect(
208  (address - mmEntry.base) / mmEntry.addrMul);
209  break;
210  }
211  }
212 }
213 
214 
215 bool MainbusComponent::ReadData(uint8_t& data, Endianness endianness)
216 {
217  if (!MakeSureMemoryMapExists())
218  return false;
219 
220  if (m_currentAddressDataBus != NULL)
221  return m_currentAddressDataBus->ReadData(data, endianness);
222  else
223  return false;
224 }
225 
226 
227 bool MainbusComponent::ReadData(uint16_t& data, Endianness endianness)
228 {
229  if (!MakeSureMemoryMapExists())
230  return false;
231 
232  if (m_currentAddressDataBus != NULL)
233  return m_currentAddressDataBus->ReadData(data, endianness);
234  else
235  return false;
236 }
237 
238 
239 bool MainbusComponent::ReadData(uint32_t& data, Endianness endianness)
240 {
241  if (!MakeSureMemoryMapExists())
242  return false;
243 
244  if (m_currentAddressDataBus != NULL)
245  return m_currentAddressDataBus->ReadData(data, endianness);
246  else
247  return false;
248 }
249 
250 
251 bool MainbusComponent::ReadData(uint64_t& data, Endianness endianness)
252 {
253  if (!MakeSureMemoryMapExists())
254  return false;
255 
256  if (m_currentAddressDataBus != NULL)
257  return m_currentAddressDataBus->ReadData(data, endianness);
258  else
259  return false;
260 }
261 
262 
263 bool MainbusComponent::WriteData(const uint8_t& data, Endianness endianness)
264 {
265  if (!MakeSureMemoryMapExists())
266  return false;
267 
268  if (m_currentAddressDataBus != NULL)
269  return m_currentAddressDataBus->WriteData(data, endianness);
270  else
271  return false;
272 }
273 
274 
275 bool MainbusComponent::WriteData(const uint16_t& data, Endianness endianness)
276 {
277  if (!MakeSureMemoryMapExists())
278  return false;
279 
280  if (m_currentAddressDataBus != NULL)
281  return m_currentAddressDataBus->WriteData(data, endianness);
282  else
283  return false;
284 }
285 
286 
287 bool MainbusComponent::WriteData(const uint32_t& data, Endianness endianness)
288 {
289  if (!MakeSureMemoryMapExists())
290  return false;
291 
292  if (m_currentAddressDataBus != NULL)
293  return m_currentAddressDataBus->WriteData(data, endianness);
294  else
295  return false;
296 }
297 
298 
299 bool MainbusComponent::WriteData(const uint64_t& data, Endianness endianness)
300 {
301  if (!MakeSureMemoryMapExists())
302  return false;
303 
304  if (m_currentAddressDataBus != NULL)
305  return m_currentAddressDataBus->WriteData(data, endianness);
306  else
307  return false;
308 }
309 
310 
311 /*****************************************************************************/
312 
313 
314 #ifdef WITHUNITTESTS
315 
316 #include "ComponentFactory.h"
317 
318 static void Test_MainbusComponent_IsStable()
319 {
320  UnitTest::Assert("the MainbusComponent should be stable",
321  ComponentFactory::HasAttribute("mainbus", "stable"));
322 }
323 
324 static void Test_MainbusComponent_Creatable()
325 {
326  refcount_ptr<Component> mainbus =
328 
329  UnitTest::Assert("The MainbusComponent should be "
330  "instanciable", !mainbus.IsNULL());
331 }
332 
333 static void Test_MainbusComponent_AddressDataBus()
334 {
335  refcount_ptr<Component> mainbus =
337 
338  AddressDataBus* bus = mainbus->AsAddressDataBus();
339  UnitTest::Assert("The MainbusComponent should implement the "
340  "AddressDataBus interface", bus != NULL);
341 }
342 
343 static void Test_MainbusComponent_Simple()
344 {
345  refcount_ptr<Component> mainbus =
349 
350  mainbus->AddChild(ram0);
351  ram0->SetVariableValue("memoryMappedSize", "0x100000");
352  ram0->SetVariableValue("memoryMappedBase", "0");
353 
354  AddressDataBus* bus = mainbus->AsAddressDataBus();
355 
356  uint8_t dataByte = 42;
357  bus->AddressSelect(128);
358  bus->WriteData(dataByte);
359  bus->AddressSelect(129);
360  dataByte = 100;
361  bus->WriteData(dataByte);
362  bus->AddressSelect(128);
363  bus->ReadData(dataByte);
364  UnitTest::Assert("memory wasn't written to correctly?", dataByte, 42);
365  bus->AddressSelect(129);
366  bus->ReadData(dataByte);
367  UnitTest::Assert("memory wasn't written to correctly?", dataByte, 100);
368 }
369 
370 static void Test_MainbusComponent_Remapping()
371 {
372  refcount_ptr<Component> mainbus =
376 
377  mainbus->AddChild(ram0);
378  ram0->SetVariableValue("memoryMappedSize", "0x10000");
379  ram0->SetVariableValue("memoryMappedBase", "0x1000");
380 
381  AddressDataBus* bus = mainbus->AsAddressDataBus();
382 
383  uint8_t dataByte = 123;
384  bus->AddressSelect(0x1030); // offset 0x30 of ram0
385  bus->WriteData(dataByte);
386  dataByte = 18;
387  bus->AddressSelect(0x1050); // offset 0x50 of ram0
388  bus->WriteData(dataByte);
389 
390  // Set a new base for ram0, but do _NOT_ flush cached state yet!
391  // (This is to assert that cached state is actually cached.)
392  ram0->SetVariableValue("memoryMappedBase", "0x1020");
393 
394  uint8_t dataByte2 = 99;
395  bus->AddressSelect(0x1050); // offset 0x30 of ram0
396  bus->ReadData(dataByte2);
397  UnitTest::Assert("remapping should NOT have taken place yet, "
398  "cached state should still be in effect!", dataByte2, 18);
399 
400  // Now, flush the state and make sure the new mapping takes effect:
401  mainbus->FlushCachedState();
402 
403  dataByte2 = 99;
404  bus->AddressSelect(0x1050); // offset 0x30 of ram0
405  bus->ReadData(dataByte2);
406  UnitTest::Assert("remapping failed?", dataByte2, 123);
407 }
408 
409 static void Test_MainbusComponent_Multiple_NonOverlapping()
410 {
411  refcount_ptr<Component> mainbus =
419 
420  mainbus->AddChild(ram0);
421  mainbus->AddChild(ram1);
422  mainbus->AddChild(ram2);
423  ram0->SetVariableValue("memoryMappedSize", "0x100");
424  ram0->SetVariableValue("memoryMappedBase", "0x000");
425  ram1->SetVariableValue("memoryMappedSize", "0x100");
426  ram1->SetVariableValue("memoryMappedBase", "0x100");
427  ram2->SetVariableValue("memoryMappedSize", "0x100");
428  ram2->SetVariableValue("memoryMappedBase", "0x200");
429 
430  AddressDataBus* bus = mainbus->AsAddressDataBus();
431 
432  for (size_t i = 0; i < 0x300; i += sizeof(uint16_t)) {
433  uint16_t data = (uint8_t) i;
434  bus->AddressSelect(i);
435  bus->WriteData(data, LittleEndian);
436  }
437 
438  for (size_t i = 0; i < 0x300; i += sizeof(uint16_t)) {
439  uint16_t data;
440  bus->AddressSelect(i);
441  bus->ReadData(data, BigEndian);
442  UnitTest::Assert("memory wasn't written to correctly?",
443  data, (uint16_t) (i << 8));
444  }
445 }
446 
447 static void Test_MainbusComponent_Simple_With_AddrMul()
448 {
449  refcount_ptr<Component> mainbus =
453 
454  mainbus->AddChild(ram0);
455  ram0->SetVariableValue("memoryMappedSize", "0x1000");
456  ram0->SetVariableValue("memoryMappedBase", "0x80");
457  ram0->SetVariableValue("memoryMappedAddrMul", "5");
458 
459  AddressDataBus* bus = mainbus->AsAddressDataBus();
460 
461  uint8_t dataByte = 42;
462  bus->AddressSelect(128);
463  bus->WriteData(dataByte);
464  bus->AddressSelect(133);
465  dataByte = 100;
466  bus->WriteData(dataByte);
467 
468  bus->AddressSelect(128);
469  bus->ReadData(dataByte);
470  UnitTest::Assert("memory wasn't written to correctly?", dataByte, 42);
471  bus->AddressSelect(133);
472  bus->ReadData(dataByte);
473  UnitTest::Assert("memory wasn't written to correctly?", dataByte, 100);
474 
475  ram0->SetVariableValue("memoryMappedAddrMul", "2");
476  mainbus->FlushCachedState();
477 
478  bus->AddressSelect(128);
479  bus->ReadData(dataByte);
480  UnitTest::Assert("addr mul strangeness?", dataByte, 42);
481  bus->AddressSelect(130);
482  bus->ReadData(dataByte);
483  UnitTest::Assert("offset 130 should have the same value as "
484  "offset 133 had", dataByte, 100);
485  bus->AddressSelect(133);
486  bus->ReadData(dataByte);
487  UnitTest::Assert("offset 133 should NOT have any value "
488  "written to it yet!", dataByte, 0);
489 
490  ram0->SetVariableValue("memoryMappedAddrMul", "1");
491  mainbus->FlushCachedState();
492 
493  bus->AddressSelect(128);
494  bus->ReadData(dataByte);
495  UnitTest::Assert("addr mul strangeness [2]", dataByte, 42);
496  bus->AddressSelect(129);
497  bus->ReadData(dataByte);
498  UnitTest::Assert("offset 129 mismatch [2]", dataByte, 100);
499  bus->AddressSelect(133);
500  bus->ReadData(dataByte);
501  UnitTest::Assert("offset 133 should NOT have any value "
502  "written to it yet! [2]", dataByte, 0);
503 
504  // AddrMul "0" should be same as "1", because the user might think that
505  // address multiplication is "turned off" by setting it to 0.
506  ram0->SetVariableValue("memoryMappedAddrMul", "0");
507  mainbus->FlushCachedState();
508 
509  bus->AddressSelect(128);
510  bus->ReadData(dataByte);
511  UnitTest::Assert("addr mul strangeness [3]", dataByte, 42);
512  bus->AddressSelect(129);
513  bus->ReadData(dataByte);
514  UnitTest::Assert("offset 129 mismatch [3]", dataByte, 100);
515  bus->AddressSelect(133);
516  bus->ReadData(dataByte);
517  UnitTest::Assert("offset 133 should NOT have any value "
518  "written to it yet! [3]", dataByte, 0);
519 }
520 
521 static void Test_MainbusComponent_PreRunCheck()
522 {
523  GXemul gxemul;
524 
525  gxemul.GetCommandInterpreter().RunCommand("add testmips");
526 
527  UnitTest::Assert("preruncheck should initially succeed for testmips",
528  gxemul.GetRootComponent()->PreRunCheck(&gxemul) == true);
529 
530  // Adding a second RAM component should succeed, since the initial size
531  // is 0, and does not (yet) conflict.
532  gxemul.GetCommandInterpreter().RunCommand("add ram mainbus0");
533  UnitTest::Assert("preruncheck should still succeed",
534  gxemul.GetRootComponent()->PreRunCheck(&gxemul) == true);
535 
536  // By changing the size to 42, the new ram1 component will overlap
537  // the ram0 component (at least partially).
538  gxemul.GetCommandInterpreter().RunCommand("ram1.memoryMappedSize = 42");
539  UnitTest::Assert("preruncheck should now fail",
540  gxemul.GetRootComponent()->PreRunCheck(&gxemul) == false);
541 }
542 
544 {
545  // Construction, etc.:
546  UNITTEST(Test_MainbusComponent_IsStable);
547  UNITTEST(Test_MainbusComponent_Creatable);
548  UNITTEST(Test_MainbusComponent_AddressDataBus);
549 
550  // Memory mapping, ranges, overlaps, addrmul, etc.:
551  UNITTEST(Test_MainbusComponent_Simple);
552  UNITTEST(Test_MainbusComponent_Remapping);
553  UNITTEST(Test_MainbusComponent_Multiple_NonOverlapping);
554  UNITTEST(Test_MainbusComponent_Simple_With_AddrMul);
555 
556  // TODO: Write outside of mapped space
557  // TODO: Write PARTIALLY outside of mapped space!!! e.g. 64-bit
558  // into a 3-byte memory area???
559 
560  UNITTEST(Test_MainbusComponent_PreRunCheck);
561 }
562 
563 #endif
564 
Component::PreRunCheck
bool PreRunCheck(GXemul *gxemul)
Checks the state of this component and all its children, before starting execution.
Definition: Component.cc:298
data
u_short data
Definition: siireg.h:79
Component::FlushCachedStateForComponent
virtual void FlushCachedStateForComponent()
Resets the cached state of this component.
Definition: Component.cc:327
AddressDataBus::ReadData
virtual bool ReadData(uint8_t &data, Endianness endianness=BigEndian)=0
Reads 8-bit data from the currently selected address.
refcount_ptr::IsNULL
bool IsNULL() const
Checks whether or not an object is referenced by the reference counted pointer.
Definition: refcount_ptr.h:216
Component::GenerateTreeDump
string GenerateTreeDump(const string &branchTemplate, bool htmlLinksForClassNames=false, string prefixForComponentUrls="") const
Generates an ASCII tree dump of a component tree.
Definition: Component.cc:459
Component::AddChild
void AddChild(refcount_ptr< Component > childComponent, size_t insertPosition=(size_t) -1)
Adds a reference to a child component.
Definition: Component.cc:595
MainbusComponent::Create
static refcount_ptr< Component > Create(const ComponentCreateArgs &args)
Creates a MainbusComponent.
Definition: MainbusComponent.cc:46
ComponentFactory.h
GXemul
The main emulator class.
Definition: GXemul.h:54
MainbusComponent::GetAttribute
static string GetAttribute(const string &attributeName)
Get attribute information about the MainbusComponent class.
Definition: MainbusComponent.cc:52
MainbusComponent::AddressSelect
virtual void AddressSelect(uint64_t address)
Place an address on the bus.
Definition: MainbusComponent.cc:181
MainbusComponent::MainbusComponent
MainbusComponent()
Constructs a MainbusComponent.
Definition: MainbusComponent.cc:32
MainbusComponent::AsAddressDataBus
virtual AddressDataBus * AsAddressDataBus()
Returns the component's AddressDataBus interface.
Definition: MainbusComponent.cc:175
GXemul::GetCommandInterpreter
CommandInterpreter & GetCommandInterpreter()
Gets a reference to the CommandInterpreter.
Definition: GXemul.cc:631
MainbusComponent::PreRunCheckForComponent
virtual bool PreRunCheckForComponent(GXemul *gxemul)
Checks the state of this component, before starting execution.
Definition: MainbusComponent.cc:76
LittleEndian
@ LittleEndian
Definition: misc.h:159
StateVariable
StateVariables make up the persistent state of Component objects.
Definition: StateVariable.h:67
refcount_ptr< Component >
StateVariable::ToInteger
uint64_t ToInteger() const
Returns the variable as an unsignedinteger value.
Definition: StateVariable.cc:280
UNITTESTS
#define UNITTESTS(class)
Helper for unit test case execution.
Definition: UnitTest.h:184
MainbusComponent::ReadData
virtual bool ReadData(uint8_t &data, Endianness endianness)
Reads 8-bit data from the currently selected address.
Definition: MainbusComponent.cc:215
UNITTEST
#define UNITTEST(functionname)
Helper for unit test case execution.
Definition: UnitTest.h:217
UnitTest::Assert
static void Assert(const string &strFailMessage, bool condition)
Asserts that a boolean condition is correct.
Definition: UnitTest.cc:40
Component::GetChildren
Components & GetChildren()
Gets pointers to child components.
Definition: Component.cc:674
AddressDataBus::WriteData
virtual bool WriteData(const uint8_t &data, Endianness endianness=BigEndian)=0
Writes 8-bit data to the currently selected address.
GXemul::GetRootComponent
refcount_ptr< Component > GetRootComponent()
Gets a pointer to the root configuration component.
Definition: GXemul.cc:667
UI::ShowDebugMessage
virtual void ShowDebugMessage(const string &msg)=0
Shows a debug message.
MainbusComponent::FlushCachedStateForComponent
virtual void FlushCachedStateForComponent()
Resets the cached state of this component.
Definition: MainbusComponent.cc:64
Endianness
Endianness
Definition: misc.h:156
MainbusComponent::WriteData
virtual bool WriteData(const uint8_t &data, Endianness endianness)
Writes 8-bit data to the currently selected address.
Definition: MainbusComponent.cc:263
ComponentFactory::CreateComponent
static refcount_ptr< Component > CreateComponent(const string &componentNameAndOptionalArgs, GXemul *gxemul=NULL)
Creates a component given a short component name.
Definition: ComponentFactory.cc:87
Component::SetVariableValue
bool SetVariableValue(const string &name, const string &expression)
Sets a variable to a new value.
Definition: Component.cc:1030
AddressDataBus::AddressSelect
virtual void AddressSelect(uint64_t address)=0
Place an address on the bus.
Component::GenerateShortestPossiblePath
string GenerateShortestPossiblePath() const
Generates a short string representation of the path to the Component.
Definition: Component.cc:721
CommandInterpreter::RunCommand
bool RunCommand(const string &command, bool *pSuccess=NULL)
Runs a command, given as a string.
Definition: CommandInterpreter.cc:957
GXemul::GetUI
UI * GetUI()
Gets a pointer to the GXemul instance' active UI.
Definition: GXemul.cc:661
Component
A Component is a node in the configuration tree that makes up an emulation setup.
Definition: Component.h:62
MainbusComponent
Main bus Component.
Definition: MainbusComponent.h:47
Components
vector< refcount_ptr< Component > > Components
Definition: Component.h:43
MainbusComponent::~MainbusComponent
virtual ~MainbusComponent()
Definition: MainbusComponent.cc:41
ComponentFactory::HasAttribute
static bool HasAttribute(const string &name, const string &attributeName)
Checks if a component has a specific attribute.
Definition: ComponentFactory.cc:210
MainbusComponent.h
Component::FlushCachedState
void FlushCachedState()
Resets the cached state of this component and all its children.
Definition: Component.cc:317
AddressDataBus
An interface for implementing components that read/write data via an address bus.
Definition: AddressDataBus.h:44
Component::GetAttribute
static string GetAttribute(const string &attributeName)
Creates a Component.
Definition: Component.cc:66
BigEndian
@ BigEndian
Definition: misc.h:158
Component::AsAddressDataBus
virtual AddressDataBus * AsAddressDataBus()
Returns the component's AddressDataBus interface, if any.
Definition: Component.cc:367
ComponentCreateArgs
Definition: Component.h:48
GXemul.h

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