cpu_sh.cc Source File
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57 #define DYNTRANS_DELAYSLOT
78 int cpu_id,
char *cpu_type_name)
84 while (cpu_type_defs[i].
name != NULL) {
85 if (strcasecmp(cpu_type_defs[i].
name, cpu_type_name) == 0) {
90 if (cpu_type_defs[i].
name == NULL)
100 fatal(
"SH64 emulation not implemented. Sorry.\n");
147 snprintf(tmpstr,
sizeof(tmpstr),
"r%i", i);
152 snprintf(tmpstr,
sizeof(tmpstr),
"r%i_bank", i);
157 snprintf(tmpstr,
sizeof(tmpstr),
"fr%i", i);
159 snprintf(tmpstr,
sizeof(tmpstr),
"xf%i", i);
164 snprintf(tmpstr,
sizeof(tmpstr),
"itlb_hi_%i", i);
166 snprintf(tmpstr,
sizeof(tmpstr),
"itlb_lo_%i", i);
171 snprintf(tmpstr,
sizeof(tmpstr),
"utlb_hi_%i", i);
173 snprintf(tmpstr,
sizeof(tmpstr),
"utlb_lo_%i", i);
182 snprintf(
name,
sizeof(
name),
"%s.irq[0x%x]",
184 memset(&templ, 0,
sizeof(templ));
194 memset(&templ, 0,
sizeof(templ));
308 unsigned int index = irq_nr / 0x20;
317 fatal(
"[ SH interrupt 0x%x, prio 0 (?), aborting ]\n", irq_nr);
335 int index = irq_nr / 0x20;
346 for (index=0; index<0x1000/0x20; index++) {
369 while (tdefs[i].
name != NULL) {
374 if ((i % 6) == 0 || tdefs[i].
name == NULL)
385 debug(
" (%s-endian)\n",
397 uint16_t iword = *((uint16_t *)&ib[0]);
431 switch ((iword >> 8) & 0xf) {
465 debug(
"cpu%i: pc = 0x%08" PRIx32, x, (uint32_t)
cpu->
pc);
468 debug(
"cpu%i: sr = 0x%08" PRIx32
" (%s, %s, %s, %s, %s, %s,"
469 " imask=0x%x, %s, %s)\n", x, (int32_t)
cpu->
cd.
sh.
sr,
485 debug(
"cpu%i: mach = 0x%08" PRIx32
" macl = 0x%08" PRIx32
486 " gbr = 0x%08" PRIx32
"\n", x, (uint32_t)
cpu->
cd.
sh.
mach,
500 debug(
"cpu%i: fpscr = 0x%08" PRIx32
" (%s,%s,%s) fpul = 0x%08"
526 debug(
"cpu%i: vbr = 0x%08" PRIx32
" sgr = 0x%08" PRIx32
529 debug(
"cpu%i: spc = 0x%08" PRIx32
" ssr = 0x%08" PRIx32
"\n",
531 debug(
"cpu%i: expevt = 0x%" PRIx32
" intevt = 0x%" PRIx32
538 debug(
" r%i_bank = 0x%08x ", i,
560 for (j=0; j<m->
ncpus; j++) {
563 if (x >= 0 && j != x)
567 printf(
"cpu%i: itlb_hi_%-2i = 0x%08" PRIx32
" "
568 "itlb_lo_%-2i = 0x%08" PRIx32
"\n", j, i,
572 printf(
"cpu%i: utlb_hi_%-2i = 0x%08" PRIx32
" "
573 "utlb_lo_%-2i = 0x%08" PRIx32
"\n", j, i,
638 debug(
"[ interrupt 0x%03x", intevt);
640 debug(
"[ exception 0x%03x", expevt);
642 debug(
", pc=0x%08" PRIx32
" ", (uint32_t)
cpu->
pc);
644 debug(
"vaddr=0x%08" PRIx32
" ", vaddr);
650 fatal(
"[ sh_exception(): BL bit already set. ]\n");
667 cpu->
pc +=
sizeof(uint16_t);
672 cpu->
pc -=
sizeof(uint16_t);
694 cpu->
pc = vbr + 0x100;
701 cpu->
pc = vbr + 0x600;
706 cpu->
pc = 0xa0000000;
713 cpu->
pc = vbr + 0x400;
740 printf(
"\nRESERVED SuperH instruction at spc=%08" PRIx32
"\n",
750 default:
fatal(
"sh_exception(): exception 0x%x is not yet "
751 "implemented.\n", expevt);
776 int running, uint64_t dumpaddr)
779 uint64_t offset,
addr;
787 if (
symbol != NULL && offset==0)
793 debug(
"%08" PRIx32, (uint32_t) dumpaddr);
801 const int hi4 = iword >> 12, lo4 = iword & 15, lo8 = iword & 255;
802 int r8 = (iword >> 8) & 15, r4 = (iword >> 4) & 15;
812 debug(
"stc\tsr,r%i\n", r8);
813 else if (lo8 == 0x03)
814 debug(
"bsrf\tr%i\n", r8);
815 else if (lo4 >= 4 && lo4 <= 6) {
817 debug(
"mov.b\tr%i,@(r0,r%i)", r4, r8);
819 debug(
"mov.w\tr%i,@(r0,r%i)", r4, r8);
821 debug(
"mov.l\tr%i,@(r0,r%i)", r4, r8);
824 debug(
"\t; r0+r%i = ", r8);
834 }
else if (lo4 == 0x7)
835 debug(
"mul.l\tr%i,r%i\n", r4, r8);
836 else if (iword == 0x0008)
838 else if (iword == 0x0009)
840 else if (lo8 == 0x0a)
841 debug(
"sts\tmach,r%i\n", r8);
842 else if (iword == 0x000b)
844 else if (lo4 >= 0xc && lo4 <= 0xe) {
846 debug(
"mov.b\t@(r0,r%i),r%i", r4, r8);
848 debug(
"mov.w\t@(r0,r%i),r%i", r4, r8);
850 debug(
"mov.l\t@(r0,r%i),r%i", r4, r8);
853 debug(
"\t; r0+r%i = ", r4);
863 }
else if (lo8 == 0x12)
864 debug(
"stc\tgbr,r%i\n", r8);
865 else if (iword == 0x0018)
867 else if (iword == 0x0019)
869 else if (lo8 == 0x1a)
870 debug(
"sts\tmacl,r%i\n", r8);
871 else if (iword == 0x001b)
873 else if (lo8 == 0x22)
874 debug(
"stc\tvbr,r%i\n", r8);
875 else if (lo8 == 0x23)
876 debug(
"braf\tr%i\n", r8);
877 else if (iword == 0x0028)
879 else if (lo8 == 0x29)
880 debug(
"movt\tr%i\n", r8);
881 else if (lo8 == 0x2a)
882 debug(
"sts\tpr,r%i\n", r8);
883 else if (iword == 0x002b)
885 else if (lo8 == 0x32)
886 debug(
"stc\tssr,r%i\n", r8);
887 else if (iword == 0x0038)
889 else if (iword == 0x003b)
891 else if (lo8 == 0x42)
892 debug(
"stc\tspc,r%i\n", r8);
893 else if (iword == 0x0048)
895 else if (iword == 0x0058)
897 else if (lo8 == 0x5a)
898 debug(
"sts\tfpul,r%i\n", r8);
899 else if (lo8 == 0x6a)
900 debug(
"sts\tfpscr,r%i\n", r8);
901 else if ((lo8 & 0x8f) == 0x82)
902 debug(
"stc\tr%i_bank,r%i\n", (lo8 >> 4) & 7, r8);
903 else if (lo8 == 0x83)
904 debug(
"pref\t@r%i\n", r8);
905 else if (lo8 == 0x93)
906 debug(
"ocbi\t@r%i\n", r8);
907 else if (lo8 == 0xa3)
908 debug(
"ocbp\t@r%i\n", r8);
909 else if (lo8 == 0xb3)
910 debug(
"ocbwb\t@r%i\n", r8);
911 else if (lo8 == 0xc3)
912 debug(
"movca.l\tr0,@r%i\n", r8);
913 else if (lo8 == 0xfa)
914 debug(
"stc\tdbr,r%i\n", r8);
916 debug(
"gxemul_dreamcast_prom_emul\n");
918 debug(
"UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
921 debug(
"mov.l\tr%i,@(%i,r%i)", r4, lo4 * 4, r8);
924 debug(
"\t; r%i+%i = ", r8, lo4 * 4);
936 debug(
"mov.b\tr%i,@r%i", r4, r8);
938 debug(
"mov.w\tr%i,@r%i", r4, r8);
940 debug(
"mov.l\tr%i,@r%i", r4, r8);
942 debug(
"mov.b\tr%i,@-r%i", r4, r8);
944 debug(
"mov.w\tr%i,@-r%i", r4, r8);
946 debug(
"mov.l\tr%i,@-r%i", r4, r8);
948 debug(
"div0s\tr%i,r%i", r4, r8);
950 debug(
"tst\tr%i,r%i", r4, r8);
952 debug(
"and\tr%i,r%i", r4, r8);
954 debug(
"xor\tr%i,r%i", r4, r8);
956 debug(
"or\tr%i,r%i", r4, r8);
958 debug(
"cmp/str\tr%i,r%i", r4, r8);
960 debug(
"xtrct\tr%i,r%i", r4, r8);
962 debug(
"mulu.w\tr%i,r%i", r4, r8);
964 debug(
"muls.w\tr%i,r%i", r4, r8);
966 debug(
"UNIMPLEMENTED hi4=0x%x, lo8=0x%02x", hi4, lo8);
974 debug(
"cmp/eq\tr%i,r%i\n", r4, r8);
976 debug(
"cmp/hs\tr%i,r%i\n", r4, r8);
978 debug(
"cmp/ge\tr%i,r%i\n", r4, r8);
980 debug(
"div1\tr%i,r%i\n", r4, r8);
982 debug(
"dmulu.l\tr%i,r%i\n", r4, r8);
984 debug(
"cmp/hi\tr%i,r%i\n", r4, r8);
986 debug(
"cmp/gt\tr%i,r%i\n", r4, r8);
988 debug(
"sub\tr%i,r%i\n", r4, r8);
990 debug(
"subc\tr%i,r%i\n", r4, r8);
992 debug(
"subv\tr%i,r%i\n", r4, r8);
994 debug(
"add\tr%i,r%i\n", r4, r8);
996 debug(
"dmuls.l\tr%i,r%i\n", r4, r8);
998 debug(
"addc\tr%i,r%i\n", r4, r8);
1000 debug(
"addv\tr%i,r%i\n", r4, r8);
1002 debug(
"UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
1006 debug(
"shll\tr%i\n", r8);
1007 else if (lo8 == 0x01)
1008 debug(
"shlr\tr%i\n", r8);
1009 else if (lo8 == 0x02)
1010 debug(
"sts.l\tmach,@-r%i\n", r8);
1011 else if (lo8 == 0x03)
1012 debug(
"stc.l\tsr,@-r%i\n", r8);
1013 else if (lo8 == 0x04)
1014 debug(
"rotl\tr%i\n", r8);
1015 else if (lo8 == 0x05)
1016 debug(
"rotr\tr%i\n", r8);
1017 else if (lo8 == 0x06)
1018 debug(
"lds.l\t@r%i+,mach\n", r8);
1019 else if (lo8 == 0x07)
1020 debug(
"ldc.l\t@r%i+,sr\n", r8);
1021 else if (lo8 == 0x08)
1022 debug(
"shll2\tr%i\n", r8);
1023 else if (lo8 == 0x09)
1024 debug(
"shlr2\tr%i\n", r8);
1025 else if (lo8 == 0x0a)
1026 debug(
"lds\tr%i,mach\n", r8);
1027 else if (lo8 == 0x0b)
1028 debug(
"jsr\t@r%i\n", r8);
1029 else if (lo4 == 0xc)
1030 debug(
"shad\tr%i,r%i\n", r4, r8);
1031 else if (lo4 == 0xd)
1032 debug(
"shld\tr%i,r%i\n", r4, r8);
1033 else if (lo8 == 0x0e)
1034 debug(
"ldc\tr%i,sr\n", r8);
1035 else if (lo8 == 0x10)
1036 debug(
"dt\tr%i\n", r8);
1037 else if (lo8 == 0x11)
1038 debug(
"cmp/pz\tr%i\n", r8);
1039 else if (lo8 == 0x12)
1040 debug(
"sts.l\tmacl,@-r%i\n", r8);
1041 else if (lo8 == 0x13)
1042 debug(
"stc.l\tgbr,@-r%i\n", r8);
1043 else if (lo8 == 0x15)
1044 debug(
"cmp/pl\tr%i\n", r8);
1045 else if (lo8 == 0x16)
1046 debug(
"lds.l\t@r%i+,macl\n", r8);
1047 else if (lo8 == 0x17)
1048 debug(
"ldc.l\t@r%i+,gbr\n", r8);
1049 else if (lo8 == 0x18)
1050 debug(
"shll8\tr%i\n", r8);
1051 else if (lo8 == 0x19)
1052 debug(
"shlr8\tr%i\n", r8);
1053 else if (lo8 == 0x1a)
1054 debug(
"lds\tr%i,macl\n", r8);
1055 else if (lo8 == 0x1b)
1056 debug(
"tas.b\t@r%i\n", r8);
1057 else if (lo8 == 0x1e)
1058 debug(
"ldc\tr%i,gbr\n", r8);
1059 else if (lo8 == 0x20)
1060 debug(
"shal\tr%i\n", r8);
1061 else if (lo8 == 0x21)
1062 debug(
"shar\tr%i\n", r8);
1063 else if (lo8 == 0x22)
1064 debug(
"sts.l\tpr,@-r%i\n", r8);
1065 else if (lo8 == 0x23)
1066 debug(
"stc.l\tvbr,@-r%i\n", r8);
1067 else if (lo8 == 0x24)
1068 debug(
"rotcl\tr%i\n", r8);
1069 else if (lo8 == 0x25)
1070 debug(
"rotcr\tr%i\n", r8);
1071 else if (lo8 == 0x26)
1072 debug(
"lds.l\t@r%i+,pr\n", r8);
1073 else if (lo8 == 0x27)
1074 debug(
"ldc.l\t@r%i+,vbr\n", r8);
1075 else if (lo8 == 0x28)
1076 debug(
"shll16\tr%i\n", r8);
1077 else if (lo8 == 0x29)
1078 debug(
"shlr16\tr%i\n", r8);
1079 else if (lo8 == 0x2a)
1080 debug(
"lds\tr%i,pr\n", r8);
1081 else if (lo8 == 0x2b) {
1082 debug(
"jmp\t@r%i", r8);
1091 }
else if (lo8 == 0x2e)
1092 debug(
"ldc\tr%i,vbr\n", r8);
1093 else if (lo8 == 0x33)
1094 debug(
"stc.l\tssr,@-r%i\n", r8);
1095 else if (lo8 == 0x37)
1096 debug(
"ldc.l\t@r%i+,ssr\n", r8);
1097 else if (lo8 == 0x3e)
1098 debug(
"ldc\tr%i,ssr\n", r8);
1099 else if (lo8 == 0x43)
1100 debug(
"stc.l\tspc,@-r%i\n", r8);
1101 else if (lo8 == 0x47)
1102 debug(
"ldc.l\t@r%i+,spc\n", r8);
1103 else if (lo8 == 0x4e)
1104 debug(
"ldc\tr%i,spc\n", r8);
1105 else if (lo8 == 0x52)
1106 debug(
"sts.l\tfpul,@-r%i\n", r8);
1107 else if (lo8 == 0x56)
1108 debug(
"lds.l\t@r%i+,fpul\n", r8);
1109 else if (lo8 == 0x5a)
1110 debug(
"lds\tr%i,fpul\n", r8);
1111 else if (lo8 == 0x62)
1112 debug(
"sts.l\tfpscr,@-r%i\n", r8);
1113 else if (lo8 == 0x66)
1114 debug(
"lds.l\t@r%i+,fpscr\n", r8);
1115 else if (lo8 == 0x6a)
1116 debug(
"lds\tr%i,fpscr\n", r8);
1117 else if ((lo8 & 0x8f) == 0x83)
1118 debug(
"stc.l\tr%i_bank,@-r%i\n", (lo8 >> 4) & 7, r8);
1119 else if ((lo8 & 0x8f) == 0x87)
1120 debug(
"ldc.l\t@r%i,r%i_bank\n", r8, (lo8 >> 4) & 7, r8);
1121 else if ((lo8 & 0x8f) == 0x8e)
1122 debug(
"ldc\tr%i,r%i_bank\n", r8, (lo8 >> 4) & 7);
1123 else if (lo8 == 0xfa)
1124 debug(
"ldc\tr%i,dbr\n", r8);
1126 debug(
"UNIMPLEMENTED hi4=0x%x, lo8=0x%02x\n", hi4, lo8);
1129 debug(
"mov.l\t@(%i,r%i),r%i", lo4 * 4, r4, r8);
1136 debug(
"\t; r%i+%i = 0x%08" PRIx32, r4, lo4 * 4, (
int)
addr);
1142 debug(
"mov.b\t@r%i,r%i", r4, r8);
1143 else if (lo4 == 0x1)
1144 debug(
"mov.w\t@r%i,r%i", r4, r8);
1145 else if (lo4 == 0x2)
1146 debug(
"mov.l\t@r%i,r%i", r4, r8);
1147 else if (lo4 == 0x3)
1148 debug(
"mov\tr%i,r%i", r4, r8);
1149 else if (lo4 == 0x4)
1150 debug(
"mov.b\t@r%i+,r%i", r4, r8);
1151 else if (lo4 == 0x5)
1152 debug(
"mov.w\t@r%i+,r%i", r4, r8);
1153 else if (lo4 == 0x6)
1154 debug(
"mov.l\t@r%i+,r%i", r4, r8);
1155 else if (lo4 == 0x7)
1156 debug(
"not\tr%i,r%i", r4, r8);
1157 else if (lo4 == 0x8)
1158 debug(
"swap.b\tr%i,r%i", r4, r8);
1159 else if (lo4 == 0x9)
1160 debug(
"swap.w\tr%i,r%i", r4, r8);
1161 else if (lo4 == 0xa)
1162 debug(
"negc\tr%i,r%i", r4, r8);
1163 else if (lo4 == 0xb)
1164 debug(
"neg\tr%i,r%i", r4, r8);
1165 else if (lo4 == 0xc)
1166 debug(
"extu.b\tr%i,r%i", r4, r8);
1167 else if (lo4 == 0xd)
1168 debug(
"extu.w\tr%i,r%i", r4, r8);
1169 else if (lo4 == 0xe)
1170 debug(
"exts.b\tr%i,r%i", r4, r8);
1171 else if (lo4 == 0xf)
1172 debug(
"exts.w\tr%i,r%i", r4, r8);
1174 debug(
"UNIMPLEMENTED hi4=0x%x, lo8=0x%02x", hi4, lo8);
1175 if (
running && lo4 < 8 && (lo4 & 3) < 3) {
1181 debug(
"add\t#%i,r%i\n", (int8_t)lo8, r8);
1184 if (r8 == 0 || r8 == 4) {
1186 debug(
"mov.b\tr0,@(%i,r%i)", lo4, r4);
1188 debug(
"mov.b\t@(%i,r%i),r0", lo4, r4);
1190 debug(
"\t; r%i+%i = 0x%08" PRIx32, r4, lo4,
1194 }
else if (r8 == 1 || r8 == 5) {
1196 debug(
"mov.w\tr0,@(%i,r%i)", lo4 * 2, r4);
1198 debug(
"mov.w\t@(%i,r%i),r0", lo4 * 2, r4);
1200 debug(
"\t; r%i+%i = 0x%08" PRIx32, r4, lo4 * 2,
1204 }
else if (r8 == 0x8) {
1205 debug(
"cmp/eq\t#%i,r0\n", (int8_t)lo8);
1206 }
else if (r8 == 0x9 || r8 == 0xb || r8 == 0xd || r8 == 0xf) {
1209 debug(
"b%s%s\t0x%x",
1210 (r8 == 0x9 || r8 == 0xd)?
"t" :
"f",
1211 (r8 == 0x9 || r8 == 0xb)?
"" :
"/s", (
int)
addr);
1218 debug(
"UNIMPLEMENTED hi4=0x%x,0x%x\n", hi4, r8);
1222 addr = lo8 * (hi4==9? 2 : 4);
1223 addr += (dumpaddr & ~(hi4==9? 1 : 3)) + 4;
1224 debug(
"mov.%s\t0x%x,r%i", hi4==9?
"w":
"l", (
int)
addr, r8);
1233 addr = (int32_t)(int16_t)((iword & 0xfff) << 4);
1235 addr += dumpaddr + 4;
1236 debug(
"%s\t0x%x", hi4==0xa?
"bra":
"bsr", (
int)
addr);
1246 debug(
"mov.b\tr0,@(%i,gbr)\n", lo8);
1248 debug(
"mov.w\tr0,@(%i,gbr)\n", lo8 * 2);
1250 debug(
"mov.l\tr0,@(%i,gbr)\n", lo8 * 4);
1252 debug(
"trapa\t#%i\n", (uint8_t)lo8);
1254 debug(
"mov.b\t(%i,gbr),r0\n", lo8);
1256 debug(
"mov.w\t(%i,gbr),r0\n", lo8 * 2);
1258 debug(
"mov.l\t(%i,gbr),r0\n", lo8 * 4);
1259 else if (r8 == 0x7) {
1260 addr = lo8 * 4 + (dumpaddr & ~3) + 4;
1262 }
else if (r8 == 0x8)
1263 debug(
"tst\t#%i,r0\n", (uint8_t)lo8);
1265 debug(
"and\t#%i,r0\n", (uint8_t)lo8);
1267 debug(
"xor\t#%i,r0\n", (uint8_t)lo8);
1269 debug(
"or\t#%i,r0\n", (uint8_t)lo8);
1271 debug(
"tst.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
1273 debug(
"and.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
1275 debug(
"xor.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
1277 debug(
"or.b\t#%i,@(r0,gbr)\n", (uint8_t)lo8);
1279 debug(
"UNIMPLEMENTED hi4=0x%x,0x%x\n", hi4, r8);
1282 debug(
"mov\t#%i,r%i\n", (int8_t)lo8, r8);
1286 debug(
"fadd\t%sr%i,%sr%i\n",
1289 else if (lo4 == 0x1)
1290 debug(
"fsub\t%sr%i,%sr%i\n",
1293 else if (lo4 == 0x2)
1294 debug(
"fmul\t%sr%i,%sr%i\n",
1297 else if (lo4 == 0x3)
1298 debug(
"fdiv\t%sr%i,%sr%i\n",
1301 else if (lo4 == 0x4)
1302 debug(
"fcmp/eq\t%sr%i,%sr%i\n",
1305 else if (lo4 == 0x5)
1306 debug(
"fcmp/gt\t%sr%i,%sr%i\n",
1309 else if (lo4 == 0x6) {
1310 const char *n =
"fr";
1312 n = (r8 & 1)?
"xd" :
"dr";
1315 debug(
"fmov\t@(r0,r%i),%s%i\n", r4, n, r8);
1316 }
else if (lo4 == 0x7) {
1317 const char *n =
"fr";
1319 n = (r4 & 1)?
"xd" :
"dr";
1322 debug(
"fmov\t%s%i,@(r0,r%i)\n", n, r4, r8);
1323 }
else if (lo4 == 0x8) {
1324 const char *n =
"fr";
1326 n = (r8 & 1)?
"xd" :
"dr";
1329 debug(
"fmov\t@r%i,%s%i\n", r4, n, r8);
1330 }
else if (lo4 == 0x9) {
1331 const char *n =
"fr";
1333 n = (r8 & 1)?
"xd" :
"dr";
1336 debug(
"fmov\t@r%i+,%s%i\n", r4, n, r8);
1337 }
else if (lo4 == 0xa) {
1338 const char *n =
"fr";
1340 n = (r4 & 1)?
"xd" :
"dr";
1343 debug(
"fmov\t%s%i,@r%i\n", n, r4, r8);
1344 }
else if (lo4 == 0xb) {
1345 const char *n =
"fr";
1347 n = (r4 & 1)?
"xd" :
"dr";
1350 debug(
"fmov\t%s%i,@-r%i\n", n, r4, r8);
1351 }
else if (lo4 == 0xc) {
1352 const char *n1 =
"fr", *n2 =
"fr";
1354 n1 = (r4 & 1)?
"xd" :
"dr";
1355 n2 = (r8 & 1)?
"xd" :
"dr";
1358 debug(
"fmov\t%s%i,%s%i\n", n1, r4, n2, r8);
1359 }
else if (lo8 == 0x0d)
1360 debug(
"fsts\tfpul,fr%i\n", r8);
1361 else if (lo8 == 0x1d)
1362 debug(
"flds\tfr%i,fpul\n", r8);
1363 else if (lo8 == 0x2d)
1364 debug(
"float\tfpul,%sr%i\n",
1366 else if (lo8 == 0x3d)
1367 debug(
"ftrc\t%sr%i,fpul\n",
1369 else if (lo8 == 0x4d)
1370 debug(
"fneg\t%sr%i\n",
1372 else if (lo8 == 0x5d)
1373 debug(
"fabs\t%sr%i\n",
1375 else if (lo8 == 0x6d)
1376 debug(
"fsqrt\t%sr%i\n",
1378 else if (lo8 == 0x7d)
1379 debug(
"fsrra\tfr%i\n", r8);
1380 else if (lo8 == 0x8d)
1381 debug(
"fldi0\tfr%i\n", r8);
1382 else if (lo8 == 0x9d)
1383 debug(
"fldi1\tfr%i\n", r8);
1384 else if (lo8 == 0xad)
1385 debug(
"fcnvsd\tfpul,dr%i\n", r8);
1386 else if (lo8 == 0xbd)
1387 debug(
"fcnvds\tdr%i,fpul\n", r8);
1388 else if (lo8 == 0xed)
1389 debug(
"fipr\tfv%i,fv%i\n", (r8 & 3) << 2, r8 & 0xc);
1390 else if ((iword & 0x01ff) == 0x00fd)
1391 debug(
"fsca\tfpul,dr%i\n", r8);
1392 else if (iword == 0xf3fd)
1394 else if (iword == 0xfbfd)
1396 else if ((iword & 0xf3ff) == 0xf1fd)
1397 debug(
"ftrv\txmtrx,fv%i\n", r8 & 0xc);
1398 else if (lo4 == 0xe)
1399 debug(
"fmac\tfr0,fr%i,fr%i\n", r4, r8);
1401 debug(
"UNIMPLEMENTED hi4=0x%x,0x%x\n", hi4, lo8);
1403 default:
debug(
"UNIMPLEMENTED hi4=0x%x\n", hi4);
1406 return sizeof(iword);
int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
void sh3_cpu_interrupt_deassert(struct interrupt *interrupt)
void(* interrupt_deassert)(struct interrupt *)
struct symbol_context symbol_context
#define CPU_SETTINGS_ADD_REGISTER32(name, var)
#define SH_N_UTLB_ENTRIES
void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr)
void sh_cpu_dumpinfo(struct cpu *cpu)
int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
void sh_cpu_list_available_types(void)
char * get_symbol_name(struct symbol_context *, uint64_t addr, uint64_t *offset)
uint32_t utlb_hi[SH_N_UTLB_ENTRIES]
void sh_cpu_interrupt_deassert(struct interrupt *interrupt)
addr & if(addr >=0x24 &&page !=NULL)
void sh_cpu_tlbdump(struct machine *m, int x, int rawflag)
uint32_t r_bank[SH_N_GPRS_BANKED]
int(* instruction_has_delayslot)(struct cpu *cpu, unsigned char *ib)
void(* update_translation_table)(struct cpu *, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
#define EXPEVT_TLB_MISS_ST
#define CPU_SETTINGS_ADD_REGISTER64(name, var)
void(* invalidate_code_translation)(struct cpu *, uint64_t paddr, int flags)
#define SH_SR_IMASK_SHIFT
void COMBINE() strlen(struct cpu *cpu, struct arm_instr_call *ic, int low_addr)
void fatal(const char *fmt,...)
#define EXPEVT_TLB_MISS_LD
void * device_add(struct machine *machine, const char *name_and_params)
#define SH_N_ITLB_ENTRIES
#define SH4_PTEH_VPN_MASK
#define EXPEVT_TLB_PROT_LD
uint32_t itlb_hi[SH_N_ITLB_ENTRIES]
void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)
void sh_update_sr(struct cpu *cpu, uint32_t new_sr)
void sh_cpu_interrupt_assert(struct interrupt *interrupt)
#define SH_INTEVT_TMU2_TUNI2
int sh_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, int running, uint64_t dumpaddr)
int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr64, uint64_t *return_paddr, int flags)
int(* translate_v2p)(struct cpu *, uint64_t vaddr, uint64_t *return_paddr, int flags)
void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
struct pci_data * pcic_pcibus
#define EMUL_LITTLE_ENDIAN
#define EXPEVT_TLB_PROT_ST
struct sh_cpu_type_def cpu_type
#define SH_INTEVT_TMU1_TUNI1
void sh_update_interrupt_priorities(struct cpu *cpu)
int sh_run_instr(struct cpu *cpu)
#define EXPEVT_RESET_POWER
uint32_t utlb_lo[SH_N_UTLB_ENTRIES]
#define SH_INTEVT_TMU0_TUNI0
int(* run_instr)(struct cpu *cpu)
void sh_update_fpscr(struct cpu *cpu, uint32_t new_fpscr)
uint8_t int_prio_and_pending[0x1000/0x20]
void sh_pc_to_pointers(struct cpu *)
void(* interrupt_assert)(struct interrupt *)
void interrupt_handler_register(struct interrupt *templ)
#define EXPEVT_RESET_MANUAL
void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
uint32_t itlb_lo[SH_N_ITLB_ENTRIES]
#define SH4_INTEVT_SCIF_TXI
#define EXCEPTION_IN_DELAY_SLOT
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
void sh_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
#define SH4_INTEVT_SCIF_ERI
void sh3_cpu_interrupt_assert(struct interrupt *interrupt)
int sh_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, int cpu_id, char *cpu_type_name)
#define EXPEVT_FPU_DISABLE
Generated on Tue Mar 24 2020 14:04:48 for GXemul by
1.8.17