cpu_mips.cc Source File
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34 #include <sys/types.h>
38 #include "../../config.h"
57 static const char *hi6_names[] =
HI6_NAMES;
62 static const char *mmi_names[] =
MMI_NAMES;
73 #define DYNTRANS_DUALMODE_32
74 #define DYNTRANS_DELAYSLOT
90 int cpu_id,
char *cpu_type_name)
92 int i, found, j, tags_size, n_cache_lines, size_per_cache_line;
94 int64_t secondary_cache_size;
100 while (i >= 0 && cpu_type_defs[i].
name != NULL) {
101 if (strcasecmp(cpu_type_defs[i].
name, cpu_type_name) == 0) {
213 size_per_cache_line = 32;
223 tags_size = n_cache_lines * size_per_cache_line;
232 for (j=0; j<n_cache_lines; j++) {
251 secondary_cache_size = 0;
257 debug(
" (I+D = %i+%i KB",
261 if (secondary_cache_size != 0) {
263 if (secondary_cache_size >= 1048576)
265 (secondary_cache_size / 1048576));
268 (secondary_cache_size / 1024));
275 for (i=2; i<8; i++) {
279 memset(&templ, 0,
sizeof(templ));
356 debug(
"\n%i-bit %s-endian (MIPS",
361 case 1:
debug(
" ISA I");
break;
362 case 2:
debug(
" ISA II");
break;
363 case 3:
debug(
" ISA III");
break;
364 case 4:
debug(
" ISA IV");
break;
365 case 5:
debug(
" ISA V");
break;
386 debug(
", direct-mapped");
397 debug(
", direct-mapped");
402 int kb = (1 << ct->
scache) / 1024;
403 debug(
"L2 cache: %i %s",
404 kb >= 1024? kb / 1024 : kb, kb >= 1024?
"MB":
"KB");
410 debug(
", direct-mapped");
429 while (cpu_type_defs[i].
name != NULL) {
431 for (j=10 -
strlen(cpu_type_defs[i].
name); j>0; j--)
434 if ((i % 6) == 0 || cpu_type_defs[i].
name == NULL)
447 uint32_t iword = *((uint32_t *)&ib[0]);
454 switch (iword >> 26) {
456 switch (iword & 0x3f) {
463 switch ((iword >> 16) & 0x1f) {
507 for (i=0; i<m->
ncpus; i++) {
511 if (x >= 0 && i != x)
515 printf(
"cpu%i: (", i);
518 printf(
"index=0x%08x random=0x%08x",
522 printf(
"index=0x%016" PRIx64
523 " random=0x%016" PRIx64,
528 printf(
" wired=0x%" PRIx64,
534 nr_of_tlb_entries; j++) {
537 printf(
" %02x: hi=0x%08" PRIx32
" lo=0x%08"
539 (uint32_t) cop0->
tlbs[j].
hi,
542 printf(
" %02x: hi=0x%08" PRIx32
" mask=0x"
543 "%08" PRIx32
" lo0=0x%08" PRIx32
544 " lo1=0x%08" PRIx32
"\n", j,
545 (uint32_t) cop0->
tlbs[j].
hi,
550 printf(
" %02x: hi=0x%016" PRIx64
" mask="
551 "0x%016" PRIx64
" lo0=0x%016" PRIx64
552 " lo1=0x%016" PRIx64
"\n", j,
553 (uint64_t) cop0->
tlbs[j].
hi,
564 for (i=0; i<m->
ncpus; i++) {
568 if (x >= 0 && i != x)
575 printf(
"cpu%i: (", i);
578 case 2: printf(
"index=0x%x random=0x%x",
584 default:printf(
"index=0x%x random=0x%x",
587 printf(
" wired=0x%" PRIx64,
594 nr_of_tlb_entries; j++) {
595 uint64_t hi = cop0->
tlbs[j].
hi;
596 uint64_t lo0 = cop0->
tlbs[j].
lo0;
597 uint64_t lo1 = cop0->
tlbs[j].
lo1;
601 mask |= (1 << (pageshift+1)) - 1;
604 printf(
" %02x: ", j);
609 printf(
"(invalid)\n");
612 printf(
"vaddr=0x%08x ",
615 printf(
"(global), ");
617 printf(
"(asid %02x),", (
int) ((hi &
620 printf(
" paddr=0x%08x ",
630 printf(
"vaddr=0x%08" PRIx32
" ",
631 (uint32_t) (hi & ~mask));
634 printf(
"vaddr=%016" PRIx64
" ",
635 (uint64_t) (hi & ~mask));
638 printf(
"(global): ");
640 printf(
"(asid %02x):",
646 printf(
" p0=(invalid) ");
651 paddr &= ~(mask >> 1);
652 printf(
" p0=0x%09" PRIx64
" ",
658 printf(
" p1=(invalid) ");
663 paddr &= ~(mask >> 1);
664 printf(
" p1=0x%09" PRIx64
" ",
670 psize = (mask + 1) >> 1;
672 if (psize >= 1024 && psize <= 256*1024)
673 printf(
" (%iKB)", (
int) (psize >> 10));
674 else if (psize >= 1024*1024 && psize <=
676 printf(
" (%iMB)", (
int) (psize >> 20));
702 int running, uint64_t dumpaddr)
704 int hi6, special6, regimm5, sub;
705 int rt, rd, rs, sa, imm, copz, cache_op, which_cache, showtag;
706 uint64_t
addr, offset;
708 unsigned char instr[4];
714 if ((dumpaddr & 3) != 0)
715 printf(
"WARNING: Unaligned address!\n");
719 if (
symbol != NULL && offset==0)
726 debug(
"%08" PRIx32, (uint32_t)dumpaddr);
728 debug(
"%016" PRIx64, (uint64_t)dumpaddr);
730 memcpy(
instr, originstr,
sizeof(uint32_t));
743 debug(
": %02x%02x%02x%02x",
755 hi6 = (
instr[3] >> 2) & 0x3f;
759 special6 =
instr[0] & 0x3f;
770 sub = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
772 rd = (
instr[1] >> 3) & 31;
773 sa = ((
instr[1] & 7) << 2) + ((
instr[0] >> 6) & 3);
783 debug(
"nop (weird, sa=%i)", sa);
789 debug(
"%s\t%s,", special_names[special6],
791 debug(
"%s,%i", regnames[rt], sa);
795 special_rot_names[special6],
797 debug(
"%s,%i", regnames[rt], sa);
799 default:
debug(
"UNIMPLEMENTED special, sub=0x%02x\n",
809 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
811 rd = (
instr[1] >> 3) & 31;
812 sub = ((
instr[1] & 7) << 2) + ((
instr[0] >> 6) & 3);
816 debug(
"%s\t%s", special_names[special6],
818 debug(
",%s", regnames[rt]);
819 debug(
",%s", regnames[rs]);
822 debug(
"%s\t%s", special_rot_names[special6],
824 debug(
",%s", regnames[rt]);
825 debug(
",%s", regnames[rs]);
827 default:
debug(
"UNIMPLEMENTED special, sub=0x%02x\n",
832 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
837 (
instr[1] & 0x04) ?
".hb" :
"",
839 if (running &&
symbol != NULL)
843 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
844 rd = (
instr[1] >> 3) & 31;
849 (
instr[1] & 0x04) ?
".hb" :
"",
851 debug(
",%s", regnames[rs]);
852 if (running &&
symbol != NULL)
857 rd = (
instr[1] >> 3) & 31;
858 debug(
"%s\t%s", special_names[special6], regnames[rd]);
862 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
863 debug(
"%s\t%s", special_names[special6], regnames[rs]);
881 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
883 rd = (
instr[1] >> 3) & 31;
888 debug(
"move\t%s", regnames[rd]);
889 debug(
",%s", regnames[rs]);
894 debug(
"move\t%s", regnames[rd]);
895 debug(
",%s", regnames[rt]);
897 debug(
"%s\t%s", special_names[special6],
899 debug(
",%s", regnames[rs]);
900 debug(
",%s", regnames[rt]);
911 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
913 rd = (
instr[1] >> 3) & 31;
914 debug(
"%s\t", special_names[special6]);
919 debug(
"%s,", regnames[rd]);
921 debug(
"WEIRD_R5900_RD,");
923 debug(
"WEIRD_RD_NONZERO,");
926 debug(
"%s", regnames[rs]);
927 debug(
",%s", regnames[rt]);
935 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
938 debug(
"%s\t", special_names[special6]);
939 debug(
"%s", regnames[rs]);
940 debug(
",%s", regnames[rt]);
945 imm = ((
instr[1] & 7) << 2) + (
instr[0] >> 6);
946 debug(
"sync\t0x%02x", imm);
952 debug(
"syscall\t0x%05x", imm);
960 debug(
"break\t0x%05x", imm);
966 rd = (
instr[1] >> 3) & 31;
967 debug(
"mfsa\t%s", regnames[rd]);
969 debug(
"unimplemented special 0x28");
974 rs = ((
instr[3] & 3) << 3) +
975 ((
instr[2] >> 5) & 7);
976 debug(
"mtsa\t%s", regnames[rs]);
978 debug(
"unimplemented special 0x29");
982 debug(
"%s\t= UNIMPLEMENTED", special_names[special6]);
993 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
998 addr = (dumpaddr + 4) + (imm << 2);
1004 debug(
"%s\t", hi6_names[hi6]);
1010 debug(
"%s,", regnames[rt]);
1012 debug(
"%s,", regnames[rs]);
1034 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
1039 debug(
"%s\t%s,", hi6_names[hi6], regnames[rt]);
1040 debug(
"%s,", regnames[rs]);
1042 debug(
"0x%04x", imm & 0xffff);
1049 debug(
"lui\t%s,0x%x", regnames[rt], imm);
1088 debug(
"mdmx\t(UNIMPLEMENTED)");
1093 int msbd, lsb, sub10;
1094 special6 =
instr[0] & 0x3f;
1095 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
1097 rd = msbd = (
instr[1] >> 3) & 31;
1098 lsb = ((
instr[1] & 7) << 2) | (
instr[0] >> 6);
1099 sub10 = (rs << 5) | lsb;
1107 debug(
"%s", special3_names[special6]);
1112 debug(
"\t%s", regnames[rt]);
1113 debug(
",%s", regnames[rs]);
1114 debug(
",%i,%i", lsb, msbd + 1);
1121 debug(
"%s", special3_names[special6]);
1129 debug(
"\t%s", regnames[rt]);
1130 debug(
",%s", regnames[rs]);
1131 debug(
",%i,%i", lsb, msbd + 1);
1144 debug(
"\t%s", regnames[rd]);
1145 debug(
",%s", regnames[rt]);
1147 default:
debug(
"%s", special3_names[special6]);
1148 debug(
"\t(UNIMPLEMENTED)");
1160 debug(
"\t%s", regnames[rd]);
1161 debug(
",%s", regnames[rt]);
1163 default:
debug(
"%s", special3_names[special6]);
1164 debug(
"\t(UNIMPLEMENTED)");
1169 debug(
"%s", special3_names[special6]);
1170 debug(
"\t%s", regnames[rt]);
1171 debug(
",hwr%i", rd);
1174 default:
debug(
"%s", special3_names[special6]);
1175 debug(
"\t(UNIMPLEMENTED)");
1180 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
1191 debug(
"pref\t0x%x,%i(%s)",
1192 rt, imm, regnames[rs]);
1195 debug(
"\t[0x%016" PRIx64
" = %s]",
1204 debug(
"%s\t", hi6_names[hi6]);
1212 debug(
"%s", regnames[rt]);
1214 debug(
",%i(%s)", imm, regnames[rs]);
1220 debug(
"0x%08" PRIx32,
1223 debug(
"0x%016" PRIx64,
1239 imm = (((
instr[3] & 3) << 24) + (
instr[2] << 16) +
1241 addr = (dumpaddr + 4) & ~((1 << 28) - 1);
1245 debug(
"%s\t0x", hi6_names[hi6]);
1260 imm &= ((1 << 26) - 1);
1265 return sizeof(instrword);
1268 rt = ((
instr[3] & 3) << 3) + (
instr[2] >> 5);
1269 copz =
instr[2] & 31;
1271 cache_op = copz >> 2;
1272 which_cache = copz & 3;
1274 debug(
"cache\t0x%02x,0x%04x(%s)", copz, imm, regnames[rt]);
1275 if (which_cache==0)
debug(
" [ primary I-cache");
1276 if (which_cache==1)
debug(
" [ primary D-cache");
1277 if (which_cache==2)
debug(
" [ secondary I-cache");
1278 if (which_cache==3)
debug(
" [ secondary D-cache");
1280 if (cache_op==0)
debug(
"index invalidate");
1281 if (cache_op==1)
debug(
"index load tag");
1282 if (cache_op==2)
debug(
"index store tag"), showtag=1;
1283 if (cache_op==3)
debug(
"create dirty exclusive");
1284 if (cache_op==4)
debug(
"hit invalidate");
1285 if (cache_op==5)
debug(
"fill OR hit writeback invalidate");
1286 if (cache_op==6)
debug(
"hit writeback");
1287 if (cache_op==7)
debug(
"hit set virtual");
1289 debug(
", addr 0x%016" PRIx64,
1292 debug(
", taghi=%08lx lo=%08lx",
1299 special6 =
instr[0] & 0x3f;
1300 instrword = (
instr[3] << 24) + (
instr[2] << 16) +
1302 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
1304 rd = (
instr[1] >> 3) & 31;
1307 int c790mmifunc = (instrword >> 6) & 0x1f;
1310 debug(
"%s\t", mmi_names[special6]);
1317 debug(
"%s,", regnames[rd]);
1319 debug(
"%s,%s", regnames[rs], regnames[rt]);
1323 debug(
"%s\t", mmi0_names[c790mmifunc]);
1324 switch (c790mmifunc) {
1334 debug(
"%s,%s,%s", regnames[rd],
1335 regnames[rs], regnames[rt]);
1338 default:
debug(
"(UNIMPLEMENTED)");
1343 debug(
"%s\t", mmi1_names[c790mmifunc]);
1344 switch (c790mmifunc) {
1351 debug(
"%s,%s,%s", regnames[rd],
1352 regnames[rs], regnames[rt]);
1355 default:
debug(
"(UNIMPLEMENTED)");
1360 debug(
"%s\t", mmi2_names[c790mmifunc]);
1361 switch (c790mmifunc) {
1365 debug(
"%s", regnames[rd]);
1378 debug(
"%s,%s,%s", regnames[rd],
1379 regnames[rs], regnames[rt]);
1382 default:
debug(
"(UNIMPLEMENTED)");
1387 debug(
"%s\t", mmi3_names[c790mmifunc]);
1388 switch (c790mmifunc) {
1392 debug(
"%s", regnames[rs]);
1401 debug(
"%s,%s,%s", regnames[rd],
1402 regnames[rs], regnames[rt]);
1405 default:
debug(
"(UNIMPLEMENTED)");
1409 default:
debug(
"(UNIMPLEMENTED)");
1415 debug(
"%s\t", special2_names[special6]);
1424 debug(
"WEIRD_NONZERO_RD(%s),",
1427 debug(
"%s,%s", regnames[rs], regnames[rt]);
1432 debug(
"%s,%s,%s", regnames[rd],
1433 regnames[rs], regnames[rt]);
1440 debug(
"%s,%s", regnames[rd], regnames[rs]);
1444 debug(
"(UNIMPLEMENTED)");
1449 regimm5 =
instr[2] & 0x1f;
1450 rs = ((
instr[3] & 3) << 3) + ((
instr[2] >> 5) & 7);
1465 debug(
"%s\t%s,", regimm_names[regimm5], regnames[rs]);
1467 addr = (dumpaddr + 4) + (imm << 2);
1472 debug(
"0x%016" PRIx64, (uint64_t)
addr);
1476 debug(
"%s\t%i(%s)", regimm_names[regimm5],
1481 debug(
"unimplemented regimm5 = 0x%02x", regimm5);
1485 debug(
"unimplemented hi6 = 0x%02x", hi6);
1490 return sizeof(instrword);
1504 int coprocnr, i, bits32;
1517 debug(
"cpu%i: pc = %08" PRIx32,
1520 debug(
"cpu%i: pc=%016" PRIx64,
1523 debug(
"cpu%i: pc = 0x%016" PRIx64,
1530 debug(
"cpu%i: hi = %08" PRIx32
" lo = %08" PRIx32
"\n",
1534 debug(
"cpu%i: hi=%016" PRIx64
"%016" PRIx64
" lo="
1535 "%016" PRIx64
"%016" PRIx64
"\n",
cpu->
cpu_id,
1539 debug(
"cpu%i: hi = 0x%016" PRIx64
" lo = 0x%016"
1548 for (i=0; i<32; i++) {
1549 int r = (i >> 1) + ((i & 1) << 4);
1556 debug(
" %3s=%016" PRIx64
"%016" PRIx64,
1557 regnames[r], (uint64_t)
1563 }
else if (bits32) {
1565 for (i=0; i<32; i++) {
1571 debug(
" %3s = %08" PRIx32, regnames[i],
1578 for (i=0; i<32; i++) {
1579 int r = (i >> 1) + ((i & 1) << 4);
1585 debug(
" %3s = 0x%016" PRIx64,
1594 for (coprocnr=0; coprocnr<4; coprocnr++) {
1600 if (!(coprocs & (1<<coprocnr)))
1603 debug(
"cpu%i: no coprocessor %i\n",
1609 for (i=0; i<32; i++) {
1615 debug(
" %8s", cop0_names[i]);
1617 debug(
" c%i,%02i", coprocnr, i);
1621 coproc[coprocnr]->reg[i]);
1630 debug(
" = 0x%016" PRIx64, (uint64_t)
1635 if ((i & nm1) == nm1)
1646 debug(
"config_select1 = 0x");
1651 debug(
"%016" PRIx64,
1657 if (coprocnr == 1) {
1658 for (i=0; i<32; i++)
1661 printf(
"cpu%i: fcr0 (fcir) = 0x%08x\n",
1663 coproc[coprocnr]->fcr[i]);
1666 printf(
"cpu%i: fcr25 (fccr) = 0x%08x\n",
1668 coproc[coprocnr]->fcr[i]);
1671 printf(
"cpu%i: fcr31 (fcsr) = 0x%08x\n",
1673 coproc[coprocnr]->fcr[i]);
1680 printf(
"cpu%i: Read-Modify-Write in progress, address "
1720 int coproc_nr, uint64_t vaddr_vpn2,
int vaddr_asid,
int x_64)
1733 cpu->
pc +=
sizeof(uint32_t);
1746 debug(
"exception %s%s",
1747 exception_names[exccode], tlb?
" <tlb>" :
"");
1752 debug(
" cause_im=0x%02x", (
int)
1759 for (x=0; x<4; x++) {
1763 if (d > -256 && d < 256) {
1764 debug(
" a%i=%i", x, (
int)d);
1767 debug(
" a%i=\"%s\"", x,
1769 d, strbuf,
sizeof(strbuf)));
1772 debug(
" a%i=0x%" PRIx32, x,
1775 debug(
" a%i=0x%" PRIx64, x,
1782 debug(
" coproc_nr=%i", coproc_nr);
1787 debug(
" vaddr=0x%08x", (
int)vaddr);
1789 debug(
" vaddr=0x%016" PRIx64, (uint64_t)vaddr);
1793 debug(
" pc=0x%08" PRIx32
" ", (uint32_t)
cpu->
pc);
1795 debug(
" pc=0x%016" PRIx64
" ", (uint64_t)
cpu->
pc);
1803 if (tlb && vaddr < 0x1000) {
1810 fatal(
"warning: LOW reference: vaddr=");
1812 fatal(
"0x%08" PRIx32, (uint32_t) vaddr);
1814 fatal(
"0x%016" PRIx64, (uint64_t) vaddr);
1815 fatal(
", exception %s, pc=", exception_names[exccode]);
1824 if (exc_model ==
EXC3K)
1842 if (exc_model ==
EXC3K) {
1916 base = 0xffffffffbfc00200ULL;
1918 base = 0xffffffff80000000ULL;
1920 switch (exc_model) {
1923 if (tlb && !(vaddr & 0x80000000ULL) &&
1925 cpu->
pc = base + 0x000;
1927 cpu->
pc = base + 0x080;
1944 cpu->
pc = base + 0x080;
1946 cpu->
pc = base + 0x000;
1950 cpu->
pc = base + 0x200;
1952 cpu->
pc = base + 0x180;
1956 if (exc_model ==
EXC3K) {
uint64_t gpr_quadhi[N_MIPS_GPRS]
struct mips_cpu_type_def cpu_type
uint64_t reg[N_MIPS_COPROC_REGS]
struct mips_coproc * coproc[N_MIPS_COPROCS]
#define XCONTEXT_BADVPN2_SHIFT
#define INTERRUPT_CONNECT(name, istruct)
void(* interrupt_deassert)(struct interrupt *)
struct symbol_context symbol_context
int cache_secondary_linesize
#define CONTEXT_BADVPN2_SHIFT
char * get_symbol_name(struct symbol_context *, uint64_t addr, uint64_t *offset)
#define XCONTEXT_BADVPN2_MASK
#define CAUSE_EXCCODE_SHIFT
int mips32_run_instr(struct cpu *cpu)
#define N_MIPS_COPROC_REGS
void coproc_function(struct cpu *cpu, struct mips_coproc *cp, int cpnr, uint32_t function, int unassemble_only, int running)
void mips_cpu_list_available_types(void)
#define R2K3K_RANDOM_MASK
#define CAUSE_EXCCODE_MASK
int(* instruction_has_delayslot)(struct cpu *cpu, unsigned char *ib)
struct mips_coproc * mips_coproc_new(struct cpu *cpu, int coproc_nr)
int cache_picache_linesize
void(* update_translation_table)(struct cpu *, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
uint64_t cache_last_paddr[2]
#define R2K3K_CONTEXT_BADVPN_SHIFT
void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
#define ENTRYHI_VPN2_MASK_R10K
#define CPU_SETTINGS_ADD_REGISTER64(name, var)
#define R2K3K_CONTEXT_BADVPN_MASK
void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
#define DEFAULT_PCACHE_SIZE
void(* invalidate_code_translation)(struct cpu *, uint64_t paddr, int flags)
int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib)
int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
int mips_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine, int cpu_id, char *cpu_type_name)
void COMBINE() strlen(struct cpu *cpu, struct arm_instr_call *ic, int low_addr)
void fatal(const char *fmt,...)
void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page)
void mips_pc_to_pointers(struct cpu *)
#define R2K3K_CAUSE_EXCCODE_MASK
int mips_run_instr(struct cpu *cpu)
#define CACHE_INSTRUCTION
#define R2K3K_RANDOM_SHIFT
int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
#define ENTRYHI_VPN2_MASK
void mips32_pc_to_pointers(struct cpu *)
void(* invalidate_translation_caches)(struct cpu *, uint64_t paddr, int flags)
int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
int(* translate_v2p)(struct cpu *, uint64_t vaddr, uint64_t *return_paddr, int flags)
struct interrupt irq_compare
void mips_cpu_dumpinfo(struct cpu *cpu)
void mips_cpu_interrupt_deassert(struct interrupt *interrupt)
#define R2K3K_ENTRYHI_ASID_SHIFT
#define R2K3K_ENTRYHI_ASID_MASK
#define EMUL_LITTLE_ENDIAN
uint64_t cop0_config_select1
#define MIPS_CPU_TYPE_DEFS
int cache_pdcache_linesize
#define CONTEXT_BADVPN2_MASK_R4100
void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr, int coproc_nr, uint64_t vaddr_vpn2, int vaddr_asid, int x_64)
void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
int store_32bit_word(struct cpu *cpu, uint64_t addr, uint64_t data32)
#define R2K3K_INDEX_SHIFT
int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *originstr, int running, uint64_t dumpaddr)
#define CONTEXT_BADVPN2_MASK
#define INITIAL_STACK_POINTER
uint64_t gpr[N_MIPS_GPRS]
#define MIPS_REGISTER_NAMES
int(* run_instr)(struct cpu *cpu)
#define DEBUG_INDENTATION
int memory_points_to_string(struct cpu *cpu, struct memory *mem, uint64_t addr, int min_string_length)
void(* interrupt_assert)(struct interrupt *)
void interrupt_handler_register(struct interrupt *templ)
#define R2K3K_ENTRYHI_VPN_MASK
void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int)
#define R2K3K_ENTRYLO_PFN_MASK
void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int)
#define SPECIAL_ROT_NAMES
int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
#define EXCEPTION_IN_DELAY_SLOT
int(* memory_rw)(struct cpu *cpu, struct memory *mem, uint64_t vaddr, unsigned char *data, size_t len, int writeflag, int cache_flags)
void mips_cpu_tlbdump(struct machine *m, int x, int rawflag)
#define ENTRYLO_PFN_SHIFT
char * memory_conv_to_string(struct cpu *cpu, struct memory *mem, uint64_t addr, char *buf, int bufsize)
#define DEFAULT_PCACHE_LINESIZE
void mips_cpu_interrupt_assert(struct interrupt *interrupt)
void debug_indentation(int diff)
int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr, uint64_t *return_addr, int flags)
#define CHECK_ALLOCATION(ptr)
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