sh4_scifreg.h Source File
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3 #ifndef _SH3_SCIFREG_H_
4 #define _SH3_SCIFREG_H_
36 #define SH3_SCIF0_BASE 0xa4000150
37 #define SH3_SCIF1_BASE 0xa4000140
39 #define SH4_SCIF_BASE 0xffe80000
54 #define SHREG_SCSMR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_SMR))
55 #define SHREG_SCBRR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_BRR))
56 #define SHREG_SCSCR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_SCR))
57 #define SHREG_SCFTDR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_FTDR))
58 #define SHREG_SCSSR2 (*(volatile uint16_t *)(SH3_SCIF0_BASE + SCIF_SSR))
59 #define SHREG_SCFRDR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_FRDR))
60 #define SHREG_SCFCR2 (*(volatile uint8_t *)(SH3_SCIF0_BASE + SCIF_FCR))
61 #define SHREG_SCFDR2 (*(volatile uint16_t *)(SH3_SCIF0_BASE + SCIF_FDR))
70 #define SCIF_FTDR 0x0c
72 #define SCIF_FRDR 0x14
76 #define SCIF_SPTR 0x20
79 #define SHREG_SCSMR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SMR))
80 #define SHREG_SCBRR2 (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_BRR))
81 #define SHREG_SCSCR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SCR))
82 #define SHREG_SCFTDR2 (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_FTDR))
83 #define SHREG_SCSSR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SSR))
84 #define SHREG_SCFRDR2 (*(volatile uint8_t *)(SH4_SCIF_BASE + SCIF_FRDR))
85 #define SHREG_SCFCR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FCR))
86 #define SHREG_SCFDR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_FDR))
88 #define SHREG_SCSPTR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_SPTR))
89 #define SHREG_SCLSR2 (*(volatile uint16_t *)(SH4_SCIF_BASE + SCIF_LSR))
92 #define SHREG_SCSFDR2 SHREG_SCFTDR2
93 #define SHREG_SCFSR2 SHREG_SCSSR2
95 #define SCSPTR2_RTSIO 0x0080
96 #define SCSPTR2_RTSDT 0x0040
97 #define SCSPTR2_CTSIO 0x0020
98 #define SCSPTR2_CTSDT 0x0010
99 #define SCSPTR2_SCKIO 0x0008
100 #define SCSPTR2_SCKDT 0x0004
101 #define SCSPTR2_SPB2IO 0x0002
102 #define SCSPTR2_SPB2DT 0x0001
104 #define SCLSR2_ORER 0x0001
109 #define SCSMR2_CHR 0x40
110 #define SCSMR2_PE 0x20
111 #define SCSMR2_O 0x10
112 #define SCSMR2_STOP 0x08
113 #define SCSMR2_CKS1 0x02
114 #define SCSMR2_CKS0 0x01
117 #define SCSMR2_IRMOD 0x80
118 #define SCSMR2_ICK3 0x40
119 #define SCSMR2_ICK2 0x20
120 #define SCSMR2_ICK1 0x10
121 #define SCSMR2_ICK0 0x08
122 #define SCSMR2_PSEL 0x04
125 #define SCSCR2_TIE 0x80
126 #define SCSCR2_RIE 0x40
127 #define SCSCR2_TE 0x20
128 #define SCSCR2_RE 0x10
129 #define SCSCR2_CKE1 0x02
130 #define SCSCR2_CKE0 0x01
133 #define SCSSR2_ER 0x0080
134 #define SCSSR2_TEND 0x0040
135 #define SCSSR2_TDFE 0x0020
136 #define SCSSR2_BRK 0x0010
137 #define SCSSR2_FER 0x0008
138 #define SCSSR2_PER 0x0004
139 #define SCSSR2_RDF 0x0002
140 #define SCSSR2_DR 0x0001
143 #define SCFCR2_RTRG1 0x80
144 #define SCFCR2_RTRG0 0x40
145 #define SCFCR2_TTRG1 0x20
146 #define SCFCR2_TTRG0 0x10
147 #define SCFCR2_MCE 0x08
148 #define SCFCR2_TFRST 0x04
149 #define SCFCR2_RFRST 0x02
150 #define SCFCR2_LOOP 0x01
152 #define FIFO_RCV_TRIGGER_1 0x00
153 #define FIFO_RCV_TRIGGER_4 0x40
154 #define FIFO_RCV_TRIGGER_8 0x80
155 #define FIFO_RCV_TRIGGER_14 0xc0
157 #define FIFO_XMT_TRIGGER_8 0x00
158 #define FIFO_XMT_TRIGGER_4 0x10
159 #define FIFO_XMT_TRIGGER_2 0x20
160 #define FIFO_XMT_TRIGGER_1 0x30
163 #define SCFDR2_TXCNT 0xff00
164 #define SCFDR2_RECVCNT 0x00ff
165 #define SCFDR2_TXF_FULL 0x1000
166 #define SCFDR2_RXF_EPTY 0x0000
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