mb86960reg.h File Reference

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Macros
mb86960reg.h File Reference

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Macros

#define MB8696X_NREGS   32
 
#define FE_DLCR0   0
 
#define FE_DLCR1   1
 
#define FE_DLCR2   2
 
#define FE_DLCR3   3
 
#define FE_DLCR4   4
 
#define FE_DLCR5   5
 
#define FE_DLCR6   6
 
#define FE_DLCR7   7
 
#define FE_DLCR8   8
 
#define FE_DLCR9   9
 
#define FE_DLCR10   10
 
#define FE_DLCR11   11
 
#define FE_DLCR12   12
 
#define FE_DLCR13   13
 
#define FE_DLCR14   14
 
#define FE_DLCR15   15
 
#define FE_MAR8   8
 
#define FE_MAR9   9
 
#define FE_MAR10   10
 
#define FE_MAR11   11
 
#define FE_MAR12   12
 
#define FE_MAR13   13
 
#define FE_MAR14   14
 
#define FE_MAR15   15
 
#define FE_BMPR8   8
 
#define FE_BMPR9   9
 
#define FE_BMPR10   10
 
#define FE_BMPR11   11
 
#define FE_BMPR12   12
 
#define FE_BMPR13   13
 
#define FE_BMPR14   14
 
#define FE_BMPR15   15
 
#define FE_BMPR16   16
 
#define FE_BMPR17   17
 
#define FE_BMPR18   18
 
#define FE_BMPR19   19
 
#define FE_RESET   31
 
#define FE_D0_BUSERR   0x01 /* Bus write error */
 
#define FE_D0_COLL16   0x02 /* Collision limit (16) encountered */
 
#define FE_D0_COLLID   0x04 /* Collision on last transmission */
 
#define FE_D0_JABBER   0x08 /* Jabber */
 
#define FE_D0_CRLOST   0x10 /* Carrier lost on last transmission */
 
#define FE_D0_PKTRCD   0x20 /* No collision on last transmission */
 
#define FE_D0_NETBSY   0x40 /* Network Busy (Carrier Detected) */
 
#define FE_D0_TXDONE   0x80 /* Transmission complete */
 
#define FE_D1_OVRFLO   0x01 /* Receiver buffer overflow */
 
#define FE_D1_CRCERR   0x02 /* CRC error on last packet */
 
#define FE_D1_ALGERR   0x04 /* Alignment error on last packet */
 
#define FE_D1_SRTPKT   0x08 /* Short (RUNT) packet is received */
 
#define FE_D1_RMTRST   0x10 /* Remote reset packet (type = 0x0900) */
 
#define FE_D1_DMAEOP   0x20 /* Host asserted End of DMA OPeration */
 
#define FE_D1_BUSERR   0x40 /* Bus read error */
 
#define FE_D1_PKTRDY   0x80 /* Packet(s) ready on receive buffer */
 
#define FE_D1_ERRBITS   "\20\4SRTPKT\3ALGERR\2CRCERR\1OVRFLO"
 
#define FE_D2_BUSERR   FE_D0_BUSERR
 
#define FE_D2_COLL16   FE_D0_COLL16
 
#define FE_D2_COLLID   FE_D0_COLLID
 
#define FE_D2_JABBER   FE_D0_JABBER
 
#define FE_D2_TXDONE   FE_D0_TXDONE
 
#define FE_D2_RESERVED   0x70
 
#define FE_D3_OVRFLO   FE_D1_OVRFLO
 
#define FE_D3_CRCERR   FE_D1_CRCERR
 
#define FE_D3_ALGERR   FE_D1_ALGERR
 
#define FE_D3_SRTPKT   FE_D1_SRTPKT
 
#define FE_D3_RMTRST   FE_D1_RMTRST
 
#define FE_D3_DMAEOP   FE_D1_DMAEOP
 
#define FE_D3_BUSERR   FE_D1_BUSERR
 
#define FE_D3_PKTRDY   FE_D1_PKTRDY
 
#define FE_D4_DSC   0x01 /* Disable carrier sense on trans. */
 
#define FE_D4_LBC   0x02 /* Loop back test control */
 
#define FE_D4_CNTRL   0x04 /* - ??? */
 
#define FE_D4_TEST1   0x08 /* Test output #1 */
 
#define FE_D4_COL   0xF0 /* Collision counter */
 
#define FE_D4_LBC_ENABLE   0x00 /* Perform loop back test */
 
#define FE_D4_LBC_DISABLE   0x02 /* Normal operation */
 
#define FE_D4_COL_SHIFT   4
 
#define FE_D5_AFM0   0x01 /* Receive packets for other stations */
 
#define FE_D5_AFM1   0x02 /* Receive packets for this station */
 
#define FE_D5_RMTRST   0x04 /* Enable remote reset operation */
 
#define FE_D5_SRTPKT   0x08 /* Accept short (RUNT) packets */
 
#define FE_D5_SRTADR   0x10 /* Short (16 bits?) MAC address */
 
#define FE_D5_BADPKT   0x20 /* Accept packets with error */
 
#define FE_D5_BUFEMP   0x40 /* Receive buffer is empty */
 
#define FE_D5_TEST2   0x80 /* Test output #2 */
 
#define FE_D6_BUFSIZ   0x03 /* Size of NIC buffer SRAM */
 
#define FE_D6_TXBSIZ   0x0C /* Size (and config)of trans. buffer */
 
#define FE_D6_BBW   0x10 /* Buffer SRAM bus width */
 
#define FE_D6_SBW   0x20 /* System bus width */
 
#define FE_D6_SRAM   0x40 /* Buffer SRAM access time */
 
#define FE_D6_DLC   0x80 /* Disable DLC (receiver/transmitter) */
 
#define FE_D6_BUFSIZ_8KB   0x00 /* The board has 8KB SRAM */
 
#define FE_D6_BUFSIZ_16KB   0x01 /* The board has 16KB SRAM */
 
#define FE_D6_BUFSIZ_32KB   0x02 /* The board has 32KB SRAM */
 
#define FE_D6_BUFSIZ_64KB   0x03 /* The board has 64KB SRAM */
 
#define FE_D6_TXBSIZ_1x2KB   0x00 /* Single 2KB buffer for trans. */
 
#define FE_D6_TXBSIZ_2x2KB   0x04 /* Double 2KB buffers */
 
#define FE_D6_TXBSIZ_2x4KB   0x08 /* Double 4KB buffers */
 
#define FE_D6_TXBSIZ_2x8KB   0x0C /* Double 8KB buffers */
 
#define FE_D6_BBW_WORD   0x00 /* SRAM has 16 bit data line */
 
#define FE_D6_BBW_BYTE   0x10 /* SRAM has 8 bit data line */
 
#define FE_D6_SBW_WORD   0x00 /* Access with 16 bit (AT) bus */
 
#define FE_D6_SBW_BYTE   0x20 /* Access with 8 bit (XT) bus */
 
#define FE_D6_SRAM_150ns   0x00 /* The board has slow SRAM */
 
#define FE_D6_SRAM_100ns   0x40 /* The board has fast SRAM */
 
#define FE_D6_DLC_ENABLE   0x00 /* Normal operation */
 
#define FE_D6_DLC_DISABLE   0x80 /* Stop sending/receiving */
 
#define FE_D7_BYTSWP   0x01 /* Host byte order control */
 
#define FE_D7_EOPPOL   0x02 /* Polarity of DMA EOP signal */
 
#define FE_D7_RBS   0x0C /* Register bank select */
 
#define FE_D7_RDYPNS   0x10 /* Senses RDYPNSEL input signal */
 
#define FE_D7_POWER   0x20 /* Stand-by (power down) mode control */
 
#define FE_D7_ED   0xC0 /* Encoder/Decoder config (for MB86960) */
 
#define FE_D7_IDENT   0xC0 /* Chip identification */
 
#define FE_D7_BYTSWP_LH   0x00 /* DEC/Intel byte order */
 
#define FE_D7_BYTSWP_HL   0x01 /* IBM/Motorolla byte order */
 
#define FE_D7_RBS_DLCR   0x00 /* Select DLCR8-15 */
 
#define FE_D7_RBS_MAR   0x04 /* Select MAR8-15 */
 
#define FE_D7_RBS_BMPR   0x08 /* Select BMPR8-15 */
 
#define FE_D7_POWER_DOWN   0x00 /* Power down (stand-by) mode */
 
#define FE_D7_POWER_UP   0x20 /* Normal operation */
 
#define FE_D7_ED_NORMAL   0x00 /* Normal NICE */
 
#define FE_D7_ED_MON   0x40 /* NICE + Monitor */
 
#define FE_D7_ED_BYPASS   0x80 /* Encoder/Decorder Bypass */
 
#define FE_D7_ED_TEST   0xC0 /* Encoder/Decorder Test */
 
#define FE_D7_IDENT_86960   0x00 /* MB86960 (NICE) */
 
#define FE_D7_IDENT_86964   0x40 /* MB86964 */
 
#define FE_D7_IDENT_86967   0x80 /* MB86967 */
 
#define FE_D7_IDENT_86965   0xC0 /* MB86965 (EtherCoupler) */
 
#define FE_B10_START   0x80 /* Start transmitter */
 
#define FE_B10_COUNT   0x7F /* Packet count */
 
#define FE_B11_CTRL   0x01 /* Skip or resend errored packets */
 
#define FE_B11_MODE1   0x02 /* Restart transmitter after COLL16 */
 
#define FE_B11_MODE2   0x04 /* Automatic restart enable */
 
#define FE_B11_CTRL_RESEND   0x00 /* Re-send the collided packet */
 
#define FE_B11_CTRL_SKIP   0x01 /* Skip the collided packet */
 
#define FE_B12_TXDMA   0x01 /* Enable transmitter DMA */
 
#define FE_B12_RXDMA   0x02 /* Enable receiver DMA */
 
#define FE_B13_BSTCTL   0x03 /* DMA burst mode control */
 
#define FE_B13_TPTYPE   0x04 /* Twisted pair cable impedance */
 
#define FE_B13_PORT   0x18 /* Port (TP/AUI) selection */
 
#define FE_B13_LNKTST   0x20 /* Link test enable */
 
#define FE_B13_SQTHLD   0x40 /* Lower squelch threshold */
 
#define FE_B13_IOUNLK   0x80 /* Change I/O base address */
 
#define FE_B13_BSTCTL_1   0x00
 
#define FE_B13_BSTCTL_4   0x01
 
#define FE_B13_BSTCTL_8   0x02
 
#define FE_B13_BSTCLT_12   0x03
 
#define FE_B13_TPTYPE_UTP   0x00 /* Unshielded (standard) cable */
 
#define FE_B13_TPTYPE_STP   0x04 /* Shielded (IBM) cable */
 
#define FE_B13_PORT_AUTO   0x00 /* Auto detected */
 
#define FE_B13_PORT_TP   0x08 /* Force TP */
 
#define FE_B13_PORT_AUI   0x18 /* Force AUI */
 
#define FE_B14_FILTER   0x01 /* Filter out self-originated packets */
 
#define FE_B14_SQE   0x02 /* SQE interrupt enable */
 
#define FE_B14_SKIP   0x04 /* Skip a received packet */
 
#define FE_B14_RJAB   0x20 /* RJAB interrupt enable */
 
#define FE_B14_LLD   0x40 /* Local-link-down interrupt enable */
 
#define FE_B14_RLD   0x80 /* Remote-link-down interrupt enable */
 
#define FE_B15_SQE   FE_B14_SQE
 
#define FE_B15_RCVPOL   0x08 /* Reversed receive line polarity */
 
#define FE_B15_RMTPRT   0x10 /* ??? */
 
#define FE_B15_RAJB   FE_B14_RJAB
 
#define FE_B15_LLD   FE_B14_LLD
 
#define FE_B15_RLD   FE_B14_RLD
 
#define FE_B16_DOUT   0x04 /* EEPROM Data in (CPU to EEPROM) */
 
#define FE_B16_SELECT   0x20 /* EEPROM chip select */
 
#define FE_B16_CLOCK   0x40 /* EEPROM shift clock */
 
#define FE_B16_DIN   0x80 /* EEPROM data out (EEPROM to CPU) */
 
#define FE_B17_DATA   0x80 /* EEPROM data bit */
 
#define FE_B19_IRQ   0xC0
 
#define FE_B19_IRQ_SHIFT   6
 
#define FE_B19_ROM   0x38
 
#define FE_B19_ROM_SHIFT   3
 
#define FE_B19_ADDR   0x07
 
#define FE_B19_ADDR_SHIFT   0
 
#define FE_EEPROM_SIZE   32
 
#define FE_EEPROM_CONF   0x00
 
#define FE_EEPROM_DELAY()   DELAY(4)
 
#define FE_ATI_EEP_ADDR   0x08 /* Station address (0x08-0x0d) */
 
#define FE_ATI_EEP_MEDIA   0x18 /* Media type */
 
#define FE_ATI_EEP_MAGIC   0x19 /* XXX Magic */
 
#define FE_ATI_EEP_MODEL   0x1e /* Hardware type */
 
#define FE_ATI_MODEL_AT1700T   0x00
 
#define FE_ATI_MODEL_AT1700BT   0x01
 
#define FE_ATI_MODEL_AT1700FT   0x02
 
#define FE_ATI_MODEL_AT1700AT   0x03
 
#define FE_ATI_EEP_REVISION   0x1f /* Hardware revision */
 
#define FE_FILTER_LEN   8
 
#define FE_QUEUEING_MAX   127
 
#define FE_TXLEN_SIZE   2
 
#define FE_RXSTAT_GOODPKT   0x20
 
#define FE_RXSTAT_RMT0900   0x10
 
#define FE_RXSTAT_SHORTPKT   0x08
 
#define FE_RXSTAT_ALIGNERR   0x04
 
#define FE_RXSTAT_CRCERR   0x02
 
#define FE_MBH0   0x10 /* Master interrupt register */
 
#define FE_MBH_ENADDR   0x1A /* Mac address */
 
#define FE_MBH0_MASK   0x0D
 
#define FE_MBH0_INTR_ENABLE   0x10 /* Enable interrupts */
 

Macro Definition Documentation

◆ FE_ATI_EEP_ADDR

#define FE_ATI_EEP_ADDR   0x08 /* Station address (0x08-0x0d) */

Definition at line 328 of file mb86960reg.h.

◆ FE_ATI_EEP_MAGIC

#define FE_ATI_EEP_MAGIC   0x19 /* XXX Magic */

Definition at line 330 of file mb86960reg.h.

◆ FE_ATI_EEP_MEDIA

#define FE_ATI_EEP_MEDIA   0x18 /* Media type */

Definition at line 329 of file mb86960reg.h.

◆ FE_ATI_EEP_MODEL

#define FE_ATI_EEP_MODEL   0x1e /* Hardware type */

Definition at line 331 of file mb86960reg.h.

◆ FE_ATI_EEP_REVISION

#define FE_ATI_EEP_REVISION   0x1f /* Hardware revision */

Definition at line 336 of file mb86960reg.h.

◆ FE_ATI_MODEL_AT1700AT

#define FE_ATI_MODEL_AT1700AT   0x03

Definition at line 335 of file mb86960reg.h.

◆ FE_ATI_MODEL_AT1700BT

#define FE_ATI_MODEL_AT1700BT   0x01

Definition at line 333 of file mb86960reg.h.

◆ FE_ATI_MODEL_AT1700FT

#define FE_ATI_MODEL_AT1700FT   0x02

Definition at line 334 of file mb86960reg.h.

◆ FE_ATI_MODEL_AT1700T

#define FE_ATI_MODEL_AT1700T   0x00

Definition at line 332 of file mb86960reg.h.

◆ FE_B10_COUNT

#define FE_B10_COUNT   0x7F /* Packet count */

Definition at line 241 of file mb86960reg.h.

◆ FE_B10_START

#define FE_B10_START   0x80 /* Start transmitter */

Definition at line 240 of file mb86960reg.h.

◆ FE_B11_CTRL

#define FE_B11_CTRL   0x01 /* Skip or resend errored packets */

Definition at line 244 of file mb86960reg.h.

◆ FE_B11_CTRL_RESEND

#define FE_B11_CTRL_RESEND   0x00 /* Re-send the collided packet */

Definition at line 248 of file mb86960reg.h.

◆ FE_B11_CTRL_SKIP

#define FE_B11_CTRL_SKIP   0x01 /* Skip the collided packet */

Definition at line 249 of file mb86960reg.h.

◆ FE_B11_MODE1

#define FE_B11_MODE1   0x02 /* Restart transmitter after COLL16 */

Definition at line 245 of file mb86960reg.h.

◆ FE_B11_MODE2

#define FE_B11_MODE2   0x04 /* Automatic restart enable */

Definition at line 246 of file mb86960reg.h.

◆ FE_B12_RXDMA

#define FE_B12_RXDMA   0x02 /* Enable receiver DMA */

Definition at line 253 of file mb86960reg.h.

◆ FE_B12_TXDMA

#define FE_B12_TXDMA   0x01 /* Enable transmitter DMA */

Definition at line 252 of file mb86960reg.h.

◆ FE_B13_BSTCLT_12

#define FE_B13_BSTCLT_12   0x03

Definition at line 266 of file mb86960reg.h.

◆ FE_B13_BSTCTL

#define FE_B13_BSTCTL   0x03 /* DMA burst mode control */

Definition at line 256 of file mb86960reg.h.

◆ FE_B13_BSTCTL_1

#define FE_B13_BSTCTL_1   0x00

Definition at line 263 of file mb86960reg.h.

◆ FE_B13_BSTCTL_4

#define FE_B13_BSTCTL_4   0x01

Definition at line 264 of file mb86960reg.h.

◆ FE_B13_BSTCTL_8

#define FE_B13_BSTCTL_8   0x02

Definition at line 265 of file mb86960reg.h.

◆ FE_B13_IOUNLK

#define FE_B13_IOUNLK   0x80 /* Change I/O base address */

Definition at line 261 of file mb86960reg.h.

◆ FE_B13_LNKTST

#define FE_B13_LNKTST   0x20 /* Link test enable */

Definition at line 259 of file mb86960reg.h.

◆ FE_B13_PORT

#define FE_B13_PORT   0x18 /* Port (TP/AUI) selection */

Definition at line 258 of file mb86960reg.h.

◆ FE_B13_PORT_AUI

#define FE_B13_PORT_AUI   0x18 /* Force AUI */

Definition at line 273 of file mb86960reg.h.

◆ FE_B13_PORT_AUTO

#define FE_B13_PORT_AUTO   0x00 /* Auto detected */

Definition at line 271 of file mb86960reg.h.

◆ FE_B13_PORT_TP

#define FE_B13_PORT_TP   0x08 /* Force TP */

Definition at line 272 of file mb86960reg.h.

◆ FE_B13_SQTHLD

#define FE_B13_SQTHLD   0x40 /* Lower squelch threshold */

Definition at line 260 of file mb86960reg.h.

◆ FE_B13_TPTYPE

#define FE_B13_TPTYPE   0x04 /* Twisted pair cable impedance */

Definition at line 257 of file mb86960reg.h.

◆ FE_B13_TPTYPE_STP

#define FE_B13_TPTYPE_STP   0x04 /* Shielded (IBM) cable */

Definition at line 269 of file mb86960reg.h.

◆ FE_B13_TPTYPE_UTP

#define FE_B13_TPTYPE_UTP   0x00 /* Unshielded (standard) cable */

Definition at line 268 of file mb86960reg.h.

◆ FE_B14_FILTER

#define FE_B14_FILTER   0x01 /* Filter out self-originated packets */

Definition at line 276 of file mb86960reg.h.

◆ FE_B14_LLD

#define FE_B14_LLD   0x40 /* Local-link-down interrupt enable */

Definition at line 280 of file mb86960reg.h.

◆ FE_B14_RJAB

#define FE_B14_RJAB   0x20 /* RJAB interrupt enable */

Definition at line 279 of file mb86960reg.h.

◆ FE_B14_RLD

#define FE_B14_RLD   0x80 /* Remote-link-down interrupt enable */

Definition at line 281 of file mb86960reg.h.

◆ FE_B14_SKIP

#define FE_B14_SKIP   0x04 /* Skip a received packet */

Definition at line 278 of file mb86960reg.h.

◆ FE_B14_SQE

#define FE_B14_SQE   0x02 /* SQE interrupt enable */

Definition at line 277 of file mb86960reg.h.

◆ FE_B15_LLD

#define FE_B15_LLD   FE_B14_LLD

Definition at line 288 of file mb86960reg.h.

◆ FE_B15_RAJB

#define FE_B15_RAJB   FE_B14_RJAB

Definition at line 287 of file mb86960reg.h.

◆ FE_B15_RCVPOL

#define FE_B15_RCVPOL   0x08 /* Reversed receive line polarity */

Definition at line 285 of file mb86960reg.h.

◆ FE_B15_RLD

#define FE_B15_RLD   FE_B14_RLD

Definition at line 289 of file mb86960reg.h.

◆ FE_B15_RMTPRT

#define FE_B15_RMTPRT   0x10 /* ??? */

Definition at line 286 of file mb86960reg.h.

◆ FE_B15_SQE

#define FE_B15_SQE   FE_B14_SQE

Definition at line 284 of file mb86960reg.h.

◆ FE_B16_CLOCK

#define FE_B16_CLOCK   0x40 /* EEPROM shift clock */

Definition at line 294 of file mb86960reg.h.

◆ FE_B16_DIN

#define FE_B16_DIN   0x80 /* EEPROM data out (EEPROM to CPU) */

Definition at line 295 of file mb86960reg.h.

◆ FE_B16_DOUT

#define FE_B16_DOUT   0x04 /* EEPROM Data in (CPU to EEPROM) */

Definition at line 292 of file mb86960reg.h.

◆ FE_B16_SELECT

#define FE_B16_SELECT   0x20 /* EEPROM chip select */

Definition at line 293 of file mb86960reg.h.

◆ FE_B17_DATA

#define FE_B17_DATA   0x80 /* EEPROM data bit */

Definition at line 298 of file mb86960reg.h.

◆ FE_B19_ADDR

#define FE_B19_ADDR   0x07

Definition at line 309 of file mb86960reg.h.

◆ FE_B19_ADDR_SHIFT

#define FE_B19_ADDR_SHIFT   0

Definition at line 310 of file mb86960reg.h.

◆ FE_B19_IRQ

#define FE_B19_IRQ   0xC0

Definition at line 303 of file mb86960reg.h.

◆ FE_B19_IRQ_SHIFT

#define FE_B19_IRQ_SHIFT   6

Definition at line 304 of file mb86960reg.h.

◆ FE_B19_ROM

#define FE_B19_ROM   0x38

Definition at line 306 of file mb86960reg.h.

◆ FE_B19_ROM_SHIFT

#define FE_B19_ROM_SHIFT   3

Definition at line 307 of file mb86960reg.h.

◆ FE_BMPR10

#define FE_BMPR10   10

Definition at line 85 of file mb86960reg.h.

◆ FE_BMPR11

#define FE_BMPR11   11

Definition at line 86 of file mb86960reg.h.

◆ FE_BMPR12

#define FE_BMPR12   12

Definition at line 87 of file mb86960reg.h.

◆ FE_BMPR13

#define FE_BMPR13   13

Definition at line 88 of file mb86960reg.h.

◆ FE_BMPR14

#define FE_BMPR14   14

Definition at line 89 of file mb86960reg.h.

◆ FE_BMPR15

#define FE_BMPR15   15

Definition at line 90 of file mb86960reg.h.

◆ FE_BMPR16

#define FE_BMPR16   16

Definition at line 93 of file mb86960reg.h.

◆ FE_BMPR17

#define FE_BMPR17   17

Definition at line 94 of file mb86960reg.h.

◆ FE_BMPR18

#define FE_BMPR18   18

Definition at line 95 of file mb86960reg.h.

◆ FE_BMPR19

#define FE_BMPR19   19

Definition at line 96 of file mb86960reg.h.

◆ FE_BMPR8

#define FE_BMPR8   8

Definition at line 83 of file mb86960reg.h.

◆ FE_BMPR9

#define FE_BMPR9   9

Definition at line 84 of file mb86960reg.h.

◆ FE_D0_BUSERR

#define FE_D0_BUSERR   0x01 /* Bus write error */

Definition at line 110 of file mb86960reg.h.

◆ FE_D0_COLL16

#define FE_D0_COLL16   0x02 /* Collision limit (16) encountered */

Definition at line 111 of file mb86960reg.h.

◆ FE_D0_COLLID

#define FE_D0_COLLID   0x04 /* Collision on last transmission */

Definition at line 112 of file mb86960reg.h.

◆ FE_D0_CRLOST

#define FE_D0_CRLOST   0x10 /* Carrier lost on last transmission */

Definition at line 114 of file mb86960reg.h.

◆ FE_D0_JABBER

#define FE_D0_JABBER   0x08 /* Jabber */

Definition at line 113 of file mb86960reg.h.

◆ FE_D0_NETBSY

#define FE_D0_NETBSY   0x40 /* Network Busy (Carrier Detected) */

Definition at line 116 of file mb86960reg.h.

◆ FE_D0_PKTRCD

#define FE_D0_PKTRCD   0x20 /* No collision on last transmission */

Definition at line 115 of file mb86960reg.h.

◆ FE_D0_TXDONE

#define FE_D0_TXDONE   0x80 /* Transmission complete */

Definition at line 117 of file mb86960reg.h.

◆ FE_D1_ALGERR

#define FE_D1_ALGERR   0x04 /* Alignment error on last packet */

Definition at line 122 of file mb86960reg.h.

◆ FE_D1_BUSERR

#define FE_D1_BUSERR   0x40 /* Bus read error */

Definition at line 126 of file mb86960reg.h.

◆ FE_D1_CRCERR

#define FE_D1_CRCERR   0x02 /* CRC error on last packet */

Definition at line 121 of file mb86960reg.h.

◆ FE_D1_DMAEOP

#define FE_D1_DMAEOP   0x20 /* Host asserted End of DMA OPeration */

Definition at line 125 of file mb86960reg.h.

◆ FE_D1_ERRBITS

#define FE_D1_ERRBITS   "\20\4SRTPKT\3ALGERR\2CRCERR\1OVRFLO"

Definition at line 129 of file mb86960reg.h.

◆ FE_D1_OVRFLO

#define FE_D1_OVRFLO   0x01 /* Receiver buffer overflow */

Definition at line 120 of file mb86960reg.h.

◆ FE_D1_PKTRDY

#define FE_D1_PKTRDY   0x80 /* Packet(s) ready on receive buffer */

Definition at line 127 of file mb86960reg.h.

◆ FE_D1_RMTRST

#define FE_D1_RMTRST   0x10 /* Remote reset packet (type = 0x0900) */

Definition at line 124 of file mb86960reg.h.

◆ FE_D1_SRTPKT

#define FE_D1_SRTPKT   0x08 /* Short (RUNT) packet is received */

Definition at line 123 of file mb86960reg.h.

◆ FE_D2_BUSERR

#define FE_D2_BUSERR   FE_D0_BUSERR

Definition at line 132 of file mb86960reg.h.

◆ FE_D2_COLL16

#define FE_D2_COLL16   FE_D0_COLL16

Definition at line 133 of file mb86960reg.h.

◆ FE_D2_COLLID

#define FE_D2_COLLID   FE_D0_COLLID

Definition at line 134 of file mb86960reg.h.

◆ FE_D2_JABBER

#define FE_D2_JABBER   FE_D0_JABBER

Definition at line 135 of file mb86960reg.h.

◆ FE_D2_RESERVED

#define FE_D2_RESERVED   0x70

Definition at line 138 of file mb86960reg.h.

◆ FE_D2_TXDONE

#define FE_D2_TXDONE   FE_D0_TXDONE

Definition at line 136 of file mb86960reg.h.

◆ FE_D3_ALGERR

#define FE_D3_ALGERR   FE_D1_ALGERR

Definition at line 143 of file mb86960reg.h.

◆ FE_D3_BUSERR

#define FE_D3_BUSERR   FE_D1_BUSERR

Definition at line 147 of file mb86960reg.h.

◆ FE_D3_CRCERR

#define FE_D3_CRCERR   FE_D1_CRCERR

Definition at line 142 of file mb86960reg.h.

◆ FE_D3_DMAEOP

#define FE_D3_DMAEOP   FE_D1_DMAEOP

Definition at line 146 of file mb86960reg.h.

◆ FE_D3_OVRFLO

#define FE_D3_OVRFLO   FE_D1_OVRFLO

Definition at line 141 of file mb86960reg.h.

◆ FE_D3_PKTRDY

#define FE_D3_PKTRDY   FE_D1_PKTRDY

Definition at line 148 of file mb86960reg.h.

◆ FE_D3_RMTRST

#define FE_D3_RMTRST   FE_D1_RMTRST

Definition at line 145 of file mb86960reg.h.

◆ FE_D3_SRTPKT

#define FE_D3_SRTPKT   FE_D1_SRTPKT

Definition at line 144 of file mb86960reg.h.

◆ FE_D4_CNTRL

#define FE_D4_CNTRL   0x04 /* - ??? */

Definition at line 153 of file mb86960reg.h.

◆ FE_D4_COL

#define FE_D4_COL   0xF0 /* Collision counter */

Definition at line 155 of file mb86960reg.h.

◆ FE_D4_COL_SHIFT

#define FE_D4_COL_SHIFT   4

Definition at line 160 of file mb86960reg.h.

◆ FE_D4_DSC

#define FE_D4_DSC   0x01 /* Disable carrier sense on trans. */

Definition at line 151 of file mb86960reg.h.

◆ FE_D4_LBC

#define FE_D4_LBC   0x02 /* Loop back test control */

Definition at line 152 of file mb86960reg.h.

◆ FE_D4_LBC_DISABLE

#define FE_D4_LBC_DISABLE   0x02 /* Normal operation */

Definition at line 158 of file mb86960reg.h.

◆ FE_D4_LBC_ENABLE

#define FE_D4_LBC_ENABLE   0x00 /* Perform loop back test */

Definition at line 157 of file mb86960reg.h.

◆ FE_D4_TEST1

#define FE_D4_TEST1   0x08 /* Test output #1 */

Definition at line 154 of file mb86960reg.h.

◆ FE_D5_AFM0

#define FE_D5_AFM0   0x01 /* Receive packets for other stations */

Definition at line 163 of file mb86960reg.h.

◆ FE_D5_AFM1

#define FE_D5_AFM1   0x02 /* Receive packets for this station */

Definition at line 164 of file mb86960reg.h.

◆ FE_D5_BADPKT

#define FE_D5_BADPKT   0x20 /* Accept packets with error */

Definition at line 168 of file mb86960reg.h.

◆ FE_D5_BUFEMP

#define FE_D5_BUFEMP   0x40 /* Receive buffer is empty */

Definition at line 169 of file mb86960reg.h.

◆ FE_D5_RMTRST

#define FE_D5_RMTRST   0x04 /* Enable remote reset operation */

Definition at line 165 of file mb86960reg.h.

◆ FE_D5_SRTADR

#define FE_D5_SRTADR   0x10 /* Short (16 bits?) MAC address */

Definition at line 167 of file mb86960reg.h.

◆ FE_D5_SRTPKT

#define FE_D5_SRTPKT   0x08 /* Accept short (RUNT) packets */

Definition at line 166 of file mb86960reg.h.

◆ FE_D5_TEST2

#define FE_D5_TEST2   0x80 /* Test output #2 */

Definition at line 170 of file mb86960reg.h.

◆ FE_D6_BBW

#define FE_D6_BBW   0x10 /* Buffer SRAM bus width */

Definition at line 175 of file mb86960reg.h.

◆ FE_D6_BBW_BYTE

#define FE_D6_BBW_BYTE   0x10 /* SRAM has 8 bit data line */

Definition at line 191 of file mb86960reg.h.

◆ FE_D6_BBW_WORD

#define FE_D6_BBW_WORD   0x00 /* SRAM has 16 bit data line */

Definition at line 190 of file mb86960reg.h.

◆ FE_D6_BUFSIZ

#define FE_D6_BUFSIZ   0x03 /* Size of NIC buffer SRAM */

Definition at line 173 of file mb86960reg.h.

◆ FE_D6_BUFSIZ_16KB

#define FE_D6_BUFSIZ_16KB   0x01 /* The board has 16KB SRAM */

Definition at line 181 of file mb86960reg.h.

◆ FE_D6_BUFSIZ_32KB

#define FE_D6_BUFSIZ_32KB   0x02 /* The board has 32KB SRAM */

Definition at line 182 of file mb86960reg.h.

◆ FE_D6_BUFSIZ_64KB

#define FE_D6_BUFSIZ_64KB   0x03 /* The board has 64KB SRAM */

Definition at line 183 of file mb86960reg.h.

◆ FE_D6_BUFSIZ_8KB

#define FE_D6_BUFSIZ_8KB   0x00 /* The board has 8KB SRAM */

Definition at line 180 of file mb86960reg.h.

◆ FE_D6_DLC

#define FE_D6_DLC   0x80 /* Disable DLC (receiver/transmitter) */

Definition at line 178 of file mb86960reg.h.

◆ FE_D6_DLC_DISABLE

#define FE_D6_DLC_DISABLE   0x80 /* Stop sending/receiving */

Definition at line 200 of file mb86960reg.h.

◆ FE_D6_DLC_ENABLE

#define FE_D6_DLC_ENABLE   0x00 /* Normal operation */

Definition at line 199 of file mb86960reg.h.

◆ FE_D6_SBW

#define FE_D6_SBW   0x20 /* System bus width */

Definition at line 176 of file mb86960reg.h.

◆ FE_D6_SBW_BYTE

#define FE_D6_SBW_BYTE   0x20 /* Access with 8 bit (XT) bus */

Definition at line 194 of file mb86960reg.h.

◆ FE_D6_SBW_WORD

#define FE_D6_SBW_WORD   0x00 /* Access with 16 bit (AT) bus */

Definition at line 193 of file mb86960reg.h.

◆ FE_D6_SRAM

#define FE_D6_SRAM   0x40 /* Buffer SRAM access time */

Definition at line 177 of file mb86960reg.h.

◆ FE_D6_SRAM_100ns

#define FE_D6_SRAM_100ns   0x40 /* The board has fast SRAM */

Definition at line 197 of file mb86960reg.h.

◆ FE_D6_SRAM_150ns

#define FE_D6_SRAM_150ns   0x00 /* The board has slow SRAM */

Definition at line 196 of file mb86960reg.h.

◆ FE_D6_TXBSIZ

#define FE_D6_TXBSIZ   0x0C /* Size (and config)of trans. buffer */

Definition at line 174 of file mb86960reg.h.

◆ FE_D6_TXBSIZ_1x2KB

#define FE_D6_TXBSIZ_1x2KB   0x00 /* Single 2KB buffer for trans. */

Definition at line 185 of file mb86960reg.h.

◆ FE_D6_TXBSIZ_2x2KB

#define FE_D6_TXBSIZ_2x2KB   0x04 /* Double 2KB buffers */

Definition at line 186 of file mb86960reg.h.

◆ FE_D6_TXBSIZ_2x4KB

#define FE_D6_TXBSIZ_2x4KB   0x08 /* Double 4KB buffers */

Definition at line 187 of file mb86960reg.h.

◆ FE_D6_TXBSIZ_2x8KB

#define FE_D6_TXBSIZ_2x8KB   0x0C /* Double 8KB buffers */

Definition at line 188 of file mb86960reg.h.

◆ FE_D7_BYTSWP

#define FE_D7_BYTSWP   0x01 /* Host byte order control */

Definition at line 203 of file mb86960reg.h.

◆ FE_D7_BYTSWP_HL

#define FE_D7_BYTSWP_HL   0x01 /* IBM/Motorolla byte order */

Definition at line 212 of file mb86960reg.h.

◆ FE_D7_BYTSWP_LH

#define FE_D7_BYTSWP_LH   0x00 /* DEC/Intel byte order */

Definition at line 211 of file mb86960reg.h.

◆ FE_D7_ED

#define FE_D7_ED   0xC0 /* Encoder/Decoder config (for MB86960) */

Definition at line 208 of file mb86960reg.h.

◆ FE_D7_ED_BYPASS

#define FE_D7_ED_BYPASS   0x80 /* Encoder/Decorder Bypass */

Definition at line 223 of file mb86960reg.h.

◆ FE_D7_ED_MON

#define FE_D7_ED_MON   0x40 /* NICE + Monitor */

Definition at line 222 of file mb86960reg.h.

◆ FE_D7_ED_NORMAL

#define FE_D7_ED_NORMAL   0x00 /* Normal NICE */

Definition at line 221 of file mb86960reg.h.

◆ FE_D7_ED_TEST

#define FE_D7_ED_TEST   0xC0 /* Encoder/Decorder Test */

Definition at line 224 of file mb86960reg.h.

◆ FE_D7_EOPPOL

#define FE_D7_EOPPOL   0x02 /* Polarity of DMA EOP signal */

Definition at line 204 of file mb86960reg.h.

◆ FE_D7_IDENT

#define FE_D7_IDENT   0xC0 /* Chip identification */

Definition at line 209 of file mb86960reg.h.

◆ FE_D7_IDENT_86960

#define FE_D7_IDENT_86960   0x00 /* MB86960 (NICE) */

Definition at line 226 of file mb86960reg.h.

◆ FE_D7_IDENT_86964

#define FE_D7_IDENT_86964   0x40 /* MB86964 */

Definition at line 227 of file mb86960reg.h.

◆ FE_D7_IDENT_86965

#define FE_D7_IDENT_86965   0xC0 /* MB86965 (EtherCoupler) */

Definition at line 229 of file mb86960reg.h.

◆ FE_D7_IDENT_86967

#define FE_D7_IDENT_86967   0x80 /* MB86967 */

Definition at line 228 of file mb86960reg.h.

◆ FE_D7_POWER

#define FE_D7_POWER   0x20 /* Stand-by (power down) mode control */

Definition at line 207 of file mb86960reg.h.

◆ FE_D7_POWER_DOWN

#define FE_D7_POWER_DOWN   0x00 /* Power down (stand-by) mode */

Definition at line 218 of file mb86960reg.h.

◆ FE_D7_POWER_UP

#define FE_D7_POWER_UP   0x20 /* Normal operation */

Definition at line 219 of file mb86960reg.h.

◆ FE_D7_RBS

#define FE_D7_RBS   0x0C /* Register bank select */

Definition at line 205 of file mb86960reg.h.

◆ FE_D7_RBS_BMPR

#define FE_D7_RBS_BMPR   0x08 /* Select BMPR8-15 */

Definition at line 216 of file mb86960reg.h.

◆ FE_D7_RBS_DLCR

#define FE_D7_RBS_DLCR   0x00 /* Select DLCR8-15 */

Definition at line 214 of file mb86960reg.h.

◆ FE_D7_RBS_MAR

#define FE_D7_RBS_MAR   0x04 /* Select MAR8-15 */

Definition at line 215 of file mb86960reg.h.

◆ FE_D7_RDYPNS

#define FE_D7_RDYPNS   0x10 /* Senses RDYPNSEL input signal */

Definition at line 206 of file mb86960reg.h.

◆ FE_DLCR0

#define FE_DLCR0   0

Definition at line 53 of file mb86960reg.h.

◆ FE_DLCR1

#define FE_DLCR1   1

Definition at line 54 of file mb86960reg.h.

◆ FE_DLCR10

#define FE_DLCR10   10

Definition at line 65 of file mb86960reg.h.

◆ FE_DLCR11

#define FE_DLCR11   11

Definition at line 66 of file mb86960reg.h.

◆ FE_DLCR12

#define FE_DLCR12   12

Definition at line 67 of file mb86960reg.h.

◆ FE_DLCR13

#define FE_DLCR13   13

Definition at line 68 of file mb86960reg.h.

◆ FE_DLCR14

#define FE_DLCR14   14

Definition at line 69 of file mb86960reg.h.

◆ FE_DLCR15

#define FE_DLCR15   15

Definition at line 70 of file mb86960reg.h.

◆ FE_DLCR2

#define FE_DLCR2   2

Definition at line 55 of file mb86960reg.h.

◆ FE_DLCR3

#define FE_DLCR3   3

Definition at line 56 of file mb86960reg.h.

◆ FE_DLCR4

#define FE_DLCR4   4

Definition at line 57 of file mb86960reg.h.

◆ FE_DLCR5

#define FE_DLCR5   5

Definition at line 58 of file mb86960reg.h.

◆ FE_DLCR6

#define FE_DLCR6   6

Definition at line 59 of file mb86960reg.h.

◆ FE_DLCR7

#define FE_DLCR7   7

Definition at line 60 of file mb86960reg.h.

◆ FE_DLCR8

#define FE_DLCR8   8

Definition at line 63 of file mb86960reg.h.

◆ FE_DLCR9

#define FE_DLCR9   9

Definition at line 64 of file mb86960reg.h.

◆ FE_EEPROM_CONF

#define FE_EEPROM_CONF   0x00

Definition at line 320 of file mb86960reg.h.

◆ FE_EEPROM_DELAY

#define FE_EEPROM_DELAY ( )    DELAY(4)

Definition at line 323 of file mb86960reg.h.

◆ FE_EEPROM_SIZE

#define FE_EEPROM_SIZE   32

Definition at line 317 of file mb86960reg.h.

◆ FE_FILTER_LEN

#define FE_FILTER_LEN   8

Definition at line 343 of file mb86960reg.h.

◆ FE_MAR10

#define FE_MAR10   10

Definition at line 75 of file mb86960reg.h.

◆ FE_MAR11

#define FE_MAR11   11

Definition at line 76 of file mb86960reg.h.

◆ FE_MAR12

#define FE_MAR12   12

Definition at line 77 of file mb86960reg.h.

◆ FE_MAR13

#define FE_MAR13   13

Definition at line 78 of file mb86960reg.h.

◆ FE_MAR14

#define FE_MAR14   14

Definition at line 79 of file mb86960reg.h.

◆ FE_MAR15

#define FE_MAR15   15

Definition at line 80 of file mb86960reg.h.

◆ FE_MAR8

#define FE_MAR8   8

Definition at line 73 of file mb86960reg.h.

◆ FE_MAR9

#define FE_MAR9   9

Definition at line 74 of file mb86960reg.h.

◆ FE_MBH0

#define FE_MBH0   0x10 /* Master interrupt register */

Definition at line 362 of file mb86960reg.h.

◆ FE_MBH0_INTR_ENABLE

#define FE_MBH0_INTR_ENABLE   0x10 /* Enable interrupts */

Definition at line 365 of file mb86960reg.h.

◆ FE_MBH0_MASK

#define FE_MBH0_MASK   0x0D

Definition at line 364 of file mb86960reg.h.

◆ FE_MBH_ENADDR

#define FE_MBH_ENADDR   0x1A /* Mac address */

Definition at line 363 of file mb86960reg.h.

◆ FE_QUEUEING_MAX

#define FE_QUEUEING_MAX   127

Definition at line 346 of file mb86960reg.h.

◆ FE_RESET

#define FE_RESET   31

Definition at line 98 of file mb86960reg.h.

◆ FE_RXSTAT_ALIGNERR

#define FE_RXSTAT_ALIGNERR   0x04

Definition at line 355 of file mb86960reg.h.

◆ FE_RXSTAT_CRCERR

#define FE_RXSTAT_CRCERR   0x02

Definition at line 356 of file mb86960reg.h.

◆ FE_RXSTAT_GOODPKT

#define FE_RXSTAT_GOODPKT   0x20

Definition at line 352 of file mb86960reg.h.

◆ FE_RXSTAT_RMT0900

#define FE_RXSTAT_RMT0900   0x10

Definition at line 353 of file mb86960reg.h.

◆ FE_RXSTAT_SHORTPKT

#define FE_RXSTAT_SHORTPKT   0x08

Definition at line 354 of file mb86960reg.h.

◆ FE_TXLEN_SIZE

#define FE_TXLEN_SIZE   2

Definition at line 349 of file mb86960reg.h.

◆ MB8696X_NREGS

#define MB8696X_NREGS   32

Definition at line 6 of file mb86960reg.h.


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