dev_dreamcast_g2.cc Source File

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dev_dreamcast_g2.cc
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1 /*
2  * Copyright (C) 2006-2011 Anders Gavare. All rights reserved.
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions are met:
6  *
7  * 1. Redistributions of source code must retain the above copyright
8  * notice, this list of conditions and the following disclaimer.
9  * 2. Redistributions in binary form must reproduce the above copyright
10  * notice, this list of conditions and the following disclaimer in the
11  * documentation and/or other materials provided with the distribution.
12  * 3. The name of the author may not be used to endorse or promote products
13  * derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *
28  * COMMENT: Dreamcast G2 bus
29  *
30  * Register offsets are from KOS, NetBSD sources, etc.
31  *
32  * TODO:
33  * Figure out what all these registers do!
34  */
35 
36 #include <stdio.h>
37 #include <stdlib.h>
38 #include <string.h>
39 
40 #include "cpu.h"
41 #include "device.h"
42 #include "machine.h"
43 #include "memory.h"
44 #include "misc.h"
45 
46 
47 #ifdef UNSTABLE_DEVEL
48 // #define debug fatal
49 #endif
50 
51 #define NREGS_EXT_DMA (0x80/sizeof(uint32_t))
52 #define NREGS_MISC (0x80/sizeof(uint32_t))
53 
56  uint32_t misc_reg[NREGS_MISC];
57 };
58 
59 
60 /*
61  * External DMA: 4 channels
62  *
63  * Note: Addresses and sizes must be 32-byte aligned.
64  * DIR is 0 for CPU to External device, 1 for External to CPU.
65  * MODE should be 5 for transfers to/from the SPU.
66  */
67 #define EXTDMA_CTRL_EXT_ADDR 0x00 /* EXTDMA_CTRL_* are repeated */
68 #define EXTDMA_CTRL_SH4_ADDR 0x04 /* 4 times (once for each channel) */
69 #define EXTDMA_CTRL_SIZE 0x08
70 #define EXTDMA_CTRL_DIR 0x0c
71 #define EXTDMA_CTRL_MODE 0x10
72 #define EXTDMA_CTRL_CHAN_ENABLE 0x14 /* Channel enable */
73 #define EXTDMA_CTRL_XFER_ENABLE 0x18 /* Transfer enable */
74 #define EXTDMA_CTRL_STATUS 0x1c /* Transfer status */
75 
76 #define EXTDMA_WAITSTATE 0x90
77 #define EXTDMA_MAGIC 0xbc
78 #define EXTDMA_MAGIC_VALUE 0x4659404f
79 #define EXTDMA_MAGIC_VALUE_ROM 0x46597f00
80 
81 #define EXTDMA_STAT_EXT_ADDR 0xc0 /* EXTDMA_STAT_* are repeated 4 */
82 #define EXTDMA_STAT_SH4_ADDR 0xc4 /* times too */
83 #define EXTDMA_STAT_SIZE 0xc8
84 #define EXTDMA_STAT_STATUS 0xcc
85 
86 
87 DEVICE_ACCESS(dreamcast_g2_extdma)
88 {
89  struct dreamcast_g2_data *d = (struct dreamcast_g2_data *) extra;
90  uint64_t idata = 0, odata = 0;
91  int reg = relative_addr, channel = 0;
92 
93  if (writeflag == MEM_WRITE)
94  idata = memory_readmax64(cpu, data, len);
95 
96  /* Default read: */
97  if (writeflag == MEM_READ)
98  odata = d->extdma_reg[relative_addr / sizeof(uint32_t)];
99 
100  /*
101  * 0x5f7800 .. 1f = DMA channel 0
102  * 20 .. 3f = DMA channel 1
103  * 40 .. 5f = DMA channel 2
104  * 60 .. 7f = DMA channel 3
105  * 80 .. bf = misc magic stuff
106  * c0 .. cf = DMA channel 0 status
107  * d0 .. df = DMA channel 1 status
108  * e0 .. ef = DMA channel 2 status
109  * f0 .. ff = DMA channel 3 status
110  */
111  if (reg < 0x7f) {
112  channel = (reg >> 5) & 3;
113  reg &= 0x1f;
114  }
115  if (reg >= 0xc0 && reg < 0xff) {
116  channel = (reg >> 4) & 3;
117  reg = 0xc0 + (reg & 0xf);
118  }
119 
120  switch (reg) {
121 
123  if (writeflag == MEM_WRITE) {
124  debug("[ dreamcast_g2_extdma: write to channel %i:"
125  " EXT_ADDR = 0x%08x ]\n", channel, (int) idata);
126  }
127  break;
128 
130  if (writeflag == MEM_WRITE) {
131  debug("[ dreamcast_g2_extdma: write to channel %i:"
132  " SH4_ADDR = 0x%08x ]\n", channel, (int) idata);
133  }
134  break;
135 
136  case EXTDMA_CTRL_SIZE:
137  if (writeflag == MEM_WRITE) {
138  debug("[ dreamcast_g2_extdma: write to channel %i:"
139  " SIZE = 0x%08x ]\n", channel, (int) idata);
140  }
141  break;
142 
143  case EXTDMA_CTRL_DIR:
144  if (writeflag == MEM_WRITE) {
145  debug("[ dreamcast_g2_extdma: write to channel %i:"
146  " DIR = 0x%08x ]\n", channel, (int) idata);
147  }
148  break;
149 
150  case EXTDMA_CTRL_MODE:
151  if (writeflag == MEM_WRITE) {
152  debug("[ dreamcast_g2_extdma: write to channel %i:"
153  " MODE = 0x%08x ]\n", channel, (int) idata);
154  }
155  break;
156 
158  if (writeflag == MEM_WRITE) {
159  debug("[ dreamcast_g2_extdma: write to channel %i:"
160  " CHAN_ENABLE = 0x%08x ]\n", channel, (int) idata);
161  if (idata != 0) {
162  fatal("EXTDMA_CTRL_CHAN_ENABLE: todo\n");
163  exit(1);
164  }
165  }
166  break;
167 
169  if (writeflag == MEM_WRITE) {
170  debug("[ dreamcast_g2_extdma: write to channel %i:"
171  " XFER_ENABLE = 0x%08x ]\n", channel, (int) idata);
172  if (idata != 0) {
173  fatal("EXTDMA_CTRL_XFER_ENABLE: todo\n");
174  exit(1);
175  }
176  }
177  break;
178 
179  case EXTDMA_CTRL_STATUS:
180  if (writeflag == MEM_WRITE) {
181  debug("[ dreamcast_g2_extdma: write to channel %i:"
182  " STATUS = 0x%08x ]\n", channel, (int) idata);
183  if (idata != 0) {
184  fatal("[ dreamcast_g2_extdma: write to channel %i:"
185  " STATUS = 0x%08x: TODO (start transfer?) ]\n",
186  channel, (int) idata);
187  exit(1);
188  }
189  }
190  break;
191 
192  case EXTDMA_WAITSTATE:
193  break;
194 
195  case 0x94:
196  case 0x98:
197  case 0x9c:
198  case 0xa0:
199  case 0xa4:
200  case 0xa8:
201  case 0xac:
202  case 0xb0:
203  case 0xb4:
204  case 0xb8:
205  /* TODO */
206  break;
207 
208  case EXTDMA_MAGIC:
209  if (writeflag == MEM_WRITE) {
210  if (idata != EXTDMA_MAGIC_VALUE &&
211  idata != EXTDMA_MAGIC_VALUE_ROM) {
212  fatal("Unimplemented g2 extdma magic "
213  "vaule 0x%x\n", (int) idata);
214  exit(1);
215  }
216  }
217  break;
218 
219  default:if (writeflag == MEM_READ) {
220  fatal("[ dreamcast_g2_extdma: read from addr 0x%x ]\n",
221  (int)relative_addr);
222  } else {
223  fatal("[ dreamcast_g2_extdma: write to addr 0x%x: "
224  "0x%x ]\n", (int)relative_addr, (int)idata);
225  }
226 
227  exit(1);
228  }
229 
230  /* Default write: */
231  if (writeflag == MEM_WRITE)
232  d->extdma_reg[relative_addr / sizeof(uint32_t)] = idata;
233 
234  if (writeflag == MEM_READ)
235  memory_writemax64(cpu, data, len, odata);
236 
237  return 1;
238 }
239 
240 
241 DEVICE_ACCESS(dreamcast_g2_misc)
242 {
243  struct dreamcast_g2_data *d = (struct dreamcast_g2_data *) extra;
244  uint64_t idata = 0, odata = 0;
245 
246  if (writeflag == MEM_WRITE)
247  idata = memory_readmax64(cpu, data, len);
248 
249  /* Default read: */
250  if (writeflag == MEM_READ)
251  odata = d->misc_reg[relative_addr / sizeof(uint32_t)];
252 
253  switch (relative_addr) {
254 
255  case 0x64:
256  /* Writing 0x1fffff to 0x5f74e4 resets a disabled GD-ROM drive? */
257  if (writeflag != MEM_WRITE || idata != 0x1fffff) {
258  fatal("[ dreamcast_g2_misc: unimplemented 0xe4 ]\n");
259  exit(1);
260  }
261  break;
262 
263  default:if (writeflag == MEM_READ) {
264  debug("[ dreamcast_g2_misc: read from addr 0x%x ]\n",
265  (int)relative_addr);
266  } else {
267  debug("[ dreamcast_g2_misc: write to addr 0x%x: "
268  "0x%x ]\n", (int)relative_addr, (int)idata);
269  }
270 
271  /* exit(1); */
272  }
273 
274  /* Default write: */
275  if (writeflag == MEM_WRITE)
276  d->misc_reg[relative_addr / sizeof(uint32_t)] = idata;
277 
278  if (writeflag == MEM_READ)
279  memory_writemax64(cpu, data, len, odata);
280 
281  return 1;
282 }
283 
284 
285 DEVINIT(dreamcast_g2)
286 {
287  struct machine *machine = devinit->machine;
288  struct dreamcast_g2_data *d;
289 
290  CHECK_ALLOCATION(d = (struct dreamcast_g2_data *)
291  malloc(sizeof(struct dreamcast_g2_data)));
292  memset(d, 0, sizeof(struct dreamcast_g2_data));
293 
294  memory_device_register(machine->memory, "g2_misc", 0x005f7480,
295  0x80, dev_dreamcast_g2_misc_access, d, DM_DEFAULT, NULL);
296 
297  memory_device_register(machine->memory, "g2_extdma", 0x005f7800,
298  0x100, dev_dreamcast_g2_extdma_access, d, DM_DEFAULT, NULL);
299 
300  return 1;
301 }
302 
data
u_short data
Definition: siireg.h:79
EXTDMA_CTRL_SH4_ADDR
#define EXTDMA_CTRL_SH4_ADDR
Definition: dev_dreamcast_g2.cc:68
dreamcast_g2_data::extdma_reg
uint32_t extdma_reg[NREGS_EXT_DMA]
Definition: dev_dreamcast_g2.cc:55
debug
#define debug
Definition: dev_adb.cc:57
EXTDMA_CTRL_EXT_ADDR
#define EXTDMA_CTRL_EXT_ADDR
Definition: dev_dreamcast_g2.cc:67
EXTDMA_CTRL_CHAN_ENABLE
#define EXTDMA_CTRL_CHAN_ENABLE
Definition: dev_dreamcast_g2.cc:72
EXTDMA_MAGIC_VALUE_ROM
#define EXTDMA_MAGIC_VALUE_ROM
Definition: dev_dreamcast_g2.cc:79
memory_device_register
void memory_device_register(struct memory *mem, const char *, uint64_t baseaddr, uint64_t len, int(*f)(struct cpu *, struct memory *, uint64_t, unsigned char *, size_t, int, void *), void *extra, int flags, unsigned char *dyntrans_data)
Definition: memory.cc:339
MEM_READ
#define MEM_READ
Definition: memory.h:116
NREGS_EXT_DMA
#define NREGS_EXT_DMA
Definition: dev_dreamcast_g2.cc:51
DM_DEFAULT
#define DM_DEFAULT
Definition: memory.h:130
devinit::machine
struct machine * machine
Definition: device.h:41
device.h
EXTDMA_CTRL_SIZE
#define EXTDMA_CTRL_SIZE
Definition: dev_dreamcast_g2.cc:69
EXTDMA_CTRL_DIR
#define EXTDMA_CTRL_DIR
Definition: dev_dreamcast_g2.cc:70
MEM_WRITE
#define MEM_WRITE
Definition: memory.h:117
EXTDMA_MAGIC_VALUE
#define EXTDMA_MAGIC_VALUE
Definition: dev_dreamcast_g2.cc:78
fatal
void fatal(const char *fmt,...)
Definition: main.cc:152
DEVICE_ACCESS
DEVICE_ACCESS(dreamcast_g2_extdma)
Definition: dev_dreamcast_g2.cc:87
DEVINIT
DEVINIT(dreamcast_g2)
Definition: dev_dreamcast_g2.cc:285
misc.h
memory_readmax64
uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len)
Definition: memory.cc:55
machine.h
machine
Definition: machine.h:97
NREGS_MISC
#define NREGS_MISC
Definition: dev_dreamcast_g2.cc:52
EXTDMA_MAGIC
#define EXTDMA_MAGIC
Definition: dev_dreamcast_g2.cc:77
devinit
Definition: device.h:40
cpu.h
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struct memory * memory
Definition: machine.h:126
dreamcast_g2_data::misc_reg
uint32_t misc_reg[NREGS_MISC]
Definition: dev_dreamcast_g2.cc:56
reg
#define reg(x)
Definition: tmp_alpha_tail.cc:53
dreamcast_g2_data
Definition: dev_dreamcast_g2.cc:54
EXTDMA_WAITSTATE
#define EXTDMA_WAITSTATE
Definition: dev_dreamcast_g2.cc:76
EXTDMA_CTRL_MODE
#define EXTDMA_CTRL_MODE
Definition: dev_dreamcast_g2.cc:71
memory_writemax64
void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len, uint64_t data)
Definition: memory.cc:89
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Definition: cpu.h:326
EXTDMA_CTRL_XFER_ENABLE
#define EXTDMA_CTRL_XFER_ENABLE
Definition: dev_dreamcast_g2.cc:73
EXTDMA_CTRL_STATUS
#define EXTDMA_CTRL_STATUS
Definition: dev_dreamcast_g2.cc:74
memory.h
CHECK_ALLOCATION
#define CHECK_ALLOCATION(ptr)
Definition: misc.h:239

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