M88K_CPUComponent.h Source File
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Go to the documentation of this file. 1 #ifndef M88K_CPUCOMPONENT_H
2 #define M88K_CPUCOMPONENT_H
46 #define M88K_PID(arn,vn) ((arn << M88K_ARN_SHIFT) | (vn << M88K_VN_SHIFT))
48 #define M88K_CPU_TYPE_DEFS { \
49 { "88100", 88100, M88K_PID(M88K_ARN_88100,3) }, \
50 { "88110", 88110, M88K_PID(M88K_ARN_88110,0) }, \
57 #define M88K_OPCODE_NAMES { \
58 "xmem.bu", "xmem", "ld.hu", "ld.bu", \
59 "ld.d", "ld", "ld.h", "ld.b", \
60 "st.d", "st", "st.h", "st.b", \
61 "opcode0c", "opcode0d", "opcode0e", "opcode0f", \
62 "and", "and.u", "mask", "mask.u", \
63 "xor", "xor.u", "or", "or.u", \
64 "addu", "subu", "divu", "mulu", \
65 "add", "sub", "div", "cmp", \
66 "c(multi)", "f(multi)", "opcode22", "opcode23", \
67 "opcode24", "opcode25", "opcode26", "opcode27", \
68 "opcode28", "opcode29", "opcode2a", "opcode2b", \
69 "opcode2c", "opcode2d", "opcode2e", "opcode2f", \
70 "br", "br.n", "bsr", "bsr.n", \
71 "bb0", "bb0.n", "bb1", "bb1.n", \
72 "opcode38", "opcode39", "bcnd", "bcnd.n", \
73 "opcode3c", "3(multi)", "tbnd", "opcode3f" }
75 #define M88K_3C_OPCODE_NAMES { \
76 "opcode3c_00", "opcode3c_01", "opcode3c_02", "opcode3c_03", \
77 "opcode3c_04", "opcode3c_05", "opcode3c_06", "opcode3c_07", \
78 "opcode3c_08", "opcode3c_09", "opcode3c_0a", "opcode3c_0b", \
79 "opcode3c_0c", "opcode3c_0d", "opcode3c_0e", "opcode3c_0f", \
80 "opcode3c_10", "opcode3c_11", "opcode3c_12", "opcode3c_13", \
81 "opcode3c_14", "opcode3c_15", "opcode3c_16", "opcode3c_17", \
82 "opcode3c_18", "opcode3c_19", "opcode3c_1a", "opcode3c_1b", \
83 "opcode3c_1c", "opcode3c_1d", "opcode3c_1e", "opcode3c_1f", \
84 "clr", "opcode3c_21", "set", "opcode3c_23", \
85 "ext", "opcode3c_25", "extu", "opcode3c_27", \
86 "mak", "opcode3c_29", "rot", "opcode3c_2b", \
87 "opcode3c_2c", "opcode3c_2d", "opcode3c_2e", "opcode3c_2f", \
88 "opcode3c_30", "opcode3c_31", "opcode3c_32", "opcode3c_33", \
89 "tb0", "opcode3c_35", "tb1", "opcode3c_37", \
90 "opcode3c_38", "opcode3c_39", "opcode3c_3a", "opcode3c_3b", \
91 "opcode3c_3c", "opcode3c_3d", "opcode3c_3e", "opcode3c_3f" }
93 #define M88K_3D_OPCODE_NAMES { \
94 "opcode3d_00", "opcode3d_01", "opcode3d_02", "opcode3d_03", \
95 "opcode3d_04", "opcode3d_05", "opcode3d_06", "opcode3d_07", \
96 "opcode3d_08", "opcode3d_09", "opcode3d_0a", "opcode3d_0b", \
97 "opcode3d_0c", "opcode3d_0d", "opcode3d_0e", "opcode3d_0f", \
98 "opcode3d_10", "opcode3d_11", "opcode3d_12", "opcode3d_13", \
99 "opcode3d_14", "opcode3d_15", "opcode3d_16", "opcode3d_17", \
100 "opcode3d_18", "opcode3d_19", "opcode3d_1a", "opcode3d_1b", \
101 "opcode3d_1c", "opcode3d_1d", "opcode3d_1e", "opcode3d_1f", \
102 "opcode3d_20", "opcode3d_21", "opcode3d_22", "opcode3d_23", \
103 "opcode3d_24", "opcode3d_25", "opcode3d_26", "opcode3d_27", \
104 "opcode3d_28", "opcode3d_29", "opcode3d_2a", "opcode3d_2b", \
105 "opcode3d_2c", "opcode3d_2d", "opcode3d_2e", "opcode3d_2f", \
106 "opcode3d_30", "opcode3d_31", "opcode3d_32", "opcode3d_33", \
107 "opcode3d_34", "opcode3d_35", "opcode3d_36", "opcode3d_37", \
108 "opcode3d_38", "opcode3d_39", "opcode3d_3a", "opcode3d_3b", \
109 "opcode3d_3c", "opcode3d_3d", "opcode3d_3e", "opcode3d_3f", \
111 "and", "opcode3d_41", "opcode3d_42", "opcode3d_43", \
112 "and.c", "opcode3d_45", "opcode3d_46", "opcode3d_47", \
113 "opcode3d_48", "opcode3d_49", "opcode3d_4a", "opcode3d_4b", \
114 "opcode3d_4c", "opcode3d_4d", "opcode3d_4e", "opcode3d_4f", \
115 "xor", "opcode3d_51", "opcode3d_52", "opcode3d_53", \
116 "xor.c", "opcode3d_55", "opcode3d_56", "opcode3d_57", \
117 "or", "opcode3d_59", "opcode3d_5a", "opcode3d_5b", \
118 "or.c", "opcode3d_5d", "opcode3d_5e", "opcode3d_5f", \
119 "addu", "addu.co", "addu.ci", "addu.cio", \
120 "subu", "subu.co", "subu.ci", "subu.cio", \
121 "divu", "divu.d", "opcode3d_6a", "opcode3d_6b", \
122 "mul", "mulu.d", "muls", "opcode3d_6f", \
123 "add", "add.co", "add.ci", "add.cio", \
124 "sub", "sub.co", "sub.ci", "sub.cio", \
125 "div", "opcode3d_79", "opcode3d_7a", "opcode3d_7b", \
126 "cmp", "opcode3d_7d", "opcode3d_7e", "opcode3d_7f", \
128 "clr", "opcode3d_81", "opcode3d_82", "opcode3d_83", \
129 "opcode3d_84", "opcode3d_85", "opcode3d_86", "opcode3d_87", \
130 "set", "opcode3d_89", "opcode3d_8a", "opcode3d_8b", \
131 "opcode3d_8c", "opcode3d_8d", "opcode3d_8e", "opcode3d_8f", \
132 "ext", "opcode3d_91", "opcode3d_92", "opcode3d_93", \
133 "opcode3d_94", "opcode3d_95", "opcode3d_96", "opcode3d_97", \
134 "extu", "opcode3d_99", "opcode3d_9a", "opcode3d_9b", \
135 "opcode3d_9c", "opcode3d_9d", "opcode3d_9e", "opcode3d_9f", \
136 "mak", "opcode3d_a1", "opcode3d_a2", "opcode3d_a3", \
137 "opcode3d_a4", "opcode3d_a5", "opcode3d_a6", "opcode3d_a7", \
138 "rot", "opcode3d_a9", "opcode3d_aa", "opcode3d_ab", \
139 "opcode3d_ac", "opcode3d_ad", "opcode3d_ae", "opcode3d_af", \
140 "opcode3d_b0", "opcode3d_b1", "opcode3d_b2", "opcode3d_b3", \
141 "opcode3d_b4", "opcode3d_b5", "opcode3d_b6", "opcode3d_b7", \
142 "opcode3d_b8", "opcode3d_b9", "opcode3d_ba", "opcode3d_bb", \
143 "opcode3d_bc", "opcode3d_bd", "opcode3d_be", "opcode3d_bf", \
145 "jmp", "opcode3d_c1", "opcode3d_c2", "opcode3d_c3", \
146 "jmp.n", "opcode3d_c5", "opcode3d_c6", "opcode3d_c7", \
147 "jsr", "opcode3d_c9", "opcode3d_ca", "opcode3d_cb", \
148 "jsr.n", "opcode3d_cd", "opcode3d_ce", "opcode3d_cf", \
149 "opcode3d_d0", "opcode3d_d1", "opcode3d_d2", "opcode3d_d3", \
150 "opcode3d_d4", "opcode3d_d5", "opcode3d_d6", "opcode3d_d7", \
151 "opcode3d_d8", "opcode3d_d9", "opcode3d_da", "opcode3d_db", \
152 "opcode3d_dc", "opcode3d_dd", "opcode3d_de", "opcode3d_df", \
153 "opcode3d_e0", "opcode3d_e1", "opcode3d_e2", "opcode3d_e3", \
154 "opcode3d_e4", "opcode3d_e5", "opcode3d_e6", "opcode3d_e7", \
155 "ff1", "opcode3d_e9", "opcode3d_ea", "opcode3d_eb", \
156 "ff0", "opcode3d_ed", "opcode3d_ee", "opcode3d_ef", \
157 "opcode3d_f0", "opcode3d_f1", "opcode3d_f2", "opcode3d_f3", \
158 "opcode3d_f4", "opcode3d_f5", "opcode3d_f6", "opcode3d_f7", \
159 "tbnd", "opcode3d_f9", "opcode3d_fa", "opcode3d_fb", \
160 "opcode3d_fc", "opcode3d_fd", "opcode3d_fe", "opcode3d_ff" }
163 #define N_M88K_CONTROL_REGS 64
164 #define M88K_CR_NAMES { \
165 "PID", "PSR", "EPSR", "SSBR", \
166 "SXIP", "SNIP", "SFIP", "VBR", \
167 "DMT0", "DMD0", "DMA0", "DMT1", \
168 "DMD1", "DMA1", "DMT2", "DMD2", \
169 "DMA2", "SR0", "SR1", "SR2", \
170 "SR3", "CR21", "CR22", "CR23", \
171 "CR24", "CR25", "CR26", "CR27", \
172 "CR28", "CR29", "CR30", "CR31", \
173 "CR32", "CR33", "CR34", "CR35", \
174 "CR36", "CR37", "CR38", "CR39", \
175 "CR40", "CR41", "CR42", "CR43", \
176 "CR44", "CR45", "CR46", "CR47", \
177 "CR48", "CR49", "CR50", "CR51", \
178 "CR52", "CR53", "CR54", "CR55", \
179 "CR56", "CR57", "CR58", "CR59", \
180 "CR60", "CR61", "CR62", "CR63" }
182 #define M88K_CR_PID 0
183 #define M88K_CR_PSR 1
184 #define M88K_CR_EPSR 2
185 #define M88K_CR_SSBR 3
186 #define M88K_CR_SXIP 4
187 #define M88K_CR_SNIP 5
188 #define M88K_CR_SFIP 6
189 #define M88K_CR_VBR 7
190 #define M88K_CR_DMT0 8
191 #define M88K_CR_DMD0 9
192 #define M88K_CR_DMA0 10
193 #define M88K_CR_DMT1 11
194 #define M88K_CR_DMD1 12
195 #define M88K_CR_DMA1 13
196 #define M88K_CR_DMT2 14
197 #define M88K_CR_DMD2 15
198 #define M88K_CR_DMA2 16
199 #define M88K_CR_SR0 17
200 #define M88K_CR_SR1 18
201 #define M88K_CR_SR2 19
202 #define M88K_CR_SR3 20
205 #define M88K_CR_NAMES_197 { \
206 "PID", "PSR", "EPSR", "SSBR", \
207 "EXIP", "ENIP", "SFIP", "VBR", \
208 "DMT0", "DMD0", "DMA0", "DMT1", \
209 "DMD1", "DMA1", "DMT2", "DMD2", \
210 "SRX", "SR0", "SR1", "SR2", \
211 "SR3", "CR21", "CR22", "CR23", \
212 "CR24", "ICMD", "ICTL", "ISAR", \
213 "ISAP", "IUAP", "IIR", "IBP", \
214 "IPPU", "IPPL", "ISR", "ILAR", \
215 "IPAR", "CR37", "CR38", "CR39", \
216 "DCMD", "DCTL", "DSAR", "DSAP", \
217 "DUAP", "DIR", "DBP", "DPPU", \
218 "DPPL", "DSR", "DLAR", "DPAR", \
219 "CR52", "CR53", "CR54", "CR55", \
220 "CR56", "CR57", "CR58", "CR59", \
221 "CR60", "CR61", "CR62", "CR63" }
223 #define M88K_CR_EXIP 4
224 #define M88K_CR_ENIP 5
225 #define M88K_CR_SRX 16
226 #define M88K_CR_ICMD 25
227 #define M88K_CR_ICTL 26
228 #define M88K_CR_ISAR 27
229 #define M88K_CR_ISAP 28
230 #define M88K_CR_IUAP 29
231 #define M88K_CR_IIR 30
232 #define M88K_CR_IBP 31
233 #define M88K_CR_IPPU 32
234 #define M88K_CR_IPPL 33
235 #define M88K_CR_ISR 34
236 #define M88K_CR_ILAR 35
237 #define M88K_CR_IPAR 36
238 #define M88K_CR_DCMD 40
239 #define M88K_CR_DCTL 41
240 #define M88K_CR_DSAR 42
241 #define M88K_CR_DSAP 43
242 #define M88K_CR_DUAP 44
243 #define M88K_CR_DIR 45
244 #define M88K_CR_DBP 46
245 #define M88K_CR_DPPU 47
246 #define M88K_CR_DPPL 48
247 #define M88K_CR_DSR 49
248 #define M88K_CR_DLAR 50
249 #define M88K_CR_DPAR 51
252 #define N_M88K_FPU_CONTROL_REGS 64
254 #define M88K_FPCR_FPECR 0
255 #define M88K_FPECR_FDVZ (1 << 3)
256 #define M88K_FPECR_FUNIMP (1 << 6)
260 #define M88K_INSTR_ALIGNMENT_SHIFT 2
261 #define M88K_IC_ENTRIES_PER_PAGE 1024 // always 4 KB pages
264 #define N_M88K_REGS 32
265 #define M88K_ZERO_REG 0 // r0: always zero
266 #define M88K_RETURN_REG 1 // r1: the return address on function calls
267 #define M88K_RETURN_VALUE_REG 2 // r2: the return value, from function calls
268 #define M88K_FIRST_ARG_REG 2 // r2..r9: eight standard arguments to functions
269 #define M88K_STACKPOINTER_REG 31 // r31: commonly used as stack pointer
271 #define M88K_CMP_HS 0x00000800
272 #define M88K_CMP_LO 0x00000400
273 #define M88K_CMP_LS 0x00000200
274 #define M88K_CMP_HI 0x00000100
275 #define M88K_CMP_GE 0x00000080
276 #define M88K_CMP_LT 0x00000040
277 #define M88K_CMP_LE 0x00000020
278 #define M88K_CMP_GT 0x00000010
279 #define M88K_CMP_NE 0x00000008
280 #define M88K_CMP_EQ 0x00000004
283 #define M88K_EXCEPTION_RESET 0
284 #define M88K_EXCEPTION_INTERRUPT 1
285 #define M88K_EXCEPTION_INSTRUCTION_ACCESS 2
286 #define M88K_EXCEPTION_DATA_ACCESS 3
287 #define M88K_EXCEPTION_MISALIGNED_ACCESS 4
288 #define M88K_EXCEPTION_UNIMPLEMENTED_OPCODE 5
289 #define M88K_EXCEPTION_PRIVILEGE_VIOLATION 6
290 #define M88K_EXCEPTION_BOUNDS_CHECK_VIOLATION 7
291 #define M88K_EXCEPTION_ILLEGAL_INTEGER_DIVIDE 8
292 #define M88K_EXCEPTION_INTEGER_OVERFLOW 9
293 #define M88K_EXCEPTION_ERROR 10
294 #define M88K_EXCEPTION_SFU1_PRECISE 114
295 #define M88K_EXCEPTION_SFU1_IMPRECISE 115
296 #define M88K_EXCEPTION_USER_TRAPS_START 128
304 #define M88K_PROM_INSTR 0xf400fc92
307 #define M88K_FAIL_EARLY_INSTR 0xf400fc93
310 #define M88K_FAIL_LATE_INSTR 0xf400fc94
317 #define MAX_M8820X_CMMUS 8
318 #define M8820X_LENGTH 0x1000
319 #define N_M88200_BATC_REGS 10
320 #define N_M88200_PATC_ENTRIES 56
321 #define M8820X_PATC_SUPERVISOR_BIT 0x00000001
355 static string GetAttribute(
const string& attributeName);
362 unsigned char *instruction, vector<string>& result);
367 static void RunUnitTests(
int& nSucceeded,
int& nFailures);
385 void Exception(
int vector,
int is_trap);
387 void stcr(
int cr, uint32_t value,
bool is_rte);
394 DECLARE_DYNTRANS_INSTR(cmp);
395 DECLARE_DYNTRANS_INSTR(cmp_imm);
396 DECLARE_DYNTRANS_INSTR(extu);
397 DECLARE_DYNTRANS_INSTR(extu_imm);
398 DECLARE_DYNTRANS_INSTR(ext);
399 DECLARE_DYNTRANS_INSTR(ext_imm);
400 DECLARE_DYNTRANS_INSTR(mak);
401 DECLARE_DYNTRANS_INSTR(mak_imm);
402 DECLARE_DYNTRANS_INSTR(divu_imm);
403 DECLARE_DYNTRANS_INSTR(mulu_imm);
404 DECLARE_DYNTRANS_INSTR(bsr);
405 DECLARE_DYNTRANS_INSTR(bsr_samepage);
406 DECLARE_DYNTRANS_INSTR(bsr_functioncalltrace);
407 DECLARE_DYNTRANS_INSTR(bsr_n);
408 DECLARE_DYNTRANS_INSTR(bsr_n_functioncalltrace);
409 DECLARE_DYNTRANS_INSTR(bsr_n_functioncalltrace_singlestep);
414 DECLARE_DYNTRANS_INSTR(jmp);
415 DECLARE_DYNTRANS_INSTR(jmp_n);
416 DECLARE_DYNTRANS_INSTR(jmp_n_functioncalltrace);
417 DECLARE_DYNTRANS_INSTR(jmp_n_functioncalltrace_singlestep);
418 DECLARE_DYNTRANS_INSTR(ldcr);
419 DECLARE_DYNTRANS_INSTR(stcr);
421 template<
bool store,
typename T,
bool doubleword,
bool regofs,
bool scaled,
bool signedLoad>
static void instr_loadstore(
CPUDyntransComponent* cpubase,
DyntransIC*
ic);
425 DECLARE_DYNTRANS_INSTR(ToBeTranslated);
428 DECLARE_DYNTRANS_INSTR(fail_early);
429 DECLARE_DYNTRANS_INSTR(fail_late);
436 uint32_t m_initial_r31;
447 uint32_t m_zero_scratch;
462 #endif // M88K_CPUCOMPONENT_H
virtual void(*)(CPUDyntransComponent *, DyntransIC *) GetDyntransToBeTranslated()
virtual bool VirtualToPhysical(uint64_t vaddr, uint64_t &paddr, bool &writable)
Virtual to physical address translation (MMU).
M88K_CPUComponent()
Constructs a M88K_CPUComponent.
static void RunUnitTests(int &nSucceeded, int &nFailures)
virtual int64_t FunctionTraceArgument(int n)
virtual bool FunctionTraceReturnImpl(int64_t &retval)
#define N_M88200_BATC_REGS
virtual void ResetState()
Resets the state variables of this component.
#define N_M88K_FPU_CONTROL_REGS
#define N_M88200_PATC_ENTRIES
virtual size_t DisassembleInstruction(uint64_t vaddr, size_t maxlen, unsigned char *instruction, vector< string > &result)
Disassembles an instruction into readable strings.
StateVariables make up the persistent state of Component objects.
A base-class for processors Component implementations that use dynamic translation.
uint32_t patc_p_and_supervisorbit[N_M88200_PATC_ENTRIES]
uint32_t reg[M8820X_LENGTH/sizeof(uint32_t)]
A dyntrans instruction call.
virtual bool PreRunCheckForComponent(GXemul *gxemul)
Checks the state of this component, before starting execution.
struct arm_instr_call * ic
uint32_t patc_v_and_control[N_M88200_PATC_ENTRIES]
static refcount_ptr< Component > Create(const ComponentCreateArgs &args)
Creates a M88K_CPUComponent.
#define M88K_RETURN_VALUE_REG
A Component representing a Motorola 88000 processor.
#define M88K_FIRST_ARG_REG
static string GetAttribute(const string &attributeName)
virtual int FunctionTraceArgumentCount()
#define N_M88K_CONTROL_REGS
uint32_t batc[N_M88200_BATC_REGS]
virtual int GetDyntransICshift() const
virtual bool CheckVariableWrite(StateVariable &var, const string &oldValue)
Checks whether a write to a variable is OK.
virtual void ShowRegisters(GXemul *gxemul, const vector< string > &arguments) const
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