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Macros | |
#define | BL0 0 |
#define | BL1 1 |
#define | BL2 2 |
#define | BL3 3 |
#define | OSIOP_SCNTL0 (0x00+BL0) /* rw: SCSI control reg 0 */ |
#define | OSIOP_SCNTL1 (0x00+BL1) /* rw: SCSI control reg 1 */ |
#define | OSIOP_SDID (0x00+BL2) /* rw: SCSI destination ID */ |
#define | OSIOP_SIEN (0x00+BL3) /* rw: SCSI interrupt enable */ |
#define | OSIOP_SCID (0x04+BL0) /* rw: SCSI Chip ID reg */ |
#define | OSIOP_SXFER (0x04+BL1) /* rw: SCSI Transfer reg */ |
#define | OSIOP_SODL (0x04+BL2) /* rw: SCSI Output Data Latch */ |
#define | OSIOP_SOCL (0x04+BL3) /* rw: SCSI Output Control Latch */ |
#define | OSIOP_SFBR (0x08+BL0) /* ro: SCSI First Byte Received */ |
#define | OSIOP_SIDL (0x08+BL1) /* ro: SCSI Input Data Latch */ |
#define | OSIOP_SBDL (0x08+BL2) /* ro: SCSI Bus Data Lines */ |
#define | OSIOP_SBCL (0x08+BL3) /* rw: SCSI Bus Control Lines */ |
#define | OSIOP_DSTAT (0x0c+BL0) /* ro: DMA status */ |
#define | OSIOP_SSTAT0 (0x0c+BL1) /* ro: SCSI status reg 0 */ |
#define | OSIOP_SSTAT1 (0x0c+BL2) /* ro: SCSI status reg 1 */ |
#define | OSIOP_SSTAT2 (0x0c+BL3) /* ro: SCSI status reg 2 */ |
#define | OSIOP_DSA 0x10 /* rw: Data Structure Address */ |
#define | OSIOP_CTEST0 (0x14+BL0) /* ro: Chip test register 0 */ |
#define | OSIOP_CTEST1 (0x14+BL1) /* ro: Chip test register 1 */ |
#define | OSIOP_CTEST2 (0x14+BL2) /* ro: Chip test register 2 */ |
#define | OSIOP_CTEST3 (0x14+BL3) /* ro: Chip test register 3 */ |
#define | OSIOP_CTEST4 (0x18+BL0) /* rw: Chip test register 4 */ |
#define | OSIOP_CTEST5 (0x18+BL1) /* rw: Chip test register 5 */ |
#define | OSIOP_CTEST6 (0x18+BL2) /* rw: Chip test register 6 */ |
#define | OSIOP_CTEST7 (0x18+BL3) /* rw: Chip test register 7 */ |
#define | OSIOP_TEMP 0x1c /* rw: Temporary Stack reg */ |
#define | OSIOP_DFIFO (0x20+BL0) /* rw: DMA FIFO */ |
#define | OSIOP_ISTAT (0x20+BL1) /* rw: Interrupt Status reg */ |
#define | OSIOP_CTEST8 (0x20+BL2) /* rw: Chip test register 8 */ |
#define | OSIOP_LCRC (0x20+BL3) /* rw: LCRC value */ |
#define | OSIOP_DBC 0x24 /* rw: DMA Counter reg (longword) */ |
#define | OSIOP_DBC0 (0x24+BL0) /* rw: DMA Byte Counter reg 0 */ |
#define | OSIOP_DBC1 (0x24+BL1) /* rw: DMA Byte Counter reg 1 */ |
#define | OSIOP_DBC2 (0x24+BL2) /* rw: DMA Byte Counter reg 2 */ |
#define | OSIOP_DCMD (0x24+BL3) /* rw: DMA Command Register */ |
#define | OSIOP_DNAD 0x28 /* rw: DMA Next Data Address */ |
#define | OSIOP_DSP 0x2c /* rw: DMA SCRIPTS Pointer reg */ |
#define | OSIOP_DSPS 0x30 /* rw: DMA SCRIPTS Pointer Save reg */ |
#define | OSIOP_SCRATCH 0x34 /* rw: Scratch register */ |
#define | OSIOP_DMODE (0x38+BL0) /* rw: DMA Mode reg */ |
#define | OSIOP_DIEN (0x38+BL1) /* rw: DMA Interrupt Enable */ |
#define | OSIOP_DWT (0x38+BL2) /* rw: DMA Watchdog Timer */ |
#define | OSIOP_DCNTL (0x38+BL3) /* rw: DMA Control reg */ |
#define | OSIOP_ADDER 0x3c /* ro: Adder Sum Output */ |
#define | OSIOP_NREGS 0x40 |
#define | OSIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */ |
#define | OSIOP_ARB_SIMPLE 0x00 |
#define | OSIOP_ARB_FULL 0xc0 |
#define | OSIOP_SCNTL0_START 0x20 /* Start Sequence */ |
#define | OSIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */ |
#define | OSIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */ |
#define | OSIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */ |
#define | OSIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */ |
#define | OSIOP_SCNTL0_TRG 0x01 /* Target Mode */ |
#define | OSIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */ |
#define | OSIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */ |
#define | OSIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */ |
#define | OSIOP_SCNTL1_CON 0x10 /* Connected */ |
#define | OSIOP_SCNTL1_RST 0x08 /* Assert RST */ |
#define | OSIOP_SCNTL1_AESP 0x04 /* Assert even SCSI parity */ |
#define | OSIOP_SCNTL1_PAR 0x04 /* Force bad Parity */ |
#define | OSIOP_SCNTL1_RES0 0x02 /* Reserved */ |
#define | OSIOP_SCNTL1_RES1 0x01 /* Reserved */ |
#define | OSIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */ |
#define | OSIOP_SIEN_FCMP 0x40 /* Function Complete */ |
#define | OSIOP_SIEN_STO 0x20 /* (Re)Selection timeout */ |
#define | OSIOP_SIEN_SEL 0x10 /* (Re)Selected */ |
#define | OSIOP_SIEN_SGE 0x08 /* SCSI Gross Error */ |
#define | OSIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */ |
#define | OSIOP_SIEN_RST 0x02 /* RST asserted */ |
#define | OSIOP_SIEN_PAR 0x01 /* Parity Error */ |
#define | OSIOP_SCID_VALUE(i) (1 << (i)) |
#define | OSIOP_SXFER_DHP |
#define | OSIOP_SXFER_TP 0x70 /* Synch Transfer Period */ |
#define | OSIOP_SXFER_MO 0x0f /* Synch Max Offset */ |
#define | OSIOP_MAX_OFFSET 8 |
#define | OSIOP_REQ 0x80 /* SCSI signal <x> asserted */ |
#define | OSIOP_ACK 0x40 |
#define | OSIOP_BSY 0x20 |
#define | OSIOP_SEL 0x10 |
#define | OSIOP_ATN 0x08 |
#define | OSIOP_MSG 0x04 |
#define | OSIOP_CD 0x02 |
#define | OSIOP_IO 0x01 |
#define | OSIOP_PHASE(x) ((x) & (OSIOP_MSG|OSIOP_CD|OSIOP_IO)) |
#define | DATA_OUT_PHASE 0x00 |
#define | DATA_IN_PHASE OSIOP_IO |
#define | COMMAND_PHASE OSIOP_CD |
#define | STATUS_PHASE (OSIOP_CD|OSIOP_IO) |
#define | MSG_OUT_PHASE (OSIOP_MSG|OSIOP_CD) |
#define | MSG_IN_PHASE (OSIOP_MSG|OSIOP_CD|OSIOP_IO) |
#define | OSIOP_SBCL_SSCF1 0x02 /* wo */ |
#define | OSIOP_SBCL_SSCF0 0x01 /* wo */ |
#define | OSIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */ |
#define | OSIOP_DSTAT_RES 0x40 |
#define | OSIOP_DSTAT_BF 0x20 /* Bus fault */ |
#define | OSIOP_DSTAT_ABRT 0x10 /* Aborted */ |
#define | OSIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */ |
#define | OSIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */ |
#define | OSIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */ |
#define | OSIOP_DSTAT_IID 0x01 /* Invalid Instruction Detected */ |
#define | OSIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */ |
#define | OSIOP_SSTAT0_FCMP 0x40 /* Function Complete */ |
#define | OSIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */ |
#define | OSIOP_SSTAT0_SEL 0x10 /* (Re)Selected */ |
#define | OSIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */ |
#define | OSIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */ |
#define | OSIOP_SSTAT0_RST 0x02 /* RST asserted */ |
#define | OSIOP_SSTAT0_PAR 0x01 /* Parity Error */ |
#define | OSIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */ |
#define | OSIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */ |
#define | OSIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */ |
#define | OSIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */ |
#define | OSIOP_SSTAT1_LOA 0x08 /* Lost arbitration */ |
#define | OSIOP_SSTAT1_WOA 0x04 /* Won arbitration */ |
#define | OSIOP_SSTAT1_RST 0x02 /* SCSI RST current value */ |
#define | OSIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */ |
#define | OSIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */ |
#define | OSIOP_SCSI_FIFO_DEEP 8 |
#define | OSIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */ |
#define | OSIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */ |
#define | OSIOP_SSTAT2_CD 0x02 |
#define | OSIOP_SSTAT2_IO 0x01 |
#define | OSIOP_CTEST0_RES0 0x80 |
#define | OSIOP_CTEST0_BTD 0x40 /* Byte-to-byte Timer Disable */ |
#define | OSIOP_CTEST0_GRP 0x20 /* Generate Receive Parity */ |
#define | OSIOP_CTEST0_EAN 0x10 /* Enable Active Negation */ |
#define | OSIOP_CTEST0_HSC 0x08 /* Halt SCSI clock */ |
#define | OSIOP_CTEST0_ERF 0x04 /* Extend REQ/ACK Filtering */ |
#define | OSIOP_CTEST0_RES1 0x02 |
#define | OSIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */ |
#define | OSIOP_CTEST1_FMT |
#define | OSIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */ |
#define | OSIOP_CTEST2_RES 0x80 |
#define | OSIOP_CTEST2_SIGP 0x40 /* Signal process */ |
#define | OSIOP_CTEST2_SOFF |
#define | OSIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */ |
#define | OSIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */ |
#define | OSIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */ |
#define | OSIOP_CTEST2_DREQ 0x02 /* DREQ status */ |
#define | OSIOP_CTEST2_DACK 0x01 /* DACK status */ |
#define | OSIOP_CTEST4_MUX 0x80 /* Host bus multiplex mode */ |
#define | OSIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */ |
#define | OSIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */ |
#define | OSIOP_CTEST4_SLBE 0x10 /* SCSI loopback enable */ |
#define | OSIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */ |
#define | OSIOP_CTEST4_FBL |
#define | OSIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */ |
#define | OSIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */ |
#define | OSIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */ |
#define | OSIOP_CTEST5_MASR |
#define | OSIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */ |
#define | OSIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */ |
#define | OSIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */ |
#define | OSIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */ |
#define | OSIOP_CTEST7_CDIS 0x80 /* Cache burst disable */ |
#define | OSIOP_CTEST7_SC1 0x40 /* Snoop control 1 */ |
#define | OSIOP_CTEST7_SC0 0x20 /* Snoop control 0 */ |
#define | OSIOP_CTEST7_STD 0x10 /* Selection timeout disable */ |
#define | OSIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */ |
#define | OSIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */ |
#define | OSIOP_CTEST7_TT1 0x02 /* Transfer type bit */ |
#define | OSIOP_CTEST7_DIFF 0x01 /* Differential mode */ |
#define | OSIOP_DFIFO_FLF 0x80 /* Flush (spill) DMA FIFO */ |
#define | OSIOP_DFIFO_BO 0x7f /* FIFO byte offset counter */ |
#define | OSIOP_ISTAT_ABRT 0x80 /* Abort operation */ |
#define | OSIOP_ISTAT_RST 0x40 /* Software reset */ |
#define | OSIOP_ISTAT_SIGP 0x20 /* Signal process */ |
#define | OSIOP_ISTAT_RES 0x10 |
#define | OSIOP_ISTAT_CON 0x08 /* Connected */ |
#define | OSIOP_ISTAT_RES1 0x04 |
#define | OSIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */ |
#define | OSIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */ |
#define | OSIOP_CTEST8_V 0xf0 /* Chip revision level */ |
#define | OSIOP_CTEST8_FLF 0x08 /* Flush DMA FIFO */ |
#define | OSIOP_CTEST8_CLF 0x04 /* Clear DMA and SCSI FIFOs */ |
#define | OSIOP_CTEST8_FM 0x02 /* Fetch pin mode */ |
#define | OSIOP_CTEST8_SM 0x01 /* Snoop pins mode */ |
#define | OSIOP_DMODE_BL_MASK 0xc0 /* DMA burst length */ |
#define | OSIOP_DMODE_BL8 0xc0 /* 8 bytes */ |
#define | OSIOP_DMODE_BL4 0x80 /* 4 bytes */ |
#define | OSIOP_DMODE_BL2 0x40 /* 2 bytes */ |
#define | OSIOP_DMODE_BL1 0x00 /* 1 byte */ |
#define | OSIOP_DMODE_FC 0x30 /* Function code */ |
#define | OSIOP_DMODE_PD 0x08 /* Program/data */ |
#define | OSIOP_DMODE_FAM 0x04 /* fixed address mode */ |
#define | OSIOP_DMODE_U0 0x02 /* User programmable transfer type */ |
#define | OSIOP_DMODE_MAN 0x01 /* SCRIPTS in Manual start mode */ |
#define | OSIOP_DIEN_RES 0xc0 |
#define | OSIOP_DIEN_BF 0x20 /* On Bus Fault */ |
#define | OSIOP_DIEN_ABRT 0x10 /* On Abort */ |
#define | OSIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */ |
#define | OSIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */ |
#define | OSIOP_DIEN_WTD 0x02 /* On watchdog timeout */ |
#define | OSIOP_DIEN_IID 0x01 /* On illegal instruction detected */ |
#define | OSIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: */ |
#define | OSIOP_DCNTL_CF_2 0x00 /* 0 --> 37.51..50.00 MHz, div=2 */ |
#define | OSIOP_DCNTL_CF_1_5 0x40 /* 1 --> 25.01..37.50 MHz, div=1.5 */ |
#define | OSIOP_DCNTL_CF_1 0x80 /* 2 --> 16.67..25.00 MHz, div=1 */ |
#define | OSIOP_DCNTL_CF_3 0xc0 /* 3 --> 50.01..66.67 MHz, div=3 */ |
#define | OSIOP_DCNTL_EA 0x20 /* Enable ACK */ |
#define | OSIOP_DCNTL_SSM 0x10 /* Single step mode */ |
#define | OSIOP_DCNTL_LLM 0x08 /* Enable SCSI Low-level mode */ |
#define | OSIOP_DCNTL_STD 0x04 /* Start DMA operation */ |
#define | OSIOP_DCNTL_FA 0x02 /* Fast arbitration */ |
#define | OSIOP_DCNTL_COM 0x01 /* 53C700 Compatibility */ |
#define BL0 0 |
Definition at line 47 of file osiopreg.h.
#define BL1 1 |
Definition at line 48 of file osiopreg.h.
#define BL2 2 |
Definition at line 49 of file osiopreg.h.
#define BL3 3 |
Definition at line 50 of file osiopreg.h.
#define COMMAND_PHASE OSIOP_CD |
Definition at line 191 of file osiopreg.h.
#define DATA_IN_PHASE OSIOP_IO |
Definition at line 190 of file osiopreg.h.
#define DATA_OUT_PHASE 0x00 |
Definition at line 189 of file osiopreg.h.
Definition at line 194 of file osiopreg.h.
Definition at line 193 of file osiopreg.h.
#define OSIOP_ACK 0x40 |
Definition at line 180 of file osiopreg.h.
#define OSIOP_ADDER 0x3c /* ro: Adder Sum Output */ |
Definition at line 116 of file osiopreg.h.
#define OSIOP_ARB_FULL 0xc0 |
Definition at line 129 of file osiopreg.h.
#define OSIOP_ARB_SIMPLE 0x00 |
Definition at line 128 of file osiopreg.h.
#define OSIOP_ATN 0x08 |
Definition at line 183 of file osiopreg.h.
#define OSIOP_BSY 0x20 |
Definition at line 181 of file osiopreg.h.
#define OSIOP_CD 0x02 |
Definition at line 185 of file osiopreg.h.
#define OSIOP_CTEST0 (0x14+BL0) /* ro: Chip test register 0 */ |
Definition at line 80 of file osiopreg.h.
#define OSIOP_CTEST0_BTD 0x40 /* Byte-to-byte Timer Disable */ |
Definition at line 252 of file osiopreg.h.
#define OSIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */ |
Definition at line 258 of file osiopreg.h.
#define OSIOP_CTEST0_EAN 0x10 /* Enable Active Negation */ |
Definition at line 254 of file osiopreg.h.
#define OSIOP_CTEST0_ERF 0x04 /* Extend REQ/ACK Filtering */ |
Definition at line 256 of file osiopreg.h.
#define OSIOP_CTEST0_GRP 0x20 /* Generate Receive Parity */ |
Definition at line 253 of file osiopreg.h.
#define OSIOP_CTEST0_HSC 0x08 /* Halt SCSI clock */ |
Definition at line 255 of file osiopreg.h.
#define OSIOP_CTEST0_RES0 0x80 |
Definition at line 251 of file osiopreg.h.
#define OSIOP_CTEST0_RES1 0x02 |
Definition at line 257 of file osiopreg.h.
#define OSIOP_CTEST1 (0x14+BL1) /* ro: Chip test register 1 */ |
Definition at line 81 of file osiopreg.h.
#define OSIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */ |
Definition at line 264 of file osiopreg.h.
#define OSIOP_CTEST1_FMT |
Definition at line 263 of file osiopreg.h.
#define OSIOP_CTEST2 (0x14+BL2) /* ro: Chip test register 2 */ |
Definition at line 82 of file osiopreg.h.
#define OSIOP_CTEST2_DACK 0x01 /* DACK status */ |
Definition at line 275 of file osiopreg.h.
#define OSIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */ |
Definition at line 272 of file osiopreg.h.
#define OSIOP_CTEST2_DREQ 0x02 /* DREQ status */ |
Definition at line 274 of file osiopreg.h.
#define OSIOP_CTEST2_RES 0x80 |
Definition at line 268 of file osiopreg.h.
#define OSIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */ |
Definition at line 271 of file osiopreg.h.
#define OSIOP_CTEST2_SIGP 0x40 /* Signal process */ |
Definition at line 269 of file osiopreg.h.
#define OSIOP_CTEST2_SOFF |
Definition at line 270 of file osiopreg.h.
#define OSIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */ |
Definition at line 273 of file osiopreg.h.
#define OSIOP_CTEST3 (0x14+BL3) /* ro: Chip test register 3 */ |
Definition at line 83 of file osiopreg.h.
#define OSIOP_CTEST4 (0x18+BL0) /* rw: Chip test register 4 */ |
Definition at line 85 of file osiopreg.h.
#define OSIOP_CTEST4_FBL |
Definition at line 286 of file osiopreg.h.
#define OSIOP_CTEST4_MUX 0x80 /* Host bus multiplex mode */ |
Definition at line 281 of file osiopreg.h.
#define OSIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */ |
Definition at line 285 of file osiopreg.h.
#define OSIOP_CTEST4_SLBE 0x10 /* SCSI loopback enable */ |
Definition at line 284 of file osiopreg.h.
#define OSIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */ |
Definition at line 283 of file osiopreg.h.
#define OSIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */ |
Definition at line 282 of file osiopreg.h.
#define OSIOP_CTEST5 (0x18+BL1) /* rw: Chip test register 5 */ |
Definition at line 86 of file osiopreg.h.
#define OSIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */ |
Definition at line 290 of file osiopreg.h.
#define OSIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */ |
Definition at line 291 of file osiopreg.h.
#define OSIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */ |
Definition at line 297 of file osiopreg.h.
#define OSIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */ |
Definition at line 294 of file osiopreg.h.
#define OSIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */ |
Definition at line 296 of file osiopreg.h.
#define OSIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */ |
Definition at line 295 of file osiopreg.h.
#define OSIOP_CTEST5_MASR |
Definition at line 293 of file osiopreg.h.
#define OSIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */ |
Definition at line 292 of file osiopreg.h.
#define OSIOP_CTEST6 (0x18+BL2) /* rw: Chip test register 6 */ |
Definition at line 87 of file osiopreg.h.
#define OSIOP_CTEST7 (0x18+BL3) /* rw: Chip test register 7 */ |
Definition at line 88 of file osiopreg.h.
#define OSIOP_CTEST7_CDIS 0x80 /* Cache burst disable */ |
Definition at line 303 of file osiopreg.h.
#define OSIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */ |
Definition at line 307 of file osiopreg.h.
#define OSIOP_CTEST7_DIFF 0x01 /* Differential mode */ |
Definition at line 310 of file osiopreg.h.
#define OSIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */ |
Definition at line 308 of file osiopreg.h.
#define OSIOP_CTEST7_SC0 0x20 /* Snoop control 0 */ |
Definition at line 305 of file osiopreg.h.
#define OSIOP_CTEST7_SC1 0x40 /* Snoop control 1 */ |
Definition at line 304 of file osiopreg.h.
#define OSIOP_CTEST7_STD 0x10 /* Selection timeout disable */ |
Definition at line 306 of file osiopreg.h.
#define OSIOP_CTEST7_TT1 0x02 /* Transfer type bit */ |
Definition at line 309 of file osiopreg.h.
#define OSIOP_CTEST8 (0x20+BL2) /* rw: Chip test register 8 */ |
Definition at line 94 of file osiopreg.h.
#define OSIOP_CTEST8_CLF 0x04 /* Clear DMA and SCSI FIFOs */ |
Definition at line 332 of file osiopreg.h.
#define OSIOP_CTEST8_FLF 0x08 /* Flush DMA FIFO */ |
Definition at line 331 of file osiopreg.h.
#define OSIOP_CTEST8_FM 0x02 /* Fetch pin mode */ |
Definition at line 333 of file osiopreg.h.
#define OSIOP_CTEST8_SM 0x01 /* Snoop pins mode */ |
Definition at line 334 of file osiopreg.h.
#define OSIOP_CTEST8_V 0xf0 /* Chip revision level */ |
Definition at line 330 of file osiopreg.h.
#define OSIOP_DBC 0x24 /* rw: DMA Counter reg (longword) */ |
Definition at line 97 of file osiopreg.h.
Definition at line 98 of file osiopreg.h.
Definition at line 99 of file osiopreg.h.
Definition at line 100 of file osiopreg.h.
Definition at line 101 of file osiopreg.h.
Definition at line 114 of file osiopreg.h.
#define OSIOP_DCNTL_CF_1 0x80 /* 2 --> 16.67..25.00 MHz, div=1 */ |
Definition at line 364 of file osiopreg.h.
#define OSIOP_DCNTL_CF_1_5 0x40 /* 1 --> 25.01..37.50 MHz, div=1.5 */ |
Definition at line 363 of file osiopreg.h.
#define OSIOP_DCNTL_CF_2 0x00 /* 0 --> 37.51..50.00 MHz, div=2 */ |
Definition at line 362 of file osiopreg.h.
#define OSIOP_DCNTL_CF_3 0xc0 /* 3 --> 50.01..66.67 MHz, div=3 */ |
Definition at line 365 of file osiopreg.h.
#define OSIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: */ |
Definition at line 361 of file osiopreg.h.
#define OSIOP_DCNTL_COM 0x01 /* 53C700 Compatibility */ |
Definition at line 371 of file osiopreg.h.
#define OSIOP_DCNTL_EA 0x20 /* Enable ACK */ |
Definition at line 366 of file osiopreg.h.
#define OSIOP_DCNTL_FA 0x02 /* Fast arbitration */ |
Definition at line 370 of file osiopreg.h.
#define OSIOP_DCNTL_LLM 0x08 /* Enable SCSI Low-level mode */ |
Definition at line 368 of file osiopreg.h.
#define OSIOP_DCNTL_SSM 0x10 /* Single step mode */ |
Definition at line 367 of file osiopreg.h.
#define OSIOP_DCNTL_STD 0x04 /* Start DMA operation */ |
Definition at line 369 of file osiopreg.h.
#define OSIOP_DFIFO (0x20+BL0) /* rw: DMA FIFO */ |
Definition at line 92 of file osiopreg.h.
#define OSIOP_DFIFO_BO 0x7f /* FIFO byte offset counter */ |
Definition at line 315 of file osiopreg.h.
#define OSIOP_DFIFO_FLF 0x80 /* Flush (spill) DMA FIFO */ |
Definition at line 314 of file osiopreg.h.
#define OSIOP_DIEN (0x38+BL1) /* rw: DMA Interrupt Enable */ |
Definition at line 112 of file osiopreg.h.
#define OSIOP_DIEN_ABRT 0x10 /* On Abort */ |
Definition at line 353 of file osiopreg.h.
#define OSIOP_DIEN_BF 0x20 /* On Bus Fault */ |
Definition at line 352 of file osiopreg.h.
#define OSIOP_DIEN_IID 0x01 /* On illegal instruction detected */ |
Definition at line 357 of file osiopreg.h.
#define OSIOP_DIEN_RES 0xc0 |
Definition at line 351 of file osiopreg.h.
#define OSIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */ |
Definition at line 355 of file osiopreg.h.
#define OSIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */ |
Definition at line 354 of file osiopreg.h.
#define OSIOP_DIEN_WTD 0x02 /* On watchdog timeout */ |
Definition at line 356 of file osiopreg.h.
Definition at line 111 of file osiopreg.h.
#define OSIOP_DMODE_BL1 0x00 /* 1 byte */ |
Definition at line 342 of file osiopreg.h.
#define OSIOP_DMODE_BL2 0x40 /* 2 bytes */ |
Definition at line 341 of file osiopreg.h.
#define OSIOP_DMODE_BL4 0x80 /* 4 bytes */ |
Definition at line 340 of file osiopreg.h.
#define OSIOP_DMODE_BL8 0xc0 /* 8 bytes */ |
Definition at line 339 of file osiopreg.h.
#define OSIOP_DMODE_BL_MASK 0xc0 /* DMA burst length */ |
Definition at line 338 of file osiopreg.h.
#define OSIOP_DMODE_FAM 0x04 /* fixed address mode */ |
Definition at line 345 of file osiopreg.h.
#define OSIOP_DMODE_FC 0x30 /* Function code */ |
Definition at line 343 of file osiopreg.h.
#define OSIOP_DMODE_MAN 0x01 /* SCRIPTS in Manual start mode */ |
Definition at line 347 of file osiopreg.h.
#define OSIOP_DMODE_PD 0x08 /* Program/data */ |
Definition at line 344 of file osiopreg.h.
#define OSIOP_DMODE_U0 0x02 /* User programmable transfer type */ |
Definition at line 346 of file osiopreg.h.
#define OSIOP_DNAD 0x28 /* rw: DMA Next Data Address */ |
Definition at line 103 of file osiopreg.h.
#define OSIOP_DSA 0x10 /* rw: Data Structure Address */ |
Definition at line 78 of file osiopreg.h.
#define OSIOP_DSP 0x2c /* rw: DMA SCRIPTS Pointer reg */ |
Definition at line 105 of file osiopreg.h.
#define OSIOP_DSPS 0x30 /* rw: DMA SCRIPTS Pointer Save reg */ |
Definition at line 107 of file osiopreg.h.
#define OSIOP_DSTAT (0x0c+BL0) /* ro: DMA status */ |
Definition at line 73 of file osiopreg.h.
#define OSIOP_DSTAT_ABRT 0x10 /* Aborted */ |
Definition at line 212 of file osiopreg.h.
#define OSIOP_DSTAT_BF 0x20 /* Bus fault */ |
Definition at line 211 of file osiopreg.h.
#define OSIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */ |
Definition at line 209 of file osiopreg.h.
#define OSIOP_DSTAT_IID 0x01 /* Invalid Instruction Detected */ |
Definition at line 216 of file osiopreg.h.
#define OSIOP_DSTAT_RES 0x40 |
Definition at line 210 of file osiopreg.h.
#define OSIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */ |
Definition at line 214 of file osiopreg.h.
#define OSIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */ |
Definition at line 213 of file osiopreg.h.
#define OSIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */ |
Definition at line 215 of file osiopreg.h.
#define OSIOP_DWT (0x38+BL2) /* rw: DMA Watchdog Timer */ |
Definition at line 113 of file osiopreg.h.
#define OSIOP_IO 0x01 |
Definition at line 186 of file osiopreg.h.
Definition at line 93 of file osiopreg.h.
#define OSIOP_ISTAT_ABRT 0x80 /* Abort operation */ |
Definition at line 319 of file osiopreg.h.
#define OSIOP_ISTAT_CON 0x08 /* Connected */ |
Definition at line 323 of file osiopreg.h.
#define OSIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */ |
Definition at line 326 of file osiopreg.h.
#define OSIOP_ISTAT_RES 0x10 |
Definition at line 322 of file osiopreg.h.
#define OSIOP_ISTAT_RES1 0x04 |
Definition at line 324 of file osiopreg.h.
#define OSIOP_ISTAT_RST 0x40 /* Software reset */ |
Definition at line 320 of file osiopreg.h.
#define OSIOP_ISTAT_SIGP 0x20 /* Signal process */ |
Definition at line 321 of file osiopreg.h.
#define OSIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */ |
Definition at line 325 of file osiopreg.h.
#define OSIOP_LCRC (0x20+BL3) /* rw: LCRC value */ |
Definition at line 95 of file osiopreg.h.
#define OSIOP_MAX_OFFSET 8 |
Definition at line 173 of file osiopreg.h.
#define OSIOP_MSG 0x04 |
Definition at line 184 of file osiopreg.h.
#define OSIOP_NREGS 0x40 |
Definition at line 118 of file osiopreg.h.
Definition at line 188 of file osiopreg.h.
#define OSIOP_REQ 0x80 /* SCSI signal <x> asserted */ |
Definition at line 179 of file osiopreg.h.
#define OSIOP_SBCL (0x08+BL3) /* rw: SCSI Bus Control Lines */ |
Definition at line 71 of file osiopreg.h.
#define OSIOP_SBCL_SSCF0 0x01 /* wo */ |
Definition at line 205 of file osiopreg.h.
#define OSIOP_SBCL_SSCF1 0x02 /* wo */ |
Definition at line 204 of file osiopreg.h.
#define OSIOP_SBDL (0x08+BL2) /* ro: SCSI Bus Data Lines */ |
Definition at line 70 of file osiopreg.h.
Definition at line 63 of file osiopreg.h.
#define OSIOP_SCID_VALUE | ( | i | ) | (1 << (i)) |
Definition at line 162 of file osiopreg.h.
Definition at line 58 of file osiopreg.h.
#define OSIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */ |
Definition at line 134 of file osiopreg.h.
#define OSIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */ |
Definition at line 127 of file osiopreg.h.
#define OSIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */ |
Definition at line 132 of file osiopreg.h.
#define OSIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */ |
Definition at line 133 of file osiopreg.h.
#define OSIOP_SCNTL0_START 0x20 /* Start Sequence */ |
Definition at line 130 of file osiopreg.h.
#define OSIOP_SCNTL0_TRG 0x01 /* Target Mode */ |
Definition at line 135 of file osiopreg.h.
#define OSIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */ |
Definition at line 131 of file osiopreg.h.
Definition at line 59 of file osiopreg.h.
#define OSIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */ |
Definition at line 140 of file osiopreg.h.
#define OSIOP_SCNTL1_AESP 0x04 /* Assert even SCSI parity */ |
Definition at line 144 of file osiopreg.h.
#define OSIOP_SCNTL1_CON 0x10 /* Connected */ |
Definition at line 142 of file osiopreg.h.
#define OSIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */ |
Definition at line 141 of file osiopreg.h.
#define OSIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */ |
Definition at line 139 of file osiopreg.h.
#define OSIOP_SCNTL1_PAR 0x04 /* Force bad Parity */ |
Definition at line 145 of file osiopreg.h.
#define OSIOP_SCNTL1_RES0 0x02 /* Reserved */ |
Definition at line 146 of file osiopreg.h.
#define OSIOP_SCNTL1_RES1 0x01 /* Reserved */ |
Definition at line 147 of file osiopreg.h.
#define OSIOP_SCNTL1_RST 0x08 /* Assert RST */ |
Definition at line 143 of file osiopreg.h.
#define OSIOP_SCRATCH 0x34 /* rw: Scratch register */ |
Definition at line 109 of file osiopreg.h.
#define OSIOP_SCSI_FIFO_DEEP 8 |
Definition at line 243 of file osiopreg.h.
#define OSIOP_SDID (0x00+BL2) /* rw: SCSI destination ID */ |
Definition at line 60 of file osiopreg.h.
#define OSIOP_SEL 0x10 |
Definition at line 182 of file osiopreg.h.
#define OSIOP_SFBR (0x08+BL0) /* ro: SCSI First Byte Received */ |
Definition at line 68 of file osiopreg.h.
#define OSIOP_SIDL (0x08+BL1) /* ro: SCSI Input Data Latch */ |
Definition at line 69 of file osiopreg.h.
Definition at line 61 of file osiopreg.h.
#define OSIOP_SIEN_FCMP 0x40 /* Function Complete */ |
Definition at line 152 of file osiopreg.h.
#define OSIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */ |
Definition at line 151 of file osiopreg.h.
#define OSIOP_SIEN_PAR 0x01 /* Parity Error */ |
Definition at line 158 of file osiopreg.h.
#define OSIOP_SIEN_RST 0x02 /* RST asserted */ |
Definition at line 157 of file osiopreg.h.
#define OSIOP_SIEN_SEL 0x10 /* (Re)Selected */ |
Definition at line 154 of file osiopreg.h.
#define OSIOP_SIEN_SGE 0x08 /* SCSI Gross Error */ |
Definition at line 155 of file osiopreg.h.
#define OSIOP_SIEN_STO 0x20 /* (Re)Selection timeout */ |
Definition at line 153 of file osiopreg.h.
#define OSIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */ |
Definition at line 156 of file osiopreg.h.
#define OSIOP_SOCL (0x04+BL3) /* rw: SCSI Output Control Latch */ |
Definition at line 66 of file osiopreg.h.
#define OSIOP_SODL (0x04+BL2) /* rw: SCSI Output Data Latch */ |
Definition at line 65 of file osiopreg.h.
Definition at line 74 of file osiopreg.h.
#define OSIOP_SSTAT0_FCMP 0x40 /* Function Complete */ |
Definition at line 221 of file osiopreg.h.
#define OSIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */ |
Definition at line 220 of file osiopreg.h.
#define OSIOP_SSTAT0_PAR 0x01 /* Parity Error */ |
Definition at line 227 of file osiopreg.h.
#define OSIOP_SSTAT0_RST 0x02 /* RST asserted */ |
Definition at line 226 of file osiopreg.h.
#define OSIOP_SSTAT0_SEL 0x10 /* (Re)Selected */ |
Definition at line 223 of file osiopreg.h.
#define OSIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */ |
Definition at line 224 of file osiopreg.h.
#define OSIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */ |
Definition at line 222 of file osiopreg.h.
#define OSIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */ |
Definition at line 225 of file osiopreg.h.
Definition at line 75 of file osiopreg.h.
#define OSIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */ |
Definition at line 234 of file osiopreg.h.
#define OSIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */ |
Definition at line 231 of file osiopreg.h.
#define OSIOP_SSTAT1_LOA 0x08 /* Lost arbitration */ |
Definition at line 235 of file osiopreg.h.
#define OSIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */ |
Definition at line 233 of file osiopreg.h.
#define OSIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */ |
Definition at line 232 of file osiopreg.h.
#define OSIOP_SSTAT1_RST 0x02 /* SCSI RST current value */ |
Definition at line 237 of file osiopreg.h.
#define OSIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */ |
Definition at line 238 of file osiopreg.h.
#define OSIOP_SSTAT1_WOA 0x04 /* Won arbitration */ |
Definition at line 236 of file osiopreg.h.
Definition at line 76 of file osiopreg.h.
#define OSIOP_SSTAT2_CD 0x02 |
Definition at line 246 of file osiopreg.h.
#define OSIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */ |
Definition at line 242 of file osiopreg.h.
#define OSIOP_SSTAT2_IO 0x01 |
Definition at line 247 of file osiopreg.h.
#define OSIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */ |
Definition at line 245 of file osiopreg.h.
#define OSIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */ |
Definition at line 244 of file osiopreg.h.
Definition at line 64 of file osiopreg.h.
#define OSIOP_SXFER_DHP |
Definition at line 166 of file osiopreg.h.
#define OSIOP_SXFER_MO 0x0f /* Synch Max Offset */ |
Definition at line 172 of file osiopreg.h.
#define OSIOP_SXFER_TP 0x70 /* Synch Transfer Period */ |
Definition at line 167 of file osiopreg.h.
#define OSIOP_TEMP 0x1c /* rw: Temporary Stack reg */ |
Definition at line 90 of file osiopreg.h.
Definition at line 192 of file osiopreg.h.