sh4_mmu.h Source File
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3 #ifndef _SH3_MMU_SH4_H_
4 #define _SH3_MMU_SH4_H_
45 #define SH4_PTEH 0xff000000
46 #define SH4_PTEH_VPN_MASK 0xfffffc00
47 #define SH4_PTEH_ASID_MASK 0x000000ff
48 #define SH4_PTEL 0xff000004
49 #define SH4_PTEL_WT 0x00000001
50 #define SH4_PTEL_SH 0x00000002
51 #define SH4_PTEL_D 0x00000004
52 #define SH4_PTEL_C 0x00000008
53 #define SH4_PTEL_PR_SHIFT 5
54 #define SH4_PTEL_PR_MASK 0x00000060
55 #define SH4_PTEL_SZ_MASK 0x00000090
56 #define SH4_PTEL_SZ_1K 0x00000000
57 #define SH4_PTEL_SZ_4K 0x00000010
58 #define SH4_PTEL_SZ_64K 0x00000080
59 #define SH4_PTEL_SZ_1M 0x00000090
60 #define SH4_PTEL_V 0x00000100
61 #define SH4_PTEL_HWBITS 0x1ffff1ff
63 #define SH4_PTEA 0xff000034
64 #define SH4_PTEA_SA_MASK 0x00000007
65 #define SH4_PTEA_SA_TC 0x00000008
66 #define SH4_TTB 0xff000008
67 #define SH4_TEA 0xff00000c
68 #define SH4_MMUCR 0xff000010
69 #define SH4_MMUCR_AT 0x00000001
70 #define SH4_MMUCR_TI 0x00000004
71 #define SH4_MMUCR_SV 0x00000100
72 #define SH4_MMUCR_SQMD 0x00000200
73 #define SH4_MMUCR_URC_SHIFT 10
74 #define SH4_MMUCR_URC_MASK 0x0000fc00
75 #define SH4_MMUCR_URB_SHIFT 18
76 #define SH4_MMUCR_URB_MASK 0x00fc0000
77 #define SH4_MMUCR_LRUI_SHIFT 26
78 #define SH4_MMUCR_LRUT_MASK 0xfc000000
80 #define SH4_MMUCR_MASK (SH4_MMUCR_LRUT_MASK | SH4_MMUCR_URB_MASK | \
81 SH4_MMUCR_URC_MASK | SH4_MMUCR_SQMD | SH4_MMUCR_SV | SH4_MMUCR_AT)
88 #define SH4_ITLB_ENTRY 4
89 #define SH4_UTLB_ENTRY 64
92 #define SH4_ITLB_AA 0xf2000000
94 #define SH4_ITLB_E_SHIFT 8
95 #define SH4_ITLB_E_MASK 0x00000300
98 #define SH4_ITLB_AA_ASID_MASK 0x000000ff
99 #define SH4_ITLB_AA_V 0x00000100
100 #define SH4_ITLB_AA_VPN_SHIFT 10
101 #define SH4_ITLB_AA_VPN_MASK 0xfffffc00
103 #define SH4_ITLB_DA1 0xf3000000
104 #define SH4_ITLB_DA1_SH 0x00000002
105 #define SH4_ITLB_DA1_C 0x00000008
106 #define SH4_ITLB_DA1_SZ_MASK 0x00000090
107 #define SH4_ITLB_DA1_SZ_1K 0x00000000
108 #define SH4_ITLB_DA1_SZ_4K 0x00000010
109 #define SH4_ITLB_DA1_SZ_64K 0x00000080
110 #define SH4_ITLB_DA1_SZ_1M 0x00000090
111 #define SH4_ITLB_DA1_PR 0x00000040
112 #define SH4_ITLB_DA1_V 0x00000100
113 #define SH4_ITLB_DA1_PPN_SHIFT 11
114 #define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00
116 #define SH4_ITLB_DA2 0xf3800000
117 #define SH4_ITLB_DA2_SA_MASK 0x00000003
118 #define SH4_ITLB_DA2_TC 0x00000004
121 #define SH4_UTLB_AA 0xf6000000
123 #define SH4_UTLB_E_SHIFT 8
124 #define SH4_UTLB_E_MASK 0x00003f00
125 #define SH4_UTLB_A 0x00000080
128 #define SH4_UTLB_AA_VPN_MASK 0xfffffc00
129 #define SH4_UTLB_AA_D 0x00000200
130 #define SH4_UTLB_AA_V 0x00000100
131 #define SH4_UTLB_AA_ASID_MASK 0x000000ff
133 #define SH4_UTLB_DA1 0xf7000000
134 #define SH4_UTLB_DA1_WT 0x00000001
135 #define SH4_UTLB_DA1_SH 0x00000002
136 #define SH4_UTLB_DA1_D 0x00000004
137 #define SH4_UTLB_DA1_C 0x00000008
138 #define SH4_UTLB_DA1_SZ_MASK 0x00000090
139 #define SH4_UTLB_DA1_SZ_1K 0x00000000
140 #define SH4_UTLB_DA1_SZ_4K 0x00000010
141 #define SH4_UTLB_DA1_SZ_64K 0x00000080
142 #define SH4_UTLB_DA1_SZ_1M 0x00000090
143 #define SH4_UTLB_DA1_PR_SHIFT 5
144 #define SH4_UTLB_DA1_PR_MASK 0x00000060
145 #define SH4_UTLB_DA1_V 0x00000100
146 #define SH4_UTLB_DA1_PPN_SHIFT 11
147 #define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00
149 #define SH4_UTLB_DA2 0xf7800000
150 #define SH4_UTLB_DA2_SA_MASK 0x00000003
151 #define SH4_UTLB_DA2_TC 0x00000004
153 #define SH4_TLB_DISABLE *(volatile uint32_t *)SH4_MMUCR = SH4_MMUCR_TI
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