ppc_spr.h File Reference

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Macros
ppc_spr.h File Reference

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Macros

#define SPR_MQ   0x000 /* .6. 601 MQ register */
 
#define SPR_XER   0x001 /* 468 Fixed Point Exception Register */
 
#define SPR_RTCU_R   0x004 /* .6. 601 RTC Upper - Read */
 
#define SPR_RTCL_R   0x005 /* .6. 601 RTC Lower - Read */
 
#define SPR_LR   0x008 /* 468 Link Register */
 
#define SPR_CTR   0x009 /* 468 Count Register */
 
#define SPR_DSISR   0x012 /* .68 DSI exception source */
 
#define DSISR_DIRECT   0x80000000 /* Direct-store error exception */
 
#define DSISR_NOTFOUND   0x40000000 /* Translation not found */
 
#define DSISR_PROTECT   0x08000000 /* Memory access not permitted */
 
#define DSISR_INVRX   0x04000000 /* Reserve-indexed insn direct-store access */
 
#define DSISR_STORE   0x02000000 /* Store operation */
 
#define DSISR_DABR   0x00400000 /* DABR match */
 
#define DSISR_SEGMENT   0x00200000 /* XXX; not in 6xx PEM */
 
#define DSISR_EAR   0x00100000 /* eciwx/ecowx && EAR[E] == 0 */
 
#define SPR_DAR   0x013 /* .68 Data Address Register */
 
#define SPR_RTCU_W   0x014 /* .6. 601 RTC Upper - Write */
 
#define SPR_RTCL_W   0x015 /* .6. 601 RTC Lower - Write */
 
#define SPR_DEC   0x016 /* .68 DECrementer register */
 
#define SPR_SDR1   0x019 /* .68 Page table base address register */
 
#define SPR_SRR0   0x01a /* 468 Save/Restore Register 0 */
 
#define SPR_SRR1   0x01b /* 468 Save/Restore Register 1 */
 
#define SPR_EIE   0x050 /* ..8 Exception Interrupt ??? */
 
#define SPR_EID   0x051 /* ..8 Exception Interrupt ??? */
 
#define SPR_NRI   0x052 /* ..8 Exception Interrupt ??? */
 
#define SPR_USPRG0   0x100 /* 4.. User SPR General 0 */
 
#define SPR_VRSAVE   0x100 /* .6. AltiVec VRSAVE */
 
#define SPR_SPRG0   0x110 /* 468 SPR General 0 */
 
#define SPR_SPRG1   0x111 /* 468 SPR General 1 */
 
#define SPR_SPRG2   0x112 /* 468 SPR General 2 */
 
#define SPR_SPRG3   0x113 /* 468 SPR General 3 */
 
#define SPR_SPRG4   0x114 /* 4.. SPR General 4 */
 
#define SPR_SPRG5   0x115 /* 4.. SPR General 5 */
 
#define SPR_SPRG6   0x116 /* 4.. SPR General 6 */
 
#define SPR_SPRG7   0x117 /* 4.. SPR General 7 */
 
#define SPR_ASR   0x118 /* ... Address Space Register (PPC64) */
 
#define SPR_EAR   0x11a /* .68 External Access Register */
 
#define SPR_TBL   0x11c /* 468 Time Base Lower */
 
#define SPR_TBU   0x11d /* 468 Time Base Upper */
 
#define SPR_PVR   0x11f /* 468 Processor Version Register */
 
#define MPC601   0x0001
 
#define MPC603   0x0003
 
#define MPC604   0x0004
 
#define MPC602   0x0005
 
#define MPC603e   0x0006
 
#define MPC603ev   0x0007
 
#define MPC750   0x0008
 
#define MPC604e   0x0009
 
#define MPC604ev   0x000a
 
#define MPC7400   0x000c
 
#define MPC620   0x0014
 
#define IBM403   0x0020
 
#define IBM401A1   0x0021
 
#define IBM401B2   0x0022
 
#define IBM401C2   0x0023
 
#define IBM401D2   0x0024
 
#define IBM401E2   0x0025
 
#define IBM401F2   0x0026
 
#define IBM401G2   0x0027
 
#define IBMPOWER3   0x0041
 
#define MPC860   0x0050
 
#define MPC8240   0x0081
 
#define IBM405GP   0x4011
 
#define IBM405GPR   0x5091
 
#define IBM405L   0x4161
 
#define IBM750FX   0x7000
 
#define MPC7450   0x8000
 
#define MPC7455   0x8001
 
#define MPC7457   0x8002
 
#define MPC7447A   0x8003
 
#define MPC7448   0x8004
 
#define MPC745X_P(v)   ((v & 0xFFF8) == 0x8000)
 
#define MPC7410   0x800c
 
#define MPC8245   0x8081
 
#define SPR_HSPRG0   0x130
 
#define SPR_HSPRG1   0x131
 
#define SPR_HDEC   0x136
 
#define SPR_HIOR   0x137
 
#define SPR_RMOR   0x138
 
#define SPR_HRMOR   0x139
 
#define SPR_HSRR0   0x13a
 
#define SPR_HSRR1   0x13b
 
#define SPR_IBAT0U   0x210 /* .68 Instruction BAT Reg 0 Upper */
 
#define SPR_IBAT0L   0x211 /* .6. Instruction BAT Reg 0 Lower */
 
#define SPR_IBAT1U   0x212 /* .6. Instruction BAT Reg 1 Upper */
 
#define SPR_IBAT1L   0x213 /* .6. Instruction BAT Reg 1 Lower */
 
#define SPR_IBAT2U   0x214 /* .6. Instruction BAT Reg 2 Upper */
 
#define SPR_IBAT2L   0x215 /* .6. Instruction BAT Reg 2 Lower */
 
#define SPR_IBAT3U   0x216 /* .6. Instruction BAT Reg 3 Upper */
 
#define SPR_IBAT3L   0x217 /* .6. Instruction BAT Reg 3 Lower */
 
#define SPR_DBAT0U   0x218 /* .6. Data BAT Reg 0 Upper */
 
#define SPR_DBAT0L   0x219 /* .6. Data BAT Reg 0 Lower */
 
#define SPR_DBAT1U   0x21a /* .6. Data BAT Reg 1 Upper */
 
#define SPR_DBAT1L   0x21b /* .6. Data BAT Reg 1 Lower */
 
#define SPR_DBAT2U   0x21c /* .6. Data BAT Reg 2 Upper */
 
#define SPR_DBAT2L   0x21d /* .6. Data BAT Reg 2 Lower */
 
#define SPR_DBAT3U   0x21e /* .6. Data BAT Reg 3 Upper */
 
#define SPR_DBAT3L   0x21f /* .6. Data BAT Reg 3 Lower */
 
#define SPR_IC_CST   0x230 /* ..8 Instruction Cache CSR */
 
#define IC_CST_IEN   0x80000000 /* I cache is ENabled (RO) */
 
#define IC_CST_CMD_INVALL   0x0c000000 /* I cache invalidate all */
 
#define IC_CST_CMD_UNLOCKALL   0x0a000000 /* I cache unlock all */
 
#define IC_CST_CMD_UNLOCK   0x08000000 /* I cache unlock block */
 
#define IC_CST_CMD_LOADLOCK   0x06000000 /* I cache load & lock block */
 
#define IC_CST_CMD_DISABLE   0x04000000 /* I cache disable */
 
#define IC_CST_CMD_ENABLE   0x02000000 /* I cache enable */
 
#define IC_CST_CCER1   0x00200000 /* I cache error type 1 (RO) */
 
#define IC_CST_CCER2   0x00100000 /* I cache error type 2 (RO) */
 
#define IC_CST_CCER3   0x00080000 /* I cache error type 3 (RO) */
 
#define SPR_IBAT4U   0x230 /* .6. Instruction BAT Reg 4 Upper */
 
#define SPR_IC_ADR   0x231 /* ..8 Instruction Cache Address */
 
#define SPR_IBAT4L   0x231 /* .6. Instruction BAT Reg 4 Lower */
 
#define SPR_IC_DAT   0x232 /* ..8 Instruction Cache Data */
 
#define SPR_IBAT5U   0x232 /* .6. Instruction BAT Reg 5 Upper */
 
#define SPR_IBAT5L   0x233 /* .6. Instruction BAT Reg 5 Lower */
 
#define SPR_IBAT6U   0x234 /* .6. Instruction BAT Reg 6 Upper */
 
#define SPR_IBAT6L   0x235 /* .6. Instruction BAT Reg 6 Lower */
 
#define SPR_IBAT7U   0x236 /* .6. Instruction BAT Reg 7 Upper */
 
#define SPR_IBAT7L   0x237 /* .6. Instruction BAT Reg 7 Lower */
 
#define SPR_DC_CST   0x238 /* ..8 Data Cache CSR */
 
#define DC_CST_DEN   0x80000000 /* D cache ENabled (RO) */
 
#define DC_CST_DFWT   0x40000000 /* D cache Force Write-Thru (RO) */
 
#define DC_CST_LES   0x20000000 /* D cache Little Endian Swap (RO) */
 
#define DC_CST_CMD_FLUSH   0x0e000000 /* D cache invalidate all */
 
#define DC_CST_CMD_INVALL   0x0c000000 /* D cache invalidate all */
 
#define DC_CST_CMD_UNLOCKALL   0x0a000000 /* D cache unlock all */
 
#define DC_CST_CMD_UNLOCK   0x08000000 /* D cache unlock block */
 
#define DC_CST_CMD_CLRLESWAP   0x07000000 /* D cache clr little-endian swap */
 
#define DC_CST_CMD_LOADLOCK   0x06000000 /* D cache load & lock block */
 
#define DC_CST_CMD_SETLESWAP   0x05000000 /* D cache set little-endian swap */
 
#define DC_CST_CMD_DISABLE   0x04000000 /* D cache disable */
 
#define DC_CST_CMD_CLRFWT   0x03000000 /* D cache clear forced write-thru */
 
#define DC_CST_CMD_ENABLE   0x02000000 /* D cache enable */
 
#define DC_CST_CMD_SETFWT   0x01000000 /* D cache set forced write-thru */
 
#define DC_CST_CCER1   0x00200000 /* D cache error type 1 (RO) */
 
#define DC_CST_CCER2   0x00100000 /* D cache error type 2 (RO) */
 
#define DC_CST_CCER3   0x00080000 /* D cache error type 3 (RO) */
 
#define SPR_DBAT4U   0x238 /* .6. Data BAT Reg 4 Upper */
 
#define SPR_DC_ADR   0x231 /* ..8 Data Cache Address */
 
#define SPR_DBAT4L   0x239 /* .6. Data BAT Reg 4 Lower */
 
#define SPR_DC_DAT   0x232 /* ..8 Data Cache Data */
 
#define SPR_DBAT5U   0x23a /* .6. Data BAT Reg 5 Upper */
 
#define SPR_DBAT5L   0x23b /* .6. Data BAT Reg 5 Lower */
 
#define SPR_DBAT6U   0x23c /* .6. Data BAT Reg 6 Upper */
 
#define SPR_DBAT6L   0x23d /* .6. Data BAT Reg 6 Lower */
 
#define SPR_DBAT7U   0x23e /* .6. Data BAT Reg 7 Upper */
 
#define SPR_DBAT7L   0x23f /* .6. Data BAT Reg 7 Lower */
 
#define SPR_MI_CTR   0x310 /* ..8 IMMU control */
 
#define Mx_CTR_GPM   0x80000000 /* Group Protection Mode */
 
#define Mx_CTR_PPM   0x40000000 /* Page Protection Mode */
 
#define Mx_CTR_CIDEF   0x20000000 /* Cache-Inhibit DEFault */
 
#define MD_CTR_WTDEF   0x20000000 /* Write-Through DEFault */
 
#define Mx_CTR_RSV4   0x08000000 /* Reserve 4 TLB entries */
 
#define MD_CTR_TWAM   0x04000000 /* TableWalk Assist Mode */
 
#define Mx_CTR_PPCS   0x02000000 /* Priv/user state compare mode */
 
#define Mx_CTR_TLB_INDX   0x000001f0 /* TLB index mask */
 
#define Mx_CTR_TLB_INDX_BITPOS   8 /* TLB index shift */
 
#define SPR_MI_AP   0x312 /* ..8 IMMU access protection */
 
#define Mx_GP_SUPER(n)   (0 << (2*(15-(n)))) /* access is supervisor */
 
#define Mx_GP_PAGE   (1 << (2*(15-(n)))) /* access is page protect */
 
#define Mx_GP_SWAPPED   (2 << (2*(15-(n)))) /* access is swapped */
 
#define Mx_GP_USER   (3 << (2*(15-(n)))) /* access is user */
 
#define SPR_MI_EPN   0x313 /* ..8 IMMU effective number */
 
#define Mx_EPN_EPN   0xfffff000 /* Effective Page Number mask */
 
#define Mx_EPN_EV   0x00000020 /* Entry Valid */
 
#define Mx_EPN_ASID   0x0000000f /* Address Space ID */
 
#define SPR_MI_TWC   0x315 /* ..8 IMMU tablewalk control */
 
#define MD_TWC_L2TB   0xfffff000 /* Level-2 Tablewalk Base */
 
#define Mx_TWC_APG   0x000001e0 /* Access Protection Group */
 
#define Mx_TWC_G   0x00000010 /* Guarded memory */
 
#define Mx_TWC_PS   0x0000000c /* Page Size (L1) */
 
#define MD_TWC_WT   0x00000002 /* Write-Through */
 
#define Mx_TWC_V   0x00000001 /* Entry Valid */
 
#define SPR_MI_RPN   0x316 /* ..8 IMMU real (phys) page number */
 
#define Mx_RPN_RPN   0xfffff000 /* Real Page Number */
 
#define Mx_RPN_PP   0x00000ff0 /* Page Protection */
 
#define Mx_RPN_SPS   0x00000008 /* Small Page Size */
 
#define Mx_RPN_SH   0x00000004 /* SHared page */
 
#define Mx_RPN_CI   0x00000002 /* Cache Inhibit */
 
#define Mx_RPN_V   0x00000001 /* Valid */
 
#define SPR_MD_CTR   0x318 /* ..8 DMMU control */
 
#define SPR_M_CASID   0x319 /* ..8 CASID */
 
#define M_CASID   0x0000000f /* Current AS Id */
 
#define SPR_MD_AP   0x31a /* ..8 DMMU access protection */
 
#define SPR_MD_EPN   0x31b /* ..8 DMMU effective number */
 
#define SPR_M_TWB   0x31c /* ..8 MMU tablewalk base */
 
#define M_TWB_L1TB   0xfffff000 /* level-1 translation base */
 
#define M_TWB_L1INDX   0x00000ffc /* level-1 index */
 
#define SPR_MD_TWC   0x31d /* ..8 DMMU tablewalk control */
 
#define SPR_MD_RPN   0x31e /* ..8 DMMU real (phys) page number */
 
#define SPR_MD_TW   0x31f /* ..8 MMU tablewalk scratch */
 
#define SPR_MI_CAM   0x330 /* ..8 IMMU CAM entry read */
 
#define SPR_MI_RAM0   0x331 /* ..8 IMMU RAM entry read reg 0 */
 
#define SPR_MI_RAM1   0x332 /* ..8 IMMU RAM entry read reg 1 */
 
#define SPR_MD_CAM   0x338 /* ..8 IMMU CAM entry read */
 
#define SPR_MD_RAM0   0x339 /* ..8 IMMU RAM entry read reg 0 */
 
#define SPR_MD_RAM1   0x33a /* ..8 IMMU RAM entry read reg 1 */
 
#define SPR_UMMCR2   0x3a0 /* .6. User Monitor Mode Control Register 2 */
 
#define SPR_UMMCR0   0x3a8 /* .6. User Monitor Mode Control Register 0 */
 
#define SPR_USIA   0x3ab /* .6. User Sampled Instruction Address */
 
#define SPR_UMMCR1   0x3ac /* .6. User Monitor Mode Control Register 1 */
 
#define SPR_ZPR   0x3b0 /* 4.. Zone Protection Register */
 
#define SPR_MMCR2   0x3b0 /* .6. Monitor Mode Control Register 2 */
 
#define SPR_MMCR2_THRESHMULT_32   0x80000000 /* Multiply MMCR0 threshold by 32 */
 
#define SPR_MMCR2_THRESHMULT_2   0x00000000 /* Multiply MMCR0 threshold by 2 */
 
#define SPR_PID   0x3b1 /* 4.. Process ID */
 
#define SPR_PMC5   0x3b1 /* .6. Performance Counter Register 5 */
 
#define SPR_PMC6   0x3b2 /* .6. Performance Counter Register 6 */
 
#define SPR_CCR0   0x3b3 /* 4.. Core Configuration Register 0 */
 
#define SPR_IAC3   0x3b4 /* 4.. Instruction Address Compare 3 */
 
#define SPR_IAC4   0x3b5 /* 4.. Instruction Address Compare 4 */
 
#define SPR_DVC1   0x3b6 /* 4.. Data Value Compare 1 */
 
#define SPR_DVC2   0x3b7 /* 4.. Data Value Compare 2 */
 
#define SPR_MMCR0   0x3b8 /* .6. Monitor Mode Control Register 0 */
 
#define MMCR0_FC   0x80000000 /* Freeze counters */
 
#define MMCR0_FCS   0x40000000 /* Freeze counters in supervisor mode */
 
#define MMCR0_FCP   0x20000000 /* Freeze counters in user mode */
 
#define MMCR0_FCM1   0x10000000 /* Freeze counters when mark=1 */
 
#define MMCR0_FCM0   0x08000000 /* Freeze counters when mark=0 */
 
#define MMCR0_PMXE   0x04000000 /* Enable PM interrupt */
 
#define MMCR0_FCECE   0x02000000 /* Freeze counters after event */
 
#define MMCR0_TBSEL_15   0x01800000 /* Count bit 15 of TBL */
 
#define MMCR0_TBSEL_19   0x01000000 /* Count bit 19 of TBL */
 
#define MMCR0_TBSEL_23   0x00800000 /* Count bit 23 of TBL */
 
#define MMCR0_TBSEL_31   0x00000000 /* Count bit 31 of TBL */
 
#define MMCR0_TBEE   0x00400000 /* Time-base event enable */
 
#define MMCRO_THRESHOLD(x)   ((x) << 16) /* Threshold value */
 
#define MMCR0_PMC1CE   0x00008000 /* PMC1 condition enable */
 
#define MMCR0_PMCNCE   0x00004000 /* PMCn condition enable */
 
#define MMCR0_TRIGGER   0x00002000 /* Trigger */
 
#define MMCR0_PMC1SEL(x)   ((x) << 6) /* PMC1 selector */
 
#define MMCR0_PMC2SEL(x)   ((x) << 0) /* PMC2 selector */
 
#define SPR_SGR   0x3b9 /* 4.. Storage Guarded Register */
 
#define SPR_PMC1   0x3b9 /* .6. Performance Counter Register 1 */
 
#define SPR_DCWR   0x3ba /* 4.. Data Cache Write-through Register */
 
#define SPR_PMC2   0x3ba /* .6. Performance Counter Register 2 */
 
#define SPR_SLER   0x3bb /* 4.. Storage Little Endian Register */
 
#define SPR_SIA   0x3bb /* .6. Sampled Instruction Address */
 
#define SPR_MMCR1   0x3bc /* .6. Monitor Mode Control Register 2 */
 
#define MMCR1_PMC3SEL(x)   ((x) << 27) /* PMC 3 selector */
 
#define MMCR1_PMC4SEL(x)   ((x) << 22) /* PMC 4 selector */
 
#define MMCR1_PMC5SEL(x)   ((x) << 17) /* PMC 5 selector */
 
#define MMCR1_PMC6SEL(x)   ((x) << 11) /* PMC 6 selector */
 
#define SPR_SU0R   0x3bc /* 4.. Storage User-defined 0 Register */
 
#define SPR_DBCR1   0x3bd /* 4.. Debug Control Register 1 */
 
#define SPR_PMC3   0x3bd /* .6. Performance Counter Register 3 */
 
#define SPR_PMC4   0x3be /* .6. Performance Counter Register 4 */
 
#define SPR_DMISS   0x3d0 /* .68 Data TLB Miss Address Register */
 
#define SPR_DCMP   0x3d1 /* .68 Data TLB Compare Register */
 
#define SPR_HASH1   0x3d2 /* .68 Primary Hash Address Register */
 
#define SPR_ICDBDR   0x3d3 /* 4.. Instruction Cache Debug Data Register */
 
#define SPR_HASH2   0x3d3 /* .68 Secondary Hash Address Register */
 
#define SPR_ESR   0x3d4 /* 4.. Exception Syndrome Register */
 
#define ESR_MCI   0x80000000 /* Machine check - instruction */
 
#define ESR_PIL   0x08000000 /* Program interrupt - illegal */
 
#define ESR_PPR   0x04000000 /* Program interrupt - privileged */
 
#define ESR_PTR   0x02000000 /* Program interrupt - trap */
 
#define ESR_DST   0x00800000 /* Data storage interrupt - store fault */
 
#define ESR_DIZ   0x00800000 /* Data/instruction storage interrupt - zone fault */
 
#define ESR_U0F   0x00008000 /* Data storage interrupt - U0 fault */
 
#define SPR_IMISS   0x3d4 /* .68 Instruction TLB Miss Address Register */
 
#define SPR_TLBMISS   0x3d4 /* .6. TLB Miss Address Register */
 
#define SPR_DEAR   0x3d5 /* 4.. Data Error Address Register */
 
#define SPR_ICMP   0x3d5 /* .68 Instruction TLB Compare Register */
 
#define SPR_PTEHI   0x3d5 /* .6. Instruction TLB Compare Register */
 
#define SPR_EVPR   0x3d6 /* 4.. Exception Vector Prefix Register */
 
#define SPR_RPA   0x3d6 /* .68 Required Physical Address Register */
 
#define SPR_PTELO   0x3d6 /* .6. Required Physical Address Register */
 
#define SPR_TSR   0x3d8 /* 4.. Timer Status Register */
 
#define TSR_ENW   0x80000000 /* Enable Next Watchdog */
 
#define TSR_WIS   0x40000000 /* Watchdog Interrupt Status */
 
#define TSR_WRS_MASK   0x30000000 /* Watchdog Reset Status */
 
#define TSR_WRS_NONE   0x00000000 /* No watchdog reset has occurred */
 
#define TSR_WRS_CORE   0x10000000 /* Core reset was forced by the watchdog */
 
#define TSR_WRS_CHIP   0x20000000 /* Chip reset was forced by the watchdog */
 
#define TSR_WRS_SYSTEM   0x30000000 /* System reset was forced by the watchdog */
 
#define TSR_PIS   0x08000000 /* PIT Interrupt Status */
 
#define TSR_FIS   0x04000000 /* FIT Interrupt Status */
 
#define SPR_TCR   0x3da /* 4.. Timer Control Register */
 
#define TCR_WP_MASK   0xc0000000 /* Watchdog Period mask */
 
#define TCR_WP_2_17   0x00000000 /* 2**17 clocks */
 
#define TCR_WP_2_21   0x40000000 /* 2**21 clocks */
 
#define TCR_WP_2_25   0x80000000 /* 2**25 clocks */
 
#define TCR_WP_2_29   0xc0000000 /* 2**29 clocks */
 
#define TCR_WRC_MASK   0x30000000 /* Watchdog Reset Control mask */
 
#define TCR_WRC_NONE   0x00000000 /* No watchdog reset */
 
#define TCR_WRC_CORE   0x10000000 /* Core reset */
 
#define TCR_WRC_CHIP   0x20000000 /* Chip reset */
 
#define TCR_WRC_SYSTEM   0x30000000 /* System reset */
 
#define TCR_WIE   0x08000000 /* Watchdog Interrupt Enable */
 
#define TCR_PIE   0x04000000 /* PIT Interrupt Enable */
 
#define TCR_FP_MASK   0x03000000 /* FIT Period */
 
#define TCR_FP_2_9   0x00000000 /* 2**9 clocks */
 
#define TCR_FP_2_13   0x01000000 /* 2**13 clocks */
 
#define TCR_FP_2_17   0x02000000 /* 2**17 clocks */
 
#define TCR_FP_2_21   0x03000000 /* 2**21 clocks */
 
#define TCR_FIE   0x00800000 /* FIT Interrupt Enable */
 
#define TCR_ARE   0x00400000 /* Auto Reload Enable */
 
#define SPR_PIT   0x3db /* 4.. Programmable Interval Timer */
 
#define SPR_SRR2   0x3de /* 4.. Save/Restore Register 2 */
 
#define SPR_SRR3   0x3df /* 4.. Save/Restore Register 3 */
 
#define SPR_DBSR   0x3f0 /* 4.. Debug Status Register */
 
#define DBSR_IC   0x80000000 /* Instruction completion debug event */
 
#define DBSR_BT   0x40000000 /* Branch Taken debug event */
 
#define DBSR_EDE   0x20000000 /* Exception debug event */
 
#define DBSR_TIE   0x10000000 /* Trap Instruction debug event */
 
#define DBSR_UDE   0x08000000 /* Unconditional debug event */
 
#define DBSR_IA1   0x04000000 /* IAC1 debug event */
 
#define DBSR_IA2   0x02000000 /* IAC2 debug event */
 
#define DBSR_DR1   0x01000000 /* DAC1 Read debug event */
 
#define DBSR_DW1   0x00800000 /* DAC1 Write debug event */
 
#define DBSR_DR2   0x00400000 /* DAC2 Read debug event */
 
#define DBSR_DW2   0x00200000 /* DAC2 Write debug event */
 
#define DBSR_IDE   0x00100000 /* Imprecise debug event */
 
#define DBSR_IA3   0x00080000 /* IAC3 debug event */
 
#define DBSR_IA4   0x00040000 /* IAC4 debug event */
 
#define DBSR_MRR   0x00000300 /* Most recent reset */
 
#define SPR_HID0   0x3f0 /* ..8 Hardware Implementation Register 0 */
 
#define SPR_HID1   0x3f1 /* ..8 Hardware Implementation Register 1 */
 
#define SPR_DBCR0   0x3f2 /* 4.. Debug Control Register 0 */
 
#define DBCR0_EDM   0x80000000 /* External Debug Mode */
 
#define DBCR0_IDM   0x40000000 /* Internal Debug Mode */
 
#define DBCR0_RST_MASK   0x30000000 /* ReSeT */
 
#define DBCR0_RST_NONE   0x00000000 /* No action */
 
#define DBCR0_RST_CORE   0x10000000 /* Core reset */
 
#define DBCR0_RST_CHIP   0x20000000 /* Chip reset */
 
#define DBCR0_RST_SYSTEM   0x30000000 /* System reset */
 
#define DBCR0_IC   0x08000000 /* Instruction Completion debug event */
 
#define DBCR0_BT   0x04000000 /* Branch Taken debug event */
 
#define DBCR0_EDE   0x02000000 /* Exception Debug Event */
 
#define DBCR0_TDE   0x01000000 /* Trap Debug Event */
 
#define DBCR0_IA1   0x00800000 /* IAC (Instruction Address Compare) 1 debug event */
 
#define DBCR0_IA2   0x00400000 /* IAC 2 debug event */
 
#define DBCR0_IA12   0x00200000 /* Instruction Address Range Compare 1-2 */
 
#define DBCR0_IA12X   0x00100000 /* IA12 eXclusive */
 
#define DBCR0_IA3   0x00080000 /* IAC 3 debug event */
 
#define DBCR0_IA4   0x00040000 /* IAC 4 debug event */
 
#define DBCR0_IA34   0x00020000 /* Instruction Address Range Compare 3-4 */
 
#define DBCR0_IA34X   0x00010000 /* IA34 eXclusive */
 
#define DBCR0_IA12T   0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */
 
#define DBCR0_IA34T   0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */
 
#define DBCR0_FT   0x00000001 /* Freeze Timers on debug event */
 
#define SPR_IABR   0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */
 
#define SPR_HID2   0x3f3 /* ..8 Hardware Implementation Register 2 */
 
#define SPR_IAC1   0x3f4 /* 4.. Instruction Address Compare 1 */
 
#define SPR_IAC2   0x3f5 /* 4.. Instruction Address Compare 2 */
 
#define SPR_DABR   0x3f5 /* .6. Data Address Breakpoint Register */
 
#define SPR_DAC1   0x3f6 /* 4.. Data Address Compare 1 */
 
#define SPR_MSSCR0   0x3f6 /* .6. Memory SubSystem Control Register */
 
#define MSSCR0_SHDEN   0x80000000 /* 0: Shared-state enable */
 
#define MSSCR0_SHDPEN3   0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */
 
#define MSSCR0_L1INTVEN   0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */
 
#define MSSCR0_L2INTVEN   0x07000000 /* 5-7: L2 data cache ~HIT intervention enable */
 
#define MSSCR0_DL1HWF   0x00800000 /* 8: L1 data cache hardware flush */
 
#define MSSCR0_MBO   0x00400000 /* 9: must be one */
 
#define MSSCR0_EMODE   0x00200000 /* 10: MPX bus mode (read-only) */
 
#define MSSCR0_ABD   0x00100000 /* 11: address bus driven (read-only) */
 
#define MSSCR0_BMODE   0x0000c000 /* 16-17: Bus Mode (read-only) (7450) */
 
#define MSSCR0_ID   0x00000040 /* 26: Processor ID */
 
#define MSSCR0_L2PFE   0x00000003 /* 30-31: L2 prefetching enabled (7450) */
 
#define SPR_DAC2   0x3f7 /* 4.. Data Address Compare 2 */
 
#define SPR_L2PM   0x3f8 /* .6. L2 Private Memory Control Register */
 
#define SPR_L2CR   0x3f9 /* .6. L2 Control Register */
 
#define L2CR_L2E   0x80000000 /* 0: L2 enable */
 
#define L2CR_L2PE   0x40000000 /* 1: L2 data parity enable */
 
#define L2CR_L2SIZ   0x30000000 /* 2-3: L2 size */
 
#define L2SIZ_2M   0x00000000
 
#define L2SIZ_256K   0x10000000
 
#define L2SIZ_512K   0x20000000
 
#define L2SIZ_1M   0x30000000
 
#define L2CR_L2CLK   0x0e000000 /* 4-6: L2 clock ratio */
 
#define L2CLK_DIS   0x00000000 /* disable L2 clock */
 
#define L2CLK_10   0x02000000 /* core clock / 1 */
 
#define L2CLK_15   0x04000000 /* / 1.5 */
 
#define L2CLK_35   0x06000000 /* / 3.5 */
 
#define L2CLK_20   0x08000000 /* / 2 */
 
#define L2CLK_25   0x0a000000 /* / 2.5 */
 
#define L2CLK_30   0x0c000000 /* / 3 */
 
#define L2CLK_40   0x0e000000 /* / 4 */
 
#define L2CR_L2RAM   0x01800000 /* 7-8: L2 RAM type */
 
#define L2RAM_FLOWTHRU_BURST   0x00000000
 
#define L2RAM_PIPELINE_BURST   0x01000000
 
#define L2RAM_PIPELINE_LATE   0x01800000
 
#define L2CR_L2DO
 
#define L2CR_L2I   0x00200000 /* 10: L2 global invalidate. */
 
#define L2CR_L2CTL
 
#define L2CR_L2WT   0x00080000 /* 12: L2 write-through. */
 
#define L2CR_L2TS   0x00040000 /* 13: L2 test support. */
 
#define L2CR_L2OH   0x00030000 /* 14-15: L2 output hold. */
 
#define L2CR_L2SL   0x00008000 /* 16: L2 DLL slow. */
 
#define L2CR_L2DF   0x00004000 /* 17: L2 differential clock. */
 
#define L2CR_L2BYP   0x00002000 /* 18: L2 DLL bypass. */
 
#define L2CR_L2FA   0x00001000 /* 19: L2 flush assist (for software flush). */
 
#define L2CR_L2HWF   0x00000800 /* 20: L2 hardware flush. */
 
#define L2CR_L2IO   0x00000400 /* 21: L2 instruction-only. */
 
#define L2CR_L2CLKSTP   0x00000200 /* 22: L2 clock stop. */
 
#define L2CR_L2DRO   0x00000100 /* 23: L2DLL rollover checkstop enable. */
 
#define L2CR_L2IP   0x00000001 /* 31: L2 global invalidate in */
 
#define SPR_L3CR   0x3fa /* .6. L3 Control Register */
 
#define L3CR_RESERVED   0x0438003a /* Reserved bits in L3CR */
 
#define L3CR_L3E   0x80000000 /* 0: L3 enable */
 
#define L3CR_L3PE   0x40000000 /* 1: L3 data parity checking enable */
 
#define L3CR_L3APE   0x20000000 /* 2: L3 address parity checking enable */
 
#define L3CR_L3SIZ   0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */
 
#define L3SIZ_1M   0x00000000
 
#define L3SIZ_2M   0x10000000
 
#define L3CR_L3CLKEN   0x08000000 /* 4: Enables the L3_CLK[0:1] signals */
 
#define L3CR_L3CLK   0x03800000 /* 6-8: L3 clock ratio */
 
#define L3CLK_60   0x00000000 /* core clock / 6 */
 
#define L3CLK_20   0x01000000 /* / 2 */
 
#define L3CLK_25   0x01800000 /* / 2.5 */
 
#define L3CLK_30   0x02000000 /* / 3 */
 
#define L3CLK_35   0x02800000 /* / 3.5 */
 
#define L3CLK_40   0x03000000 /* / 4 */
 
#define L3CLK_50   0x03800000 /* / 5 */
 
#define L3CR_L3IO   0x00400000 /* 9: L3 instruction-only mode */
 
#define L3CR_L3SPO   0x00040000 /* 13: L3 sample point override */
 
#define L3CR_L3CKSP   0x00030000 /* 14-15: L3 clock sample point */
 
#define L3CKSP_2   0x00000000 /* 2 clocks */
 
#define L3CKSP_3   0x00010000 /* 3 clocks */
 
#define L3CKSP_4   0x00020000 /* 4 clocks */
 
#define L3CKSP_5   0x00030000 /* 5 clocks */
 
#define L3CR_L3PSP   0x0000e000 /* 16-18: L3 P-clock sample point */
 
#define L3PSP_0   0x00000000 /* 0 clocks */
 
#define L3PSP_1   0x00002000 /* 1 clocks */
 
#define L3PSP_2   0x00004000 /* 2 clocks */
 
#define L3PSP_3   0x00006000 /* 3 clocks */
 
#define L3PSP_4   0x00008000 /* 4 clocks */
 
#define L3PSP_5   0x0000a000 /* 5 clocks */
 
#define L3CR_L3REP   0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */
 
#define L3CR_L3HWF   0x00000800 /* 20: L3 hardware flush */
 
#define L3CR_L3I   0x00000400 /* 21: L3 global invalidate */
 
#define L3CR_L3RT   0x00000300 /* 22-23: L3 SRAM type */
 
#define L3RT_MSUG2_DDR   0x00000000 /* MSUG2 DDR SRAM */
 
#define L3RT_PIPELINE_LATE   0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */
 
#define L3RT_PB2_SRAM   0x00000300 /* PB2 SRAM */
 
#define L3CR_L3NIRCA   0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */
 
#define L3CR_L3DO   0x00000040 /* 25: L3 data-only mode */
 
#define L3CR_PMEN   0x00000004 /* 29: Private memory enable */
 
#define L3CR_PMSIZ   0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */
 
#define SPR_DCCR   0x3fa /* 4.. Data Cache Cachability Register */
 
#define SPR_ICCR   0x3fb /* 4.. Instruction Cache Cachability Register */
 
#define SPR_THRM1   0x3fc /* .6. Thermal Management Register */
 
#define SPR_THRM2   0x3fd /* .6. Thermal Management Register */
 
#define SPR_THRM_TIN   0x80000000 /* Thermal interrupt bit (RO) */
 
#define SPR_THRM_TIV   0x40000000 /* Thermal interrupt valid (RO) */
 
#define SPR_THRM_THRESHOLD(x)   ((x) << 23) /* Thermal sensor threshold */
 
#define SPR_THRM_TID   0x00000004 /* Thermal interrupt direction */
 
#define SPR_THRM_TIE   0x00000002 /* Thermal interrupt enable */
 
#define SPR_THRM_VALID   0x00000001 /* Valid bit */
 
#define SPR_THRM3   0x3fe /* .6. Thermal Management Register */
 
#define SPR_THRM_TIMER(x)   ((x) << 1) /* Sampling interval timer */
 
#define SPR_THRM_ENABLE   0x00000001 /* TAU Enable */
 
#define SPR_FPECR   0x3fe /* .6. Floating-Point Exception Cause Register */
 
#define SPR_PIR   0x3ff /* .6. Processor Identification Register */
 
#define TBR_TBL   0x10c /* 468 Time Base Lower */
 
#define TBR_TBU   0x10d /* 468 Time Base Upper */
 
#define PMC_OVERFLOW   0x80000000 /* Counter has overflowed */
 
#define PMCN_NONE   0 /* Count nothing */
 
#define PMCN_CYCLES   1 /* Processor cycles */
 
#define PMCN_ICOMP   2 /* Instructions completed */
 
#define PMCN_TBLTRANS   3 /* TBL bit transitions */
 
#define PCMN_IDISPATCH   4 /* Instructions dispatched */
 

Macro Definition Documentation

◆ DBCR0_BT

#define DBCR0_BT   0x04000000 /* Branch Taken debug event */

Definition at line 366 of file ppc_spr.h.

◆ DBCR0_EDE

#define DBCR0_EDE   0x02000000 /* Exception Debug Event */

Definition at line 367 of file ppc_spr.h.

◆ DBCR0_EDM

#define DBCR0_EDM   0x80000000 /* External Debug Mode */

Definition at line 358 of file ppc_spr.h.

◆ DBCR0_FT

#define DBCR0_FT   0x00000001 /* Freeze Timers on debug event */

Definition at line 379 of file ppc_spr.h.

◆ DBCR0_IA1

#define DBCR0_IA1   0x00800000 /* IAC (Instruction Address Compare) 1 debug event */

Definition at line 369 of file ppc_spr.h.

◆ DBCR0_IA12

#define DBCR0_IA12   0x00200000 /* Instruction Address Range Compare 1-2 */

Definition at line 371 of file ppc_spr.h.

◆ DBCR0_IA12T

#define DBCR0_IA12T   0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */

Definition at line 377 of file ppc_spr.h.

◆ DBCR0_IA12X

#define DBCR0_IA12X   0x00100000 /* IA12 eXclusive */

Definition at line 372 of file ppc_spr.h.

◆ DBCR0_IA2

#define DBCR0_IA2   0x00400000 /* IAC 2 debug event */

Definition at line 370 of file ppc_spr.h.

◆ DBCR0_IA3

#define DBCR0_IA3   0x00080000 /* IAC 3 debug event */

Definition at line 373 of file ppc_spr.h.

◆ DBCR0_IA34

#define DBCR0_IA34   0x00020000 /* Instruction Address Range Compare 3-4 */

Definition at line 375 of file ppc_spr.h.

◆ DBCR0_IA34T

#define DBCR0_IA34T   0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */

Definition at line 378 of file ppc_spr.h.

◆ DBCR0_IA34X

#define DBCR0_IA34X   0x00010000 /* IA34 eXclusive */

Definition at line 376 of file ppc_spr.h.

◆ DBCR0_IA4

#define DBCR0_IA4   0x00040000 /* IAC 4 debug event */

Definition at line 374 of file ppc_spr.h.

◆ DBCR0_IC

#define DBCR0_IC   0x08000000 /* Instruction Completion debug event */

Definition at line 365 of file ppc_spr.h.

◆ DBCR0_IDM

#define DBCR0_IDM   0x40000000 /* Internal Debug Mode */

Definition at line 359 of file ppc_spr.h.

◆ DBCR0_RST_CHIP

#define DBCR0_RST_CHIP   0x20000000 /* Chip reset */

Definition at line 363 of file ppc_spr.h.

◆ DBCR0_RST_CORE

#define DBCR0_RST_CORE   0x10000000 /* Core reset */

Definition at line 362 of file ppc_spr.h.

◆ DBCR0_RST_MASK

#define DBCR0_RST_MASK   0x30000000 /* ReSeT */

Definition at line 360 of file ppc_spr.h.

◆ DBCR0_RST_NONE

#define DBCR0_RST_NONE   0x00000000 /* No action */

Definition at line 361 of file ppc_spr.h.

◆ DBCR0_RST_SYSTEM

#define DBCR0_RST_SYSTEM   0x30000000 /* System reset */

Definition at line 364 of file ppc_spr.h.

◆ DBCR0_TDE

#define DBCR0_TDE   0x01000000 /* Trap Debug Event */

Definition at line 368 of file ppc_spr.h.

◆ DBSR_BT

#define DBSR_BT   0x40000000 /* Branch Taken debug event */

Definition at line 341 of file ppc_spr.h.

◆ DBSR_DR1

#define DBSR_DR1   0x01000000 /* DAC1 Read debug event */

Definition at line 347 of file ppc_spr.h.

◆ DBSR_DR2

#define DBSR_DR2   0x00400000 /* DAC2 Read debug event */

Definition at line 349 of file ppc_spr.h.

◆ DBSR_DW1

#define DBSR_DW1   0x00800000 /* DAC1 Write debug event */

Definition at line 348 of file ppc_spr.h.

◆ DBSR_DW2

#define DBSR_DW2   0x00200000 /* DAC2 Write debug event */

Definition at line 350 of file ppc_spr.h.

◆ DBSR_EDE

#define DBSR_EDE   0x20000000 /* Exception debug event */

Definition at line 342 of file ppc_spr.h.

◆ DBSR_IA1

#define DBSR_IA1   0x04000000 /* IAC1 debug event */

Definition at line 345 of file ppc_spr.h.

◆ DBSR_IA2

#define DBSR_IA2   0x02000000 /* IAC2 debug event */

Definition at line 346 of file ppc_spr.h.

◆ DBSR_IA3

#define DBSR_IA3   0x00080000 /* IAC3 debug event */

Definition at line 352 of file ppc_spr.h.

◆ DBSR_IA4

#define DBSR_IA4   0x00040000 /* IAC4 debug event */

Definition at line 353 of file ppc_spr.h.

◆ DBSR_IC

#define DBSR_IC   0x80000000 /* Instruction completion debug event */

Definition at line 340 of file ppc_spr.h.

◆ DBSR_IDE

#define DBSR_IDE   0x00100000 /* Imprecise debug event */

Definition at line 351 of file ppc_spr.h.

◆ DBSR_MRR

#define DBSR_MRR   0x00000300 /* Most recent reset */

Definition at line 354 of file ppc_spr.h.

◆ DBSR_TIE

#define DBSR_TIE   0x10000000 /* Trap Instruction debug event */

Definition at line 343 of file ppc_spr.h.

◆ DBSR_UDE

#define DBSR_UDE   0x08000000 /* Unconditional debug event */

Definition at line 344 of file ppc_spr.h.

◆ DC_CST_CCER1

#define DC_CST_CCER1   0x00200000 /* D cache error type 1 (RO) */

Definition at line 171 of file ppc_spr.h.

◆ DC_CST_CCER2

#define DC_CST_CCER2   0x00100000 /* D cache error type 2 (RO) */

Definition at line 172 of file ppc_spr.h.

◆ DC_CST_CCER3

#define DC_CST_CCER3   0x00080000 /* D cache error type 3 (RO) */

Definition at line 173 of file ppc_spr.h.

◆ DC_CST_CMD_CLRFWT

#define DC_CST_CMD_CLRFWT   0x03000000 /* D cache clear forced write-thru */

Definition at line 168 of file ppc_spr.h.

◆ DC_CST_CMD_CLRLESWAP

#define DC_CST_CMD_CLRLESWAP   0x07000000 /* D cache clr little-endian swap */

Definition at line 164 of file ppc_spr.h.

◆ DC_CST_CMD_DISABLE

#define DC_CST_CMD_DISABLE   0x04000000 /* D cache disable */

Definition at line 167 of file ppc_spr.h.

◆ DC_CST_CMD_ENABLE

#define DC_CST_CMD_ENABLE   0x02000000 /* D cache enable */

Definition at line 169 of file ppc_spr.h.

◆ DC_CST_CMD_FLUSH

#define DC_CST_CMD_FLUSH   0x0e000000 /* D cache invalidate all */

Definition at line 160 of file ppc_spr.h.

◆ DC_CST_CMD_INVALL

#define DC_CST_CMD_INVALL   0x0c000000 /* D cache invalidate all */

Definition at line 161 of file ppc_spr.h.

◆ DC_CST_CMD_LOADLOCK

#define DC_CST_CMD_LOADLOCK   0x06000000 /* D cache load & lock block */

Definition at line 165 of file ppc_spr.h.

◆ DC_CST_CMD_SETFWT

#define DC_CST_CMD_SETFWT   0x01000000 /* D cache set forced write-thru */

Definition at line 170 of file ppc_spr.h.

◆ DC_CST_CMD_SETLESWAP

#define DC_CST_CMD_SETLESWAP   0x05000000 /* D cache set little-endian swap */

Definition at line 166 of file ppc_spr.h.

◆ DC_CST_CMD_UNLOCK

#define DC_CST_CMD_UNLOCK   0x08000000 /* D cache unlock block */

Definition at line 163 of file ppc_spr.h.

◆ DC_CST_CMD_UNLOCKALL

#define DC_CST_CMD_UNLOCKALL   0x0a000000 /* D cache unlock all */

Definition at line 162 of file ppc_spr.h.

◆ DC_CST_DEN

#define DC_CST_DEN   0x80000000 /* D cache ENabled (RO) */

Definition at line 157 of file ppc_spr.h.

◆ DC_CST_DFWT

#define DC_CST_DFWT   0x40000000 /* D cache Force Write-Thru (RO) */

Definition at line 158 of file ppc_spr.h.

◆ DC_CST_LES

#define DC_CST_LES   0x20000000 /* D cache Little Endian Swap (RO) */

Definition at line 159 of file ppc_spr.h.

◆ DSISR_DABR

#define DSISR_DABR   0x00400000 /* DABR match */

Definition at line 48 of file ppc_spr.h.

◆ DSISR_DIRECT

#define DSISR_DIRECT   0x80000000 /* Direct-store error exception */

Definition at line 43 of file ppc_spr.h.

◆ DSISR_EAR

#define DSISR_EAR   0x00100000 /* eciwx/ecowx && EAR[E] == 0 */

Definition at line 50 of file ppc_spr.h.

◆ DSISR_INVRX

#define DSISR_INVRX   0x04000000 /* Reserve-indexed insn direct-store access */

Definition at line 46 of file ppc_spr.h.

◆ DSISR_NOTFOUND

#define DSISR_NOTFOUND   0x40000000 /* Translation not found */

Definition at line 44 of file ppc_spr.h.

◆ DSISR_PROTECT

#define DSISR_PROTECT   0x08000000 /* Memory access not permitted */

Definition at line 45 of file ppc_spr.h.

◆ DSISR_SEGMENT

#define DSISR_SEGMENT   0x00200000 /* XXX; not in 6xx PEM */

Definition at line 49 of file ppc_spr.h.

◆ DSISR_STORE

#define DSISR_STORE   0x02000000 /* Store operation */

Definition at line 47 of file ppc_spr.h.

◆ ESR_DIZ

#define ESR_DIZ   0x00800000 /* Data/instruction storage interrupt - zone fault */

Definition at line 296 of file ppc_spr.h.

◆ ESR_DST

#define ESR_DST   0x00800000 /* Data storage interrupt - store fault */

Definition at line 295 of file ppc_spr.h.

◆ ESR_MCI

#define ESR_MCI   0x80000000 /* Machine check - instruction */

Definition at line 291 of file ppc_spr.h.

◆ ESR_PIL

#define ESR_PIL   0x08000000 /* Program interrupt - illegal */

Definition at line 292 of file ppc_spr.h.

◆ ESR_PPR

#define ESR_PPR   0x04000000 /* Program interrupt - privileged */

Definition at line 293 of file ppc_spr.h.

◆ ESR_PTR

#define ESR_PTR   0x02000000 /* Program interrupt - trap */

Definition at line 294 of file ppc_spr.h.

◆ ESR_U0F

#define ESR_U0F   0x00008000 /* Data storage interrupt - U0 fault */

Definition at line 297 of file ppc_spr.h.

◆ IBM401A1

#define IBM401A1   0x0021

Definition at line 88 of file ppc_spr.h.

◆ IBM401B2

#define IBM401B2   0x0022

Definition at line 89 of file ppc_spr.h.

◆ IBM401C2

#define IBM401C2   0x0023

Definition at line 90 of file ppc_spr.h.

◆ IBM401D2

#define IBM401D2   0x0024

Definition at line 91 of file ppc_spr.h.

◆ IBM401E2

#define IBM401E2   0x0025

Definition at line 92 of file ppc_spr.h.

◆ IBM401F2

#define IBM401F2   0x0026

Definition at line 93 of file ppc_spr.h.

◆ IBM401G2

#define IBM401G2   0x0027

Definition at line 94 of file ppc_spr.h.

◆ IBM403

#define IBM403   0x0020

Definition at line 87 of file ppc_spr.h.

◆ IBM405GP

#define IBM405GP   0x4011

Definition at line 98 of file ppc_spr.h.

◆ IBM405GPR

#define IBM405GPR   0x5091

Definition at line 99 of file ppc_spr.h.

◆ IBM405L

#define IBM405L   0x4161

Definition at line 100 of file ppc_spr.h.

◆ IBM750FX

#define IBM750FX   0x7000

Definition at line 101 of file ppc_spr.h.

◆ IBMPOWER3

#define IBMPOWER3   0x0041

Definition at line 95 of file ppc_spr.h.

◆ IC_CST_CCER1

#define IC_CST_CCER1   0x00200000 /* I cache error type 1 (RO) */

Definition at line 143 of file ppc_spr.h.

◆ IC_CST_CCER2

#define IC_CST_CCER2   0x00100000 /* I cache error type 2 (RO) */

Definition at line 144 of file ppc_spr.h.

◆ IC_CST_CCER3

#define IC_CST_CCER3   0x00080000 /* I cache error type 3 (RO) */

Definition at line 145 of file ppc_spr.h.

◆ IC_CST_CMD_DISABLE

#define IC_CST_CMD_DISABLE   0x04000000 /* I cache disable */

Definition at line 141 of file ppc_spr.h.

◆ IC_CST_CMD_ENABLE

#define IC_CST_CMD_ENABLE   0x02000000 /* I cache enable */

Definition at line 142 of file ppc_spr.h.

◆ IC_CST_CMD_INVALL

#define IC_CST_CMD_INVALL   0x0c000000 /* I cache invalidate all */

Definition at line 137 of file ppc_spr.h.

◆ IC_CST_CMD_LOADLOCK

#define IC_CST_CMD_LOADLOCK   0x06000000 /* I cache load & lock block */

Definition at line 140 of file ppc_spr.h.

◆ IC_CST_CMD_UNLOCK

#define IC_CST_CMD_UNLOCK   0x08000000 /* I cache unlock block */

Definition at line 139 of file ppc_spr.h.

◆ IC_CST_CMD_UNLOCKALL

#define IC_CST_CMD_UNLOCKALL   0x0a000000 /* I cache unlock all */

Definition at line 138 of file ppc_spr.h.

◆ IC_CST_IEN

#define IC_CST_IEN   0x80000000 /* I cache is ENabled (RO) */

Definition at line 136 of file ppc_spr.h.

◆ L2CLK_10

#define L2CLK_10   0x02000000 /* core clock / 1 */

Definition at line 410 of file ppc_spr.h.

◆ L2CLK_15

#define L2CLK_15   0x04000000 /* / 1.5 */

Definition at line 411 of file ppc_spr.h.

◆ L2CLK_20

#define L2CLK_20   0x08000000 /* / 2 */

Definition at line 413 of file ppc_spr.h.

◆ L2CLK_25

#define L2CLK_25   0x0a000000 /* / 2.5 */

Definition at line 414 of file ppc_spr.h.

◆ L2CLK_30

#define L2CLK_30   0x0c000000 /* / 3 */

Definition at line 415 of file ppc_spr.h.

◆ L2CLK_35

#define L2CLK_35   0x06000000 /* / 3.5 */

Definition at line 412 of file ppc_spr.h.

◆ L2CLK_40

#define L2CLK_40   0x0e000000 /* / 4 */

Definition at line 416 of file ppc_spr.h.

◆ L2CLK_DIS

#define L2CLK_DIS   0x00000000 /* disable L2 clock */

Definition at line 409 of file ppc_spr.h.

◆ L2CR_L2BYP

#define L2CR_L2BYP   0x00002000 /* 18: L2 DLL bypass. */

Definition at line 429 of file ppc_spr.h.

◆ L2CR_L2CLK

#define L2CR_L2CLK   0x0e000000 /* 4-6: L2 clock ratio */

Definition at line 408 of file ppc_spr.h.

◆ L2CR_L2CLKSTP

#define L2CR_L2CLKSTP   0x00000200 /* 22: L2 clock stop. */

Definition at line 433 of file ppc_spr.h.

◆ L2CR_L2CTL

#define L2CR_L2CTL
Value:
0x00100000 /* 11: L2 RAM control (ZZ enable).
Enables automatic operation of the
L2ZZ (low-power mode) signal. */

Definition at line 423 of file ppc_spr.h.

◆ L2CR_L2DF

#define L2CR_L2DF   0x00004000 /* 17: L2 differential clock. */

Definition at line 428 of file ppc_spr.h.

◆ L2CR_L2DO

#define L2CR_L2DO
Value:
0x00400000 /* 9: L2 data-only.
Setting this bit disables instruction
caching. */

Definition at line 421 of file ppc_spr.h.

◆ L2CR_L2DRO

#define L2CR_L2DRO   0x00000100 /* 23: L2DLL rollover checkstop enable. */

Definition at line 434 of file ppc_spr.h.

◆ L2CR_L2E

#define L2CR_L2E   0x80000000 /* 0: L2 enable */

Definition at line 401 of file ppc_spr.h.

◆ L2CR_L2FA

#define L2CR_L2FA   0x00001000 /* 19: L2 flush assist (for software flush). */

Definition at line 430 of file ppc_spr.h.

◆ L2CR_L2HWF

#define L2CR_L2HWF   0x00000800 /* 20: L2 hardware flush. */

Definition at line 431 of file ppc_spr.h.

◆ L2CR_L2I

#define L2CR_L2I   0x00200000 /* 10: L2 global invalidate. */

Definition at line 422 of file ppc_spr.h.

◆ L2CR_L2IO

#define L2CR_L2IO   0x00000400 /* 21: L2 instruction-only. */

Definition at line 432 of file ppc_spr.h.

◆ L2CR_L2IP

#define L2CR_L2IP   0x00000001 /* 31: L2 global invalidate in */

Definition at line 435 of file ppc_spr.h.

◆ L2CR_L2OH

#define L2CR_L2OH   0x00030000 /* 14-15: L2 output hold. */

Definition at line 426 of file ppc_spr.h.

◆ L2CR_L2PE

#define L2CR_L2PE   0x40000000 /* 1: L2 data parity enable */

Definition at line 402 of file ppc_spr.h.

◆ L2CR_L2RAM

#define L2CR_L2RAM   0x01800000 /* 7-8: L2 RAM type */

Definition at line 417 of file ppc_spr.h.

◆ L2CR_L2SIZ

#define L2CR_L2SIZ   0x30000000 /* 2-3: L2 size */

Definition at line 403 of file ppc_spr.h.

◆ L2CR_L2SL

#define L2CR_L2SL   0x00008000 /* 16: L2 DLL slow. */

Definition at line 427 of file ppc_spr.h.

◆ L2CR_L2TS

#define L2CR_L2TS   0x00040000 /* 13: L2 test support. */

Definition at line 425 of file ppc_spr.h.

◆ L2CR_L2WT

#define L2CR_L2WT   0x00080000 /* 12: L2 write-through. */

Definition at line 424 of file ppc_spr.h.

◆ L2RAM_FLOWTHRU_BURST

#define L2RAM_FLOWTHRU_BURST   0x00000000

Definition at line 418 of file ppc_spr.h.

◆ L2RAM_PIPELINE_BURST

#define L2RAM_PIPELINE_BURST   0x01000000

Definition at line 419 of file ppc_spr.h.

◆ L2RAM_PIPELINE_LATE

#define L2RAM_PIPELINE_LATE   0x01800000

Definition at line 420 of file ppc_spr.h.

◆ L2SIZ_1M

#define L2SIZ_1M   0x30000000

Definition at line 407 of file ppc_spr.h.

◆ L2SIZ_256K

#define L2SIZ_256K   0x10000000

Definition at line 405 of file ppc_spr.h.

◆ L2SIZ_2M

#define L2SIZ_2M   0x00000000

Definition at line 404 of file ppc_spr.h.

◆ L2SIZ_512K

#define L2SIZ_512K   0x20000000

Definition at line 406 of file ppc_spr.h.

◆ L3CKSP_2

#define L3CKSP_2   0x00000000 /* 2 clocks */

Definition at line 457 of file ppc_spr.h.

◆ L3CKSP_3

#define L3CKSP_3   0x00010000 /* 3 clocks */

Definition at line 458 of file ppc_spr.h.

◆ L3CKSP_4

#define L3CKSP_4   0x00020000 /* 4 clocks */

Definition at line 459 of file ppc_spr.h.

◆ L3CKSP_5

#define L3CKSP_5   0x00030000 /* 5 clocks */

Definition at line 460 of file ppc_spr.h.

◆ L3CLK_20

#define L3CLK_20   0x01000000 /* / 2 */

Definition at line 448 of file ppc_spr.h.

◆ L3CLK_25

#define L3CLK_25   0x01800000 /* / 2.5 */

Definition at line 449 of file ppc_spr.h.

◆ L3CLK_30

#define L3CLK_30   0x02000000 /* / 3 */

Definition at line 450 of file ppc_spr.h.

◆ L3CLK_35

#define L3CLK_35   0x02800000 /* / 3.5 */

Definition at line 451 of file ppc_spr.h.

◆ L3CLK_40

#define L3CLK_40   0x03000000 /* / 4 */

Definition at line 452 of file ppc_spr.h.

◆ L3CLK_50

#define L3CLK_50   0x03800000 /* / 5 */

Definition at line 453 of file ppc_spr.h.

◆ L3CLK_60

#define L3CLK_60   0x00000000 /* core clock / 6 */

Definition at line 447 of file ppc_spr.h.

◆ L3CR_L3APE

#define L3CR_L3APE   0x20000000 /* 2: L3 address parity checking enable */

Definition at line 441 of file ppc_spr.h.

◆ L3CR_L3CKSP

#define L3CR_L3CKSP   0x00030000 /* 14-15: L3 clock sample point */

Definition at line 456 of file ppc_spr.h.

◆ L3CR_L3CLK

#define L3CR_L3CLK   0x03800000 /* 6-8: L3 clock ratio */

Definition at line 446 of file ppc_spr.h.

◆ L3CR_L3CLKEN

#define L3CR_L3CLKEN   0x08000000 /* 4: Enables the L3_CLK[0:1] signals */

Definition at line 445 of file ppc_spr.h.

◆ L3CR_L3DO

#define L3CR_L3DO   0x00000040 /* 25: L3 data-only mode */

Definition at line 476 of file ppc_spr.h.

◆ L3CR_L3E

#define L3CR_L3E   0x80000000 /* 0: L3 enable */

Definition at line 439 of file ppc_spr.h.

◆ L3CR_L3HWF

#define L3CR_L3HWF   0x00000800 /* 20: L3 hardware flush */

Definition at line 469 of file ppc_spr.h.

◆ L3CR_L3I

#define L3CR_L3I   0x00000400 /* 21: L3 global invalidate */

Definition at line 470 of file ppc_spr.h.

◆ L3CR_L3IO

#define L3CR_L3IO   0x00400000 /* 9: L3 instruction-only mode */

Definition at line 454 of file ppc_spr.h.

◆ L3CR_L3NIRCA

#define L3CR_L3NIRCA   0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */

Definition at line 475 of file ppc_spr.h.

◆ L3CR_L3PE

#define L3CR_L3PE   0x40000000 /* 1: L3 data parity checking enable */

Definition at line 440 of file ppc_spr.h.

◆ L3CR_L3PSP

#define L3CR_L3PSP   0x0000e000 /* 16-18: L3 P-clock sample point */

Definition at line 461 of file ppc_spr.h.

◆ L3CR_L3REP

#define L3CR_L3REP   0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */

Definition at line 468 of file ppc_spr.h.

◆ L3CR_L3RT

#define L3CR_L3RT   0x00000300 /* 22-23: L3 SRAM type */

Definition at line 471 of file ppc_spr.h.

◆ L3CR_L3SIZ

#define L3CR_L3SIZ   0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */

Definition at line 442 of file ppc_spr.h.

◆ L3CR_L3SPO

#define L3CR_L3SPO   0x00040000 /* 13: L3 sample point override */

Definition at line 455 of file ppc_spr.h.

◆ L3CR_PMEN

#define L3CR_PMEN   0x00000004 /* 29: Private memory enable */

Definition at line 477 of file ppc_spr.h.

◆ L3CR_PMSIZ

#define L3CR_PMSIZ   0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */

Definition at line 478 of file ppc_spr.h.

◆ L3CR_RESERVED

#define L3CR_RESERVED   0x0438003a /* Reserved bits in L3CR */

Definition at line 438 of file ppc_spr.h.

◆ L3PSP_0

#define L3PSP_0   0x00000000 /* 0 clocks */

Definition at line 462 of file ppc_spr.h.

◆ L3PSP_1

#define L3PSP_1   0x00002000 /* 1 clocks */

Definition at line 463 of file ppc_spr.h.

◆ L3PSP_2

#define L3PSP_2   0x00004000 /* 2 clocks */

Definition at line 464 of file ppc_spr.h.

◆ L3PSP_3

#define L3PSP_3   0x00006000 /* 3 clocks */

Definition at line 465 of file ppc_spr.h.

◆ L3PSP_4

#define L3PSP_4   0x00008000 /* 4 clocks */

Definition at line 466 of file ppc_spr.h.

◆ L3PSP_5

#define L3PSP_5   0x0000a000 /* 5 clocks */

Definition at line 467 of file ppc_spr.h.

◆ L3RT_MSUG2_DDR

#define L3RT_MSUG2_DDR   0x00000000 /* MSUG2 DDR SRAM */

Definition at line 472 of file ppc_spr.h.

◆ L3RT_PB2_SRAM

#define L3RT_PB2_SRAM   0x00000300 /* PB2 SRAM */

Definition at line 474 of file ppc_spr.h.

◆ L3RT_PIPELINE_LATE

#define L3RT_PIPELINE_LATE   0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */

Definition at line 473 of file ppc_spr.h.

◆ L3SIZ_1M

#define L3SIZ_1M   0x00000000

Definition at line 443 of file ppc_spr.h.

◆ L3SIZ_2M

#define L3SIZ_2M   0x10000000

Definition at line 444 of file ppc_spr.h.

◆ M_CASID

#define M_CASID   0x0000000f /* Current AS Id */

Definition at line 219 of file ppc_spr.h.

◆ M_TWB_L1INDX

#define M_TWB_L1INDX   0x00000ffc /* level-1 index */

Definition at line 224 of file ppc_spr.h.

◆ M_TWB_L1TB

#define M_TWB_L1TB   0xfffff000 /* level-1 translation base */

Definition at line 223 of file ppc_spr.h.

◆ MD_CTR_TWAM

#define MD_CTR_TWAM   0x04000000 /* TableWalk Assist Mode */

Definition at line 190 of file ppc_spr.h.

◆ MD_CTR_WTDEF

#define MD_CTR_WTDEF   0x20000000 /* Write-Through DEFault */

Definition at line 188 of file ppc_spr.h.

◆ MD_TWC_L2TB

#define MD_TWC_L2TB   0xfffff000 /* Level-2 Tablewalk Base */

Definition at line 204 of file ppc_spr.h.

◆ MD_TWC_WT

#define MD_TWC_WT   0x00000002 /* Write-Through */

Definition at line 208 of file ppc_spr.h.

◆ MMCR0_FC

#define MMCR0_FC   0x80000000 /* Freeze counters */

Definition at line 251 of file ppc_spr.h.

◆ MMCR0_FCECE

#define MMCR0_FCECE   0x02000000 /* Freeze counters after event */

Definition at line 257 of file ppc_spr.h.

◆ MMCR0_FCM0

#define MMCR0_FCM0   0x08000000 /* Freeze counters when mark=0 */

Definition at line 255 of file ppc_spr.h.

◆ MMCR0_FCM1

#define MMCR0_FCM1   0x10000000 /* Freeze counters when mark=1 */

Definition at line 254 of file ppc_spr.h.

◆ MMCR0_FCP

#define MMCR0_FCP   0x20000000 /* Freeze counters in user mode */

Definition at line 253 of file ppc_spr.h.

◆ MMCR0_FCS

#define MMCR0_FCS   0x40000000 /* Freeze counters in supervisor mode */

Definition at line 252 of file ppc_spr.h.

◆ MMCR0_PMC1CE

#define MMCR0_PMC1CE   0x00008000 /* PMC1 condition enable */

Definition at line 264 of file ppc_spr.h.

◆ MMCR0_PMC1SEL

#define MMCR0_PMC1SEL (   x)    ((x) << 6) /* PMC1 selector */

Definition at line 267 of file ppc_spr.h.

◆ MMCR0_PMC2SEL

#define MMCR0_PMC2SEL (   x)    ((x) << 0) /* PMC2 selector */

Definition at line 268 of file ppc_spr.h.

◆ MMCR0_PMCNCE

#define MMCR0_PMCNCE   0x00004000 /* PMCn condition enable */

Definition at line 265 of file ppc_spr.h.

◆ MMCR0_PMXE

#define MMCR0_PMXE   0x04000000 /* Enable PM interrupt */

Definition at line 256 of file ppc_spr.h.

◆ MMCR0_TBEE

#define MMCR0_TBEE   0x00400000 /* Time-base event enable */

Definition at line 262 of file ppc_spr.h.

◆ MMCR0_TBSEL_15

#define MMCR0_TBSEL_15   0x01800000 /* Count bit 15 of TBL */

Definition at line 258 of file ppc_spr.h.

◆ MMCR0_TBSEL_19

#define MMCR0_TBSEL_19   0x01000000 /* Count bit 19 of TBL */

Definition at line 259 of file ppc_spr.h.

◆ MMCR0_TBSEL_23

#define MMCR0_TBSEL_23   0x00800000 /* Count bit 23 of TBL */

Definition at line 260 of file ppc_spr.h.

◆ MMCR0_TBSEL_31

#define MMCR0_TBSEL_31   0x00000000 /* Count bit 31 of TBL */

Definition at line 261 of file ppc_spr.h.

◆ MMCR0_TRIGGER

#define MMCR0_TRIGGER   0x00002000 /* Trigger */

Definition at line 266 of file ppc_spr.h.

◆ MMCR1_PMC3SEL

#define MMCR1_PMC3SEL (   x)    ((x) << 27) /* PMC 3 selector */

Definition at line 276 of file ppc_spr.h.

◆ MMCR1_PMC4SEL

#define MMCR1_PMC4SEL (   x)    ((x) << 22) /* PMC 4 selector */

Definition at line 277 of file ppc_spr.h.

◆ MMCR1_PMC5SEL

#define MMCR1_PMC5SEL (   x)    ((x) << 17) /* PMC 5 selector */

Definition at line 278 of file ppc_spr.h.

◆ MMCR1_PMC6SEL

#define MMCR1_PMC6SEL (   x)    ((x) << 11) /* PMC 6 selector */

Definition at line 279 of file ppc_spr.h.

◆ MMCRO_THRESHOLD

#define MMCRO_THRESHOLD (   x)    ((x) << 16) /* Threshold value */

Definition at line 263 of file ppc_spr.h.

◆ MPC601

#define MPC601   0x0001

Definition at line 76 of file ppc_spr.h.

◆ MPC602

#define MPC602   0x0005

Definition at line 79 of file ppc_spr.h.

◆ MPC603

#define MPC603   0x0003

Definition at line 77 of file ppc_spr.h.

◆ MPC603e

#define MPC603e   0x0006

Definition at line 80 of file ppc_spr.h.

◆ MPC603ev

#define MPC603ev   0x0007

Definition at line 81 of file ppc_spr.h.

◆ MPC604

#define MPC604   0x0004

Definition at line 78 of file ppc_spr.h.

◆ MPC604e

#define MPC604e   0x0009

Definition at line 83 of file ppc_spr.h.

◆ MPC604ev

#define MPC604ev   0x000a

Definition at line 84 of file ppc_spr.h.

◆ MPC620

#define MPC620   0x0014

Definition at line 86 of file ppc_spr.h.

◆ MPC7400

#define MPC7400   0x000c

Definition at line 85 of file ppc_spr.h.

◆ MPC7410

#define MPC7410   0x800c

Definition at line 108 of file ppc_spr.h.

◆ MPC7447A

#define MPC7447A   0x8003

Definition at line 105 of file ppc_spr.h.

◆ MPC7448

#define MPC7448   0x8004

Definition at line 106 of file ppc_spr.h.

◆ MPC7450

#define MPC7450   0x8000

Definition at line 102 of file ppc_spr.h.

◆ MPC7455

#define MPC7455   0x8001

Definition at line 103 of file ppc_spr.h.

◆ MPC7457

#define MPC7457   0x8002

Definition at line 104 of file ppc_spr.h.

◆ MPC745X_P

#define MPC745X_P (   v)    ((v & 0xFFF8) == 0x8000)

Definition at line 107 of file ppc_spr.h.

◆ MPC750

#define MPC750   0x0008

Definition at line 82 of file ppc_spr.h.

◆ MPC8240

#define MPC8240   0x0081

Definition at line 97 of file ppc_spr.h.

◆ MPC8245

#define MPC8245   0x8081

Definition at line 109 of file ppc_spr.h.

◆ MPC860

#define MPC860   0x0050

Definition at line 96 of file ppc_spr.h.

◆ MSSCR0_ABD

#define MSSCR0_ABD   0x00100000 /* 11: address bus driven (read-only) */

Definition at line 394 of file ppc_spr.h.

◆ MSSCR0_BMODE

#define MSSCR0_BMODE   0x0000c000 /* 16-17: Bus Mode (read-only) (7450) */

Definition at line 395 of file ppc_spr.h.

◆ MSSCR0_DL1HWF

#define MSSCR0_DL1HWF   0x00800000 /* 8: L1 data cache hardware flush */

Definition at line 391 of file ppc_spr.h.

◆ MSSCR0_EMODE

#define MSSCR0_EMODE   0x00200000 /* 10: MPX bus mode (read-only) */

Definition at line 393 of file ppc_spr.h.

◆ MSSCR0_ID

#define MSSCR0_ID   0x00000040 /* 26: Processor ID */

Definition at line 396 of file ppc_spr.h.

◆ MSSCR0_L1INTVEN

#define MSSCR0_L1INTVEN   0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */

Definition at line 389 of file ppc_spr.h.

◆ MSSCR0_L2INTVEN

#define MSSCR0_L2INTVEN   0x07000000 /* 5-7: L2 data cache ~HIT intervention enable */

Definition at line 390 of file ppc_spr.h.

◆ MSSCR0_L2PFE

#define MSSCR0_L2PFE   0x00000003 /* 30-31: L2 prefetching enabled (7450) */

Definition at line 397 of file ppc_spr.h.

◆ MSSCR0_MBO

#define MSSCR0_MBO   0x00400000 /* 9: must be one */

Definition at line 392 of file ppc_spr.h.

◆ MSSCR0_SHDEN

#define MSSCR0_SHDEN   0x80000000 /* 0: Shared-state enable */

Definition at line 387 of file ppc_spr.h.

◆ MSSCR0_SHDPEN3

#define MSSCR0_SHDPEN3   0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */

Definition at line 388 of file ppc_spr.h.

◆ Mx_CTR_CIDEF

#define Mx_CTR_CIDEF   0x20000000 /* Cache-Inhibit DEFault */

Definition at line 187 of file ppc_spr.h.

◆ Mx_CTR_GPM

#define Mx_CTR_GPM   0x80000000 /* Group Protection Mode */

Definition at line 185 of file ppc_spr.h.

◆ Mx_CTR_PPCS

#define Mx_CTR_PPCS   0x02000000 /* Priv/user state compare mode */

Definition at line 191 of file ppc_spr.h.

◆ Mx_CTR_PPM

#define Mx_CTR_PPM   0x40000000 /* Page Protection Mode */

Definition at line 186 of file ppc_spr.h.

◆ Mx_CTR_RSV4

#define Mx_CTR_RSV4   0x08000000 /* Reserve 4 TLB entries */

Definition at line 189 of file ppc_spr.h.

◆ Mx_CTR_TLB_INDX

#define Mx_CTR_TLB_INDX   0x000001f0 /* TLB index mask */

Definition at line 192 of file ppc_spr.h.

◆ Mx_CTR_TLB_INDX_BITPOS

#define Mx_CTR_TLB_INDX_BITPOS   8 /* TLB index shift */

Definition at line 193 of file ppc_spr.h.

◆ Mx_EPN_ASID

#define Mx_EPN_ASID   0x0000000f /* Address Space ID */

Definition at line 202 of file ppc_spr.h.

◆ Mx_EPN_EPN

#define Mx_EPN_EPN   0xfffff000 /* Effective Page Number mask */

Definition at line 200 of file ppc_spr.h.

◆ Mx_EPN_EV

#define Mx_EPN_EV   0x00000020 /* Entry Valid */

Definition at line 201 of file ppc_spr.h.

◆ Mx_GP_PAGE

#define Mx_GP_PAGE   (1 << (2*(15-(n)))) /* access is page protect */

Definition at line 196 of file ppc_spr.h.

◆ Mx_GP_SUPER

#define Mx_GP_SUPER (   n)    (0 << (2*(15-(n)))) /* access is supervisor */

Definition at line 195 of file ppc_spr.h.

◆ Mx_GP_SWAPPED

#define Mx_GP_SWAPPED   (2 << (2*(15-(n)))) /* access is swapped */

Definition at line 197 of file ppc_spr.h.

◆ Mx_GP_USER

#define Mx_GP_USER   (3 << (2*(15-(n)))) /* access is user */

Definition at line 198 of file ppc_spr.h.

◆ Mx_RPN_CI

#define Mx_RPN_CI   0x00000002 /* Cache Inhibit */

Definition at line 215 of file ppc_spr.h.

◆ Mx_RPN_PP

#define Mx_RPN_PP   0x00000ff0 /* Page Protection */

Definition at line 212 of file ppc_spr.h.

◆ Mx_RPN_RPN

#define Mx_RPN_RPN   0xfffff000 /* Real Page Number */

Definition at line 211 of file ppc_spr.h.

◆ Mx_RPN_SH

#define Mx_RPN_SH   0x00000004 /* SHared page */

Definition at line 214 of file ppc_spr.h.

◆ Mx_RPN_SPS

#define Mx_RPN_SPS   0x00000008 /* Small Page Size */

Definition at line 213 of file ppc_spr.h.

◆ Mx_RPN_V

#define Mx_RPN_V   0x00000001 /* Valid */

Definition at line 216 of file ppc_spr.h.

◆ Mx_TWC_APG

#define Mx_TWC_APG   0x000001e0 /* Access Protection Group */

Definition at line 205 of file ppc_spr.h.

◆ Mx_TWC_G

#define Mx_TWC_G   0x00000010 /* Guarded memory */

Definition at line 206 of file ppc_spr.h.

◆ Mx_TWC_PS

#define Mx_TWC_PS   0x0000000c /* Page Size (L1) */

Definition at line 207 of file ppc_spr.h.

◆ Mx_TWC_V

#define Mx_TWC_V   0x00000001 /* Entry Valid */

Definition at line 209 of file ppc_spr.h.

◆ PCMN_IDISPATCH

#define PCMN_IDISPATCH   4 /* Instructions dispatched */

Definition at line 507 of file ppc_spr.h.

◆ PMC_OVERFLOW

#define PMC_OVERFLOW   0x80000000 /* Counter has overflowed */

Definition at line 500 of file ppc_spr.h.

◆ PMCN_CYCLES

#define PMCN_CYCLES   1 /* Processor cycles */

Definition at line 504 of file ppc_spr.h.

◆ PMCN_ICOMP

#define PMCN_ICOMP   2 /* Instructions completed */

Definition at line 505 of file ppc_spr.h.

◆ PMCN_NONE

#define PMCN_NONE   0 /* Count nothing */

Definition at line 503 of file ppc_spr.h.

◆ PMCN_TBLTRANS

#define PMCN_TBLTRANS   3 /* TBL bit transitions */

Definition at line 506 of file ppc_spr.h.

◆ SPR_ASR

#define SPR_ASR   0x118 /* ... Address Space Register (PPC64) */

Definition at line 71 of file ppc_spr.h.

◆ SPR_CCR0

#define SPR_CCR0   0x3b3 /* 4.. Core Configuration Register 0 */

Definition at line 245 of file ppc_spr.h.

◆ SPR_CTR

#define SPR_CTR   0x009 /* 468 Count Register */

Definition at line 41 of file ppc_spr.h.

◆ SPR_DABR

#define SPR_DABR   0x3f5 /* .6. Data Address Breakpoint Register */

Definition at line 384 of file ppc_spr.h.

◆ SPR_DAC1

#define SPR_DAC1   0x3f6 /* 4.. Data Address Compare 1 */

Definition at line 385 of file ppc_spr.h.

◆ SPR_DAC2

#define SPR_DAC2   0x3f7 /* 4.. Data Address Compare 2 */

Definition at line 398 of file ppc_spr.h.

◆ SPR_DAR

#define SPR_DAR   0x013 /* .68 Data Address Register */

Definition at line 51 of file ppc_spr.h.

◆ SPR_DBAT0L

#define SPR_DBAT0L   0x219 /* .6. Data BAT Reg 0 Lower */

Definition at line 128 of file ppc_spr.h.

◆ SPR_DBAT0U

#define SPR_DBAT0U   0x218 /* .6. Data BAT Reg 0 Upper */

Definition at line 127 of file ppc_spr.h.

◆ SPR_DBAT1L

#define SPR_DBAT1L   0x21b /* .6. Data BAT Reg 1 Lower */

Definition at line 130 of file ppc_spr.h.

◆ SPR_DBAT1U

#define SPR_DBAT1U   0x21a /* .6. Data BAT Reg 1 Upper */

Definition at line 129 of file ppc_spr.h.

◆ SPR_DBAT2L

#define SPR_DBAT2L   0x21d /* .6. Data BAT Reg 2 Lower */

Definition at line 132 of file ppc_spr.h.

◆ SPR_DBAT2U

#define SPR_DBAT2U   0x21c /* .6. Data BAT Reg 2 Upper */

Definition at line 131 of file ppc_spr.h.

◆ SPR_DBAT3L

#define SPR_DBAT3L   0x21f /* .6. Data BAT Reg 3 Lower */

Definition at line 134 of file ppc_spr.h.

◆ SPR_DBAT3U

#define SPR_DBAT3U   0x21e /* .6. Data BAT Reg 3 Upper */

Definition at line 133 of file ppc_spr.h.

◆ SPR_DBAT4L

#define SPR_DBAT4L   0x239 /* .6. Data BAT Reg 4 Lower */

Definition at line 176 of file ppc_spr.h.

◆ SPR_DBAT4U

#define SPR_DBAT4U   0x238 /* .6. Data BAT Reg 4 Upper */

Definition at line 174 of file ppc_spr.h.

◆ SPR_DBAT5L

#define SPR_DBAT5L   0x23b /* .6. Data BAT Reg 5 Lower */

Definition at line 179 of file ppc_spr.h.

◆ SPR_DBAT5U

#define SPR_DBAT5U   0x23a /* .6. Data BAT Reg 5 Upper */

Definition at line 178 of file ppc_spr.h.

◆ SPR_DBAT6L

#define SPR_DBAT6L   0x23d /* .6. Data BAT Reg 6 Lower */

Definition at line 181 of file ppc_spr.h.

◆ SPR_DBAT6U

#define SPR_DBAT6U   0x23c /* .6. Data BAT Reg 6 Upper */

Definition at line 180 of file ppc_spr.h.

◆ SPR_DBAT7L

#define SPR_DBAT7L   0x23f /* .6. Data BAT Reg 7 Lower */

Definition at line 183 of file ppc_spr.h.

◆ SPR_DBAT7U

#define SPR_DBAT7U   0x23e /* .6. Data BAT Reg 7 Upper */

Definition at line 182 of file ppc_spr.h.

◆ SPR_DBCR0

#define SPR_DBCR0   0x3f2 /* 4.. Debug Control Register 0 */

Definition at line 357 of file ppc_spr.h.

◆ SPR_DBCR1

#define SPR_DBCR1   0x3bd /* 4.. Debug Control Register 1 */

Definition at line 282 of file ppc_spr.h.

◆ SPR_DBSR

#define SPR_DBSR   0x3f0 /* 4.. Debug Status Register */

Definition at line 339 of file ppc_spr.h.

◆ SPR_DC_ADR

#define SPR_DC_ADR   0x231 /* ..8 Data Cache Address */

Definition at line 175 of file ppc_spr.h.

◆ SPR_DC_CST

#define SPR_DC_CST   0x238 /* ..8 Data Cache CSR */

Definition at line 156 of file ppc_spr.h.

◆ SPR_DC_DAT

#define SPR_DC_DAT   0x232 /* ..8 Data Cache Data */

Definition at line 177 of file ppc_spr.h.

◆ SPR_DCCR

#define SPR_DCCR   0x3fa /* 4.. Data Cache Cachability Register */

Definition at line 479 of file ppc_spr.h.

◆ SPR_DCMP

#define SPR_DCMP   0x3d1 /* .68 Data TLB Compare Register */

Definition at line 286 of file ppc_spr.h.

◆ SPR_DCWR

#define SPR_DCWR   0x3ba /* 4.. Data Cache Write-through Register */

Definition at line 271 of file ppc_spr.h.

◆ SPR_DEAR

#define SPR_DEAR   0x3d5 /* 4.. Data Error Address Register */

Definition at line 300 of file ppc_spr.h.

◆ SPR_DEC

#define SPR_DEC   0x016 /* .68 DECrementer register */

Definition at line 54 of file ppc_spr.h.

◆ SPR_DMISS

#define SPR_DMISS   0x3d0 /* .68 Data TLB Miss Address Register */

Definition at line 285 of file ppc_spr.h.

◆ SPR_DSISR

#define SPR_DSISR   0x012 /* .68 DSI exception source */

Definition at line 42 of file ppc_spr.h.

◆ SPR_DVC1

#define SPR_DVC1   0x3b6 /* 4.. Data Value Compare 1 */

Definition at line 248 of file ppc_spr.h.

◆ SPR_DVC2

#define SPR_DVC2   0x3b7 /* 4.. Data Value Compare 2 */

Definition at line 249 of file ppc_spr.h.

◆ SPR_EAR

#define SPR_EAR   0x11a /* .68 External Access Register */

Definition at line 72 of file ppc_spr.h.

◆ SPR_EID

#define SPR_EID   0x051 /* ..8 Exception Interrupt ??? */

Definition at line 59 of file ppc_spr.h.

◆ SPR_EIE

#define SPR_EIE   0x050 /* ..8 Exception Interrupt ??? */

Definition at line 58 of file ppc_spr.h.

◆ SPR_ESR

#define SPR_ESR   0x3d4 /* 4.. Exception Syndrome Register */

Definition at line 290 of file ppc_spr.h.

◆ SPR_EVPR

#define SPR_EVPR   0x3d6 /* 4.. Exception Vector Prefix Register */

Definition at line 303 of file ppc_spr.h.

◆ SPR_FPECR

#define SPR_FPECR   0x3fe /* .6. Floating-Point Exception Cause Register */

Definition at line 492 of file ppc_spr.h.

◆ SPR_HASH1

#define SPR_HASH1   0x3d2 /* .68 Primary Hash Address Register */

Definition at line 287 of file ppc_spr.h.

◆ SPR_HASH2

#define SPR_HASH2   0x3d3 /* .68 Secondary Hash Address Register */

Definition at line 289 of file ppc_spr.h.

◆ SPR_HDEC

#define SPR_HDEC   0x136

Definition at line 112 of file ppc_spr.h.

◆ SPR_HID0

#define SPR_HID0   0x3f0 /* ..8 Hardware Implementation Register 0 */

Definition at line 355 of file ppc_spr.h.

◆ SPR_HID1

#define SPR_HID1   0x3f1 /* ..8 Hardware Implementation Register 1 */

Definition at line 356 of file ppc_spr.h.

◆ SPR_HID2

#define SPR_HID2   0x3f3 /* ..8 Hardware Implementation Register 2 */

Definition at line 381 of file ppc_spr.h.

◆ SPR_HIOR

#define SPR_HIOR   0x137

Definition at line 113 of file ppc_spr.h.

◆ SPR_HRMOR

#define SPR_HRMOR   0x139

Definition at line 115 of file ppc_spr.h.

◆ SPR_HSPRG0

#define SPR_HSPRG0   0x130

Definition at line 110 of file ppc_spr.h.

◆ SPR_HSPRG1

#define SPR_HSPRG1   0x131

Definition at line 111 of file ppc_spr.h.

◆ SPR_HSRR0

#define SPR_HSRR0   0x13a

Definition at line 116 of file ppc_spr.h.

◆ SPR_HSRR1

#define SPR_HSRR1   0x13b

Definition at line 117 of file ppc_spr.h.

◆ SPR_IABR

#define SPR_IABR   0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */

Definition at line 380 of file ppc_spr.h.

◆ SPR_IAC1

#define SPR_IAC1   0x3f4 /* 4.. Instruction Address Compare 1 */

Definition at line 382 of file ppc_spr.h.

◆ SPR_IAC2

#define SPR_IAC2   0x3f5 /* 4.. Instruction Address Compare 2 */

Definition at line 383 of file ppc_spr.h.

◆ SPR_IAC3

#define SPR_IAC3   0x3b4 /* 4.. Instruction Address Compare 3 */

Definition at line 246 of file ppc_spr.h.

◆ SPR_IAC4

#define SPR_IAC4   0x3b5 /* 4.. Instruction Address Compare 4 */

Definition at line 247 of file ppc_spr.h.

◆ SPR_IBAT0L

#define SPR_IBAT0L   0x211 /* .6. Instruction BAT Reg 0 Lower */

Definition at line 120 of file ppc_spr.h.

◆ SPR_IBAT0U

#define SPR_IBAT0U   0x210 /* .68 Instruction BAT Reg 0 Upper */

Definition at line 119 of file ppc_spr.h.

◆ SPR_IBAT1L

#define SPR_IBAT1L   0x213 /* .6. Instruction BAT Reg 1 Lower */

Definition at line 122 of file ppc_spr.h.

◆ SPR_IBAT1U

#define SPR_IBAT1U   0x212 /* .6. Instruction BAT Reg 1 Upper */

Definition at line 121 of file ppc_spr.h.

◆ SPR_IBAT2L

#define SPR_IBAT2L   0x215 /* .6. Instruction BAT Reg 2 Lower */

Definition at line 124 of file ppc_spr.h.

◆ SPR_IBAT2U

#define SPR_IBAT2U   0x214 /* .6. Instruction BAT Reg 2 Upper */

Definition at line 123 of file ppc_spr.h.

◆ SPR_IBAT3L

#define SPR_IBAT3L   0x217 /* .6. Instruction BAT Reg 3 Lower */

Definition at line 126 of file ppc_spr.h.

◆ SPR_IBAT3U

#define SPR_IBAT3U   0x216 /* .6. Instruction BAT Reg 3 Upper */

Definition at line 125 of file ppc_spr.h.

◆ SPR_IBAT4L

#define SPR_IBAT4L   0x231 /* .6. Instruction BAT Reg 4 Lower */

Definition at line 148 of file ppc_spr.h.

◆ SPR_IBAT4U

#define SPR_IBAT4U   0x230 /* .6. Instruction BAT Reg 4 Upper */

Definition at line 146 of file ppc_spr.h.

◆ SPR_IBAT5L

#define SPR_IBAT5L   0x233 /* .6. Instruction BAT Reg 5 Lower */

Definition at line 151 of file ppc_spr.h.

◆ SPR_IBAT5U

#define SPR_IBAT5U   0x232 /* .6. Instruction BAT Reg 5 Upper */

Definition at line 150 of file ppc_spr.h.

◆ SPR_IBAT6L

#define SPR_IBAT6L   0x235 /* .6. Instruction BAT Reg 6 Lower */

Definition at line 153 of file ppc_spr.h.

◆ SPR_IBAT6U

#define SPR_IBAT6U   0x234 /* .6. Instruction BAT Reg 6 Upper */

Definition at line 152 of file ppc_spr.h.

◆ SPR_IBAT7L

#define SPR_IBAT7L   0x237 /* .6. Instruction BAT Reg 7 Lower */

Definition at line 155 of file ppc_spr.h.

◆ SPR_IBAT7U

#define SPR_IBAT7U   0x236 /* .6. Instruction BAT Reg 7 Upper */

Definition at line 154 of file ppc_spr.h.

◆ SPR_IC_ADR

#define SPR_IC_ADR   0x231 /* ..8 Instruction Cache Address */

Definition at line 147 of file ppc_spr.h.

◆ SPR_IC_CST

#define SPR_IC_CST   0x230 /* ..8 Instruction Cache CSR */

Definition at line 135 of file ppc_spr.h.

◆ SPR_IC_DAT

#define SPR_IC_DAT   0x232 /* ..8 Instruction Cache Data */

Definition at line 149 of file ppc_spr.h.

◆ SPR_ICCR

#define SPR_ICCR   0x3fb /* 4.. Instruction Cache Cachability Register */

Definition at line 480 of file ppc_spr.h.

◆ SPR_ICDBDR

#define SPR_ICDBDR   0x3d3 /* 4.. Instruction Cache Debug Data Register */

Definition at line 288 of file ppc_spr.h.

◆ SPR_ICMP

#define SPR_ICMP   0x3d5 /* .68 Instruction TLB Compare Register */

Definition at line 301 of file ppc_spr.h.

◆ SPR_IMISS

#define SPR_IMISS   0x3d4 /* .68 Instruction TLB Miss Address Register */

Definition at line 298 of file ppc_spr.h.

◆ SPR_L2CR

#define SPR_L2CR   0x3f9 /* .6. L2 Control Register */

Definition at line 400 of file ppc_spr.h.

◆ SPR_L2PM

#define SPR_L2PM   0x3f8 /* .6. L2 Private Memory Control Register */

Definition at line 399 of file ppc_spr.h.

◆ SPR_L3CR

#define SPR_L3CR   0x3fa /* .6. L3 Control Register */

Definition at line 437 of file ppc_spr.h.

◆ SPR_LR

#define SPR_LR   0x008 /* 468 Link Register */

Definition at line 40 of file ppc_spr.h.

◆ SPR_M_CASID

#define SPR_M_CASID   0x319 /* ..8 CASID */

Definition at line 218 of file ppc_spr.h.

◆ SPR_M_TWB

#define SPR_M_TWB   0x31c /* ..8 MMU tablewalk base */

Definition at line 222 of file ppc_spr.h.

◆ SPR_MD_AP

#define SPR_MD_AP   0x31a /* ..8 DMMU access protection */

Definition at line 220 of file ppc_spr.h.

◆ SPR_MD_CAM

#define SPR_MD_CAM   0x338 /* ..8 IMMU CAM entry read */

Definition at line 231 of file ppc_spr.h.

◆ SPR_MD_CTR

#define SPR_MD_CTR   0x318 /* ..8 DMMU control */

Definition at line 217 of file ppc_spr.h.

◆ SPR_MD_EPN

#define SPR_MD_EPN   0x31b /* ..8 DMMU effective number */

Definition at line 221 of file ppc_spr.h.

◆ SPR_MD_RAM0

#define SPR_MD_RAM0   0x339 /* ..8 IMMU RAM entry read reg 0 */

Definition at line 232 of file ppc_spr.h.

◆ SPR_MD_RAM1

#define SPR_MD_RAM1   0x33a /* ..8 IMMU RAM entry read reg 1 */

Definition at line 233 of file ppc_spr.h.

◆ SPR_MD_RPN

#define SPR_MD_RPN   0x31e /* ..8 DMMU real (phys) page number */

Definition at line 226 of file ppc_spr.h.

◆ SPR_MD_TW

#define SPR_MD_TW   0x31f /* ..8 MMU tablewalk scratch */

Definition at line 227 of file ppc_spr.h.

◆ SPR_MD_TWC

#define SPR_MD_TWC   0x31d /* ..8 DMMU tablewalk control */

Definition at line 225 of file ppc_spr.h.

◆ SPR_MI_AP

#define SPR_MI_AP   0x312 /* ..8 IMMU access protection */

Definition at line 194 of file ppc_spr.h.

◆ SPR_MI_CAM

#define SPR_MI_CAM   0x330 /* ..8 IMMU CAM entry read */

Definition at line 228 of file ppc_spr.h.

◆ SPR_MI_CTR

#define SPR_MI_CTR   0x310 /* ..8 IMMU control */

Definition at line 184 of file ppc_spr.h.

◆ SPR_MI_EPN

#define SPR_MI_EPN   0x313 /* ..8 IMMU effective number */

Definition at line 199 of file ppc_spr.h.

◆ SPR_MI_RAM0

#define SPR_MI_RAM0   0x331 /* ..8 IMMU RAM entry read reg 0 */

Definition at line 229 of file ppc_spr.h.

◆ SPR_MI_RAM1

#define SPR_MI_RAM1   0x332 /* ..8 IMMU RAM entry read reg 1 */

Definition at line 230 of file ppc_spr.h.

◆ SPR_MI_RPN

#define SPR_MI_RPN   0x316 /* ..8 IMMU real (phys) page number */

Definition at line 210 of file ppc_spr.h.

◆ SPR_MI_TWC

#define SPR_MI_TWC   0x315 /* ..8 IMMU tablewalk control */

Definition at line 203 of file ppc_spr.h.

◆ SPR_MMCR0

#define SPR_MMCR0   0x3b8 /* .6. Monitor Mode Control Register 0 */

Definition at line 250 of file ppc_spr.h.

◆ SPR_MMCR1

#define SPR_MMCR1   0x3bc /* .6. Monitor Mode Control Register 2 */

Definition at line 275 of file ppc_spr.h.

◆ SPR_MMCR2

#define SPR_MMCR2   0x3b0 /* .6. Monitor Mode Control Register 2 */

Definition at line 239 of file ppc_spr.h.

◆ SPR_MMCR2_THRESHMULT_2

#define SPR_MMCR2_THRESHMULT_2   0x00000000 /* Multiply MMCR0 threshold by 2 */

Definition at line 241 of file ppc_spr.h.

◆ SPR_MMCR2_THRESHMULT_32

#define SPR_MMCR2_THRESHMULT_32   0x80000000 /* Multiply MMCR0 threshold by 32 */

Definition at line 240 of file ppc_spr.h.

◆ SPR_MQ

#define SPR_MQ   0x000 /* .6. 601 MQ register */

Definition at line 36 of file ppc_spr.h.

◆ SPR_MSSCR0

#define SPR_MSSCR0   0x3f6 /* .6. Memory SubSystem Control Register */

Definition at line 386 of file ppc_spr.h.

◆ SPR_NRI

#define SPR_NRI   0x052 /* ..8 Exception Interrupt ??? */

Definition at line 60 of file ppc_spr.h.

◆ SPR_PID

#define SPR_PID   0x3b1 /* 4.. Process ID */

Definition at line 242 of file ppc_spr.h.

◆ SPR_PIR

#define SPR_PIR   0x3ff /* .6. Processor Identification Register */

Definition at line 493 of file ppc_spr.h.

◆ SPR_PIT

#define SPR_PIT   0x3db /* 4.. Programmable Interval Timer */

Definition at line 336 of file ppc_spr.h.

◆ SPR_PMC1

#define SPR_PMC1   0x3b9 /* .6. Performance Counter Register 1 */

Definition at line 270 of file ppc_spr.h.

◆ SPR_PMC2

#define SPR_PMC2   0x3ba /* .6. Performance Counter Register 2 */

Definition at line 272 of file ppc_spr.h.

◆ SPR_PMC3

#define SPR_PMC3   0x3bd /* .6. Performance Counter Register 3 */

Definition at line 283 of file ppc_spr.h.

◆ SPR_PMC4

#define SPR_PMC4   0x3be /* .6. Performance Counter Register 4 */

Definition at line 284 of file ppc_spr.h.

◆ SPR_PMC5

#define SPR_PMC5   0x3b1 /* .6. Performance Counter Register 5 */

Definition at line 243 of file ppc_spr.h.

◆ SPR_PMC6

#define SPR_PMC6   0x3b2 /* .6. Performance Counter Register 6 */

Definition at line 244 of file ppc_spr.h.

◆ SPR_PTEHI

#define SPR_PTEHI   0x3d5 /* .6. Instruction TLB Compare Register */

Definition at line 302 of file ppc_spr.h.

◆ SPR_PTELO

#define SPR_PTELO   0x3d6 /* .6. Required Physical Address Register */

Definition at line 305 of file ppc_spr.h.

◆ SPR_PVR

#define SPR_PVR   0x11f /* 468 Processor Version Register */

Definition at line 75 of file ppc_spr.h.

◆ SPR_RMOR

#define SPR_RMOR   0x138

Definition at line 114 of file ppc_spr.h.

◆ SPR_RPA

#define SPR_RPA   0x3d6 /* .68 Required Physical Address Register */

Definition at line 304 of file ppc_spr.h.

◆ SPR_RTCL_R

#define SPR_RTCL_R   0x005 /* .6. 601 RTC Lower - Read */

Definition at line 39 of file ppc_spr.h.

◆ SPR_RTCL_W

#define SPR_RTCL_W   0x015 /* .6. 601 RTC Lower - Write */

Definition at line 53 of file ppc_spr.h.

◆ SPR_RTCU_R

#define SPR_RTCU_R   0x004 /* .6. 601 RTC Upper - Read */

Definition at line 38 of file ppc_spr.h.

◆ SPR_RTCU_W

#define SPR_RTCU_W   0x014 /* .6. 601 RTC Upper - Write */

Definition at line 52 of file ppc_spr.h.

◆ SPR_SDR1

#define SPR_SDR1   0x019 /* .68 Page table base address register */

Definition at line 55 of file ppc_spr.h.

◆ SPR_SGR

#define SPR_SGR   0x3b9 /* 4.. Storage Guarded Register */

Definition at line 269 of file ppc_spr.h.

◆ SPR_SIA

#define SPR_SIA   0x3bb /* .6. Sampled Instruction Address */

Definition at line 274 of file ppc_spr.h.

◆ SPR_SLER

#define SPR_SLER   0x3bb /* 4.. Storage Little Endian Register */

Definition at line 273 of file ppc_spr.h.

◆ SPR_SPRG0

#define SPR_SPRG0   0x110 /* 468 SPR General 0 */

Definition at line 63 of file ppc_spr.h.

◆ SPR_SPRG1

#define SPR_SPRG1   0x111 /* 468 SPR General 1 */

Definition at line 64 of file ppc_spr.h.

◆ SPR_SPRG2

#define SPR_SPRG2   0x112 /* 468 SPR General 2 */

Definition at line 65 of file ppc_spr.h.

◆ SPR_SPRG3

#define SPR_SPRG3   0x113 /* 468 SPR General 3 */

Definition at line 66 of file ppc_spr.h.

◆ SPR_SPRG4

#define SPR_SPRG4   0x114 /* 4.. SPR General 4 */

Definition at line 67 of file ppc_spr.h.

◆ SPR_SPRG5

#define SPR_SPRG5   0x115 /* 4.. SPR General 5 */

Definition at line 68 of file ppc_spr.h.

◆ SPR_SPRG6

#define SPR_SPRG6   0x116 /* 4.. SPR General 6 */

Definition at line 69 of file ppc_spr.h.

◆ SPR_SPRG7

#define SPR_SPRG7   0x117 /* 4.. SPR General 7 */

Definition at line 70 of file ppc_spr.h.

◆ SPR_SRR0

#define SPR_SRR0   0x01a /* 468 Save/Restore Register 0 */

Definition at line 56 of file ppc_spr.h.

◆ SPR_SRR1

#define SPR_SRR1   0x01b /* 468 Save/Restore Register 1 */

Definition at line 57 of file ppc_spr.h.

◆ SPR_SRR2

#define SPR_SRR2   0x3de /* 4.. Save/Restore Register 2 */

Definition at line 337 of file ppc_spr.h.

◆ SPR_SRR3

#define SPR_SRR3   0x3df /* 4.. Save/Restore Register 3 */

Definition at line 338 of file ppc_spr.h.

◆ SPR_SU0R

#define SPR_SU0R   0x3bc /* 4.. Storage User-defined 0 Register */

Definition at line 281 of file ppc_spr.h.

◆ SPR_TBL

#define SPR_TBL   0x11c /* 468 Time Base Lower */

Definition at line 73 of file ppc_spr.h.

◆ SPR_TBU

#define SPR_TBU   0x11d /* 468 Time Base Upper */

Definition at line 74 of file ppc_spr.h.

◆ SPR_TCR

#define SPR_TCR   0x3da /* 4.. Timer Control Register */

Definition at line 316 of file ppc_spr.h.

◆ SPR_THRM1

#define SPR_THRM1   0x3fc /* .6. Thermal Management Register */

Definition at line 481 of file ppc_spr.h.

◆ SPR_THRM2

#define SPR_THRM2   0x3fd /* .6. Thermal Management Register */

Definition at line 482 of file ppc_spr.h.

◆ SPR_THRM3

#define SPR_THRM3   0x3fe /* .6. Thermal Management Register */

Definition at line 489 of file ppc_spr.h.

◆ SPR_THRM_ENABLE

#define SPR_THRM_ENABLE   0x00000001 /* TAU Enable */

Definition at line 491 of file ppc_spr.h.

◆ SPR_THRM_THRESHOLD

#define SPR_THRM_THRESHOLD (   x)    ((x) << 23) /* Thermal sensor threshold */

Definition at line 485 of file ppc_spr.h.

◆ SPR_THRM_TID

#define SPR_THRM_TID   0x00000004 /* Thermal interrupt direction */

Definition at line 486 of file ppc_spr.h.

◆ SPR_THRM_TIE

#define SPR_THRM_TIE   0x00000002 /* Thermal interrupt enable */

Definition at line 487 of file ppc_spr.h.

◆ SPR_THRM_TIMER

#define SPR_THRM_TIMER (   x)    ((x) << 1) /* Sampling interval timer */

Definition at line 490 of file ppc_spr.h.

◆ SPR_THRM_TIN

#define SPR_THRM_TIN   0x80000000 /* Thermal interrupt bit (RO) */

Definition at line 483 of file ppc_spr.h.

◆ SPR_THRM_TIV

#define SPR_THRM_TIV   0x40000000 /* Thermal interrupt valid (RO) */

Definition at line 484 of file ppc_spr.h.

◆ SPR_THRM_VALID

#define SPR_THRM_VALID   0x00000001 /* Valid bit */

Definition at line 488 of file ppc_spr.h.

◆ SPR_TLBMISS

#define SPR_TLBMISS   0x3d4 /* .6. TLB Miss Address Register */

Definition at line 299 of file ppc_spr.h.

◆ SPR_TSR

#define SPR_TSR   0x3d8 /* 4.. Timer Status Register */

Definition at line 306 of file ppc_spr.h.

◆ SPR_UMMCR0

#define SPR_UMMCR0   0x3a8 /* .6. User Monitor Mode Control Register 0 */

Definition at line 235 of file ppc_spr.h.

◆ SPR_UMMCR1

#define SPR_UMMCR1   0x3ac /* .6. User Monitor Mode Control Register 1 */

Definition at line 237 of file ppc_spr.h.

◆ SPR_UMMCR2

#define SPR_UMMCR2   0x3a0 /* .6. User Monitor Mode Control Register 2 */

Definition at line 234 of file ppc_spr.h.

◆ SPR_USIA

#define SPR_USIA   0x3ab /* .6. User Sampled Instruction Address */

Definition at line 236 of file ppc_spr.h.

◆ SPR_USPRG0

#define SPR_USPRG0   0x100 /* 4.. User SPR General 0 */

Definition at line 61 of file ppc_spr.h.

◆ SPR_VRSAVE

#define SPR_VRSAVE   0x100 /* .6. AltiVec VRSAVE */

Definition at line 62 of file ppc_spr.h.

◆ SPR_XER

#define SPR_XER   0x001 /* 468 Fixed Point Exception Register */

Definition at line 37 of file ppc_spr.h.

◆ SPR_ZPR

#define SPR_ZPR   0x3b0 /* 4.. Zone Protection Register */

Definition at line 238 of file ppc_spr.h.

◆ TBR_TBL

#define TBR_TBL   0x10c /* 468 Time Base Lower */

Definition at line 496 of file ppc_spr.h.

◆ TBR_TBU

#define TBR_TBU   0x10d /* 468 Time Base Upper */

Definition at line 497 of file ppc_spr.h.

◆ TCR_ARE

#define TCR_ARE   0x00400000 /* Auto Reload Enable */

Definition at line 335 of file ppc_spr.h.

◆ TCR_FIE

#define TCR_FIE   0x00800000 /* FIT Interrupt Enable */

Definition at line 334 of file ppc_spr.h.

◆ TCR_FP_2_13

#define TCR_FP_2_13   0x01000000 /* 2**13 clocks */

Definition at line 331 of file ppc_spr.h.

◆ TCR_FP_2_17

#define TCR_FP_2_17   0x02000000 /* 2**17 clocks */

Definition at line 332 of file ppc_spr.h.

◆ TCR_FP_2_21

#define TCR_FP_2_21   0x03000000 /* 2**21 clocks */

Definition at line 333 of file ppc_spr.h.

◆ TCR_FP_2_9

#define TCR_FP_2_9   0x00000000 /* 2**9 clocks */

Definition at line 330 of file ppc_spr.h.

◆ TCR_FP_MASK

#define TCR_FP_MASK   0x03000000 /* FIT Period */

Definition at line 329 of file ppc_spr.h.

◆ TCR_PIE

#define TCR_PIE   0x04000000 /* PIT Interrupt Enable */

Definition at line 328 of file ppc_spr.h.

◆ TCR_WIE

#define TCR_WIE   0x08000000 /* Watchdog Interrupt Enable */

Definition at line 327 of file ppc_spr.h.

◆ TCR_WP_2_17

#define TCR_WP_2_17   0x00000000 /* 2**17 clocks */

Definition at line 318 of file ppc_spr.h.

◆ TCR_WP_2_21

#define TCR_WP_2_21   0x40000000 /* 2**21 clocks */

Definition at line 319 of file ppc_spr.h.

◆ TCR_WP_2_25

#define TCR_WP_2_25   0x80000000 /* 2**25 clocks */

Definition at line 320 of file ppc_spr.h.

◆ TCR_WP_2_29

#define TCR_WP_2_29   0xc0000000 /* 2**29 clocks */

Definition at line 321 of file ppc_spr.h.

◆ TCR_WP_MASK

#define TCR_WP_MASK   0xc0000000 /* Watchdog Period mask */

Definition at line 317 of file ppc_spr.h.

◆ TCR_WRC_CHIP

#define TCR_WRC_CHIP   0x20000000 /* Chip reset */

Definition at line 325 of file ppc_spr.h.

◆ TCR_WRC_CORE

#define TCR_WRC_CORE   0x10000000 /* Core reset */

Definition at line 324 of file ppc_spr.h.

◆ TCR_WRC_MASK

#define TCR_WRC_MASK   0x30000000 /* Watchdog Reset Control mask */

Definition at line 322 of file ppc_spr.h.

◆ TCR_WRC_NONE

#define TCR_WRC_NONE   0x00000000 /* No watchdog reset */

Definition at line 323 of file ppc_spr.h.

◆ TCR_WRC_SYSTEM

#define TCR_WRC_SYSTEM   0x30000000 /* System reset */

Definition at line 326 of file ppc_spr.h.

◆ TSR_ENW

#define TSR_ENW   0x80000000 /* Enable Next Watchdog */

Definition at line 307 of file ppc_spr.h.

◆ TSR_FIS

#define TSR_FIS   0x04000000 /* FIT Interrupt Status */

Definition at line 315 of file ppc_spr.h.

◆ TSR_PIS

#define TSR_PIS   0x08000000 /* PIT Interrupt Status */

Definition at line 314 of file ppc_spr.h.

◆ TSR_WIS

#define TSR_WIS   0x40000000 /* Watchdog Interrupt Status */

Definition at line 308 of file ppc_spr.h.

◆ TSR_WRS_CHIP

#define TSR_WRS_CHIP   0x20000000 /* Chip reset was forced by the watchdog */

Definition at line 312 of file ppc_spr.h.

◆ TSR_WRS_CORE

#define TSR_WRS_CORE   0x10000000 /* Core reset was forced by the watchdog */

Definition at line 311 of file ppc_spr.h.

◆ TSR_WRS_MASK

#define TSR_WRS_MASK   0x30000000 /* Watchdog Reset Status */

Definition at line 309 of file ppc_spr.h.

◆ TSR_WRS_NONE

#define TSR_WRS_NONE   0x00000000 /* No watchdog reset has occurred */

Definition at line 310 of file ppc_spr.h.

◆ TSR_WRS_SYSTEM

#define TSR_WRS_SYSTEM   0x30000000 /* System reset was forced by the watchdog */

Definition at line 313 of file ppc_spr.h.


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