mb86960reg.h Source File
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6 #define MB8696X_NREGS 32
110 #define FE_D0_BUSERR 0x01
111 #define FE_D0_COLL16 0x02
112 #define FE_D0_COLLID 0x04
113 #define FE_D0_JABBER 0x08
114 #define FE_D0_CRLOST 0x10
115 #define FE_D0_PKTRCD 0x20
116 #define FE_D0_NETBSY 0x40
117 #define FE_D0_TXDONE 0x80
120 #define FE_D1_OVRFLO 0x01
121 #define FE_D1_CRCERR 0x02
122 #define FE_D1_ALGERR 0x04
123 #define FE_D1_SRTPKT 0x08
124 #define FE_D1_RMTRST 0x10
125 #define FE_D1_DMAEOP 0x20
126 #define FE_D1_BUSERR 0x40
127 #define FE_D1_PKTRDY 0x80
129 #define FE_D1_ERRBITS "\20\4SRTPKT\3ALGERR\2CRCERR\1OVRFLO"
132 #define FE_D2_BUSERR FE_D0_BUSERR
133 #define FE_D2_COLL16 FE_D0_COLL16
134 #define FE_D2_COLLID FE_D0_COLLID
135 #define FE_D2_JABBER FE_D0_JABBER
136 #define FE_D2_TXDONE FE_D0_TXDONE
138 #define FE_D2_RESERVED 0x70
141 #define FE_D3_OVRFLO FE_D1_OVRFLO
142 #define FE_D3_CRCERR FE_D1_CRCERR
143 #define FE_D3_ALGERR FE_D1_ALGERR
144 #define FE_D3_SRTPKT FE_D1_SRTPKT
145 #define FE_D3_RMTRST FE_D1_RMTRST
146 #define FE_D3_DMAEOP FE_D1_DMAEOP
147 #define FE_D3_BUSERR FE_D1_BUSERR
148 #define FE_D3_PKTRDY FE_D1_PKTRDY
151 #define FE_D4_DSC 0x01
152 #define FE_D4_LBC 0x02
153 #define FE_D4_CNTRL 0x04
154 #define FE_D4_TEST1 0x08
155 #define FE_D4_COL 0xF0
157 #define FE_D4_LBC_ENABLE 0x00
158 #define FE_D4_LBC_DISABLE 0x02
160 #define FE_D4_COL_SHIFT 4
163 #define FE_D5_AFM0 0x01
164 #define FE_D5_AFM1 0x02
165 #define FE_D5_RMTRST 0x04
166 #define FE_D5_SRTPKT 0x08
167 #define FE_D5_SRTADR 0x10
168 #define FE_D5_BADPKT 0x20
169 #define FE_D5_BUFEMP 0x40
170 #define FE_D5_TEST2 0x80
173 #define FE_D6_BUFSIZ 0x03
174 #define FE_D6_TXBSIZ 0x0C
175 #define FE_D6_BBW 0x10
176 #define FE_D6_SBW 0x20
177 #define FE_D6_SRAM 0x40
178 #define FE_D6_DLC 0x80
180 #define FE_D6_BUFSIZ_8KB 0x00
181 #define FE_D6_BUFSIZ_16KB 0x01
182 #define FE_D6_BUFSIZ_32KB 0x02
183 #define FE_D6_BUFSIZ_64KB 0x03
185 #define FE_D6_TXBSIZ_1x2KB 0x00
186 #define FE_D6_TXBSIZ_2x2KB 0x04
187 #define FE_D6_TXBSIZ_2x4KB 0x08
188 #define FE_D6_TXBSIZ_2x8KB 0x0C
190 #define FE_D6_BBW_WORD 0x00
191 #define FE_D6_BBW_BYTE 0x10
193 #define FE_D6_SBW_WORD 0x00
194 #define FE_D6_SBW_BYTE 0x20
196 #define FE_D6_SRAM_150ns 0x00
197 #define FE_D6_SRAM_100ns 0x40
199 #define FE_D6_DLC_ENABLE 0x00
200 #define FE_D6_DLC_DISABLE 0x80
203 #define FE_D7_BYTSWP 0x01
204 #define FE_D7_EOPPOL 0x02
205 #define FE_D7_RBS 0x0C
206 #define FE_D7_RDYPNS 0x10
207 #define FE_D7_POWER 0x20
208 #define FE_D7_ED 0xC0
209 #define FE_D7_IDENT 0xC0
211 #define FE_D7_BYTSWP_LH 0x00
212 #define FE_D7_BYTSWP_HL 0x01
214 #define FE_D7_RBS_DLCR 0x00
215 #define FE_D7_RBS_MAR 0x04
216 #define FE_D7_RBS_BMPR 0x08
218 #define FE_D7_POWER_DOWN 0x00
219 #define FE_D7_POWER_UP 0x20
221 #define FE_D7_ED_NORMAL 0x00
222 #define FE_D7_ED_MON 0x40
223 #define FE_D7_ED_BYPASS 0x80
224 #define FE_D7_ED_TEST 0xC0
226 #define FE_D7_IDENT_86960 0x00
227 #define FE_D7_IDENT_86964 0x40
228 #define FE_D7_IDENT_86967 0x80
229 #define FE_D7_IDENT_86965 0xC0
240 #define FE_B10_START 0x80
241 #define FE_B10_COUNT 0x7F
244 #define FE_B11_CTRL 0x01
245 #define FE_B11_MODE1 0x02
246 #define FE_B11_MODE2 0x04
248 #define FE_B11_CTRL_RESEND 0x00
249 #define FE_B11_CTRL_SKIP 0x01
252 #define FE_B12_TXDMA 0x01
253 #define FE_B12_RXDMA 0x02
256 #define FE_B13_BSTCTL 0x03
257 #define FE_B13_TPTYPE 0x04
258 #define FE_B13_PORT 0x18
259 #define FE_B13_LNKTST 0x20
260 #define FE_B13_SQTHLD 0x40
261 #define FE_B13_IOUNLK 0x80
263 #define FE_B13_BSTCTL_1 0x00
264 #define FE_B13_BSTCTL_4 0x01
265 #define FE_B13_BSTCTL_8 0x02
266 #define FE_B13_BSTCLT_12 0x03
268 #define FE_B13_TPTYPE_UTP 0x00
269 #define FE_B13_TPTYPE_STP 0x04
271 #define FE_B13_PORT_AUTO 0x00
272 #define FE_B13_PORT_TP 0x08
273 #define FE_B13_PORT_AUI 0x18
276 #define FE_B14_FILTER 0x01
277 #define FE_B14_SQE 0x02
278 #define FE_B14_SKIP 0x04
279 #define FE_B14_RJAB 0x20
280 #define FE_B14_LLD 0x40
281 #define FE_B14_RLD 0x80
284 #define FE_B15_SQE FE_B14_SQE
285 #define FE_B15_RCVPOL 0x08
286 #define FE_B15_RMTPRT 0x10
287 #define FE_B15_RAJB FE_B14_RJAB
288 #define FE_B15_LLD FE_B14_LLD
289 #define FE_B15_RLD FE_B14_RLD
292 #define FE_B16_DOUT 0x04
293 #define FE_B16_SELECT 0x20
294 #define FE_B16_CLOCK 0x40
295 #define FE_B16_DIN 0x80
298 #define FE_B17_DATA 0x80
303 #define FE_B19_IRQ 0xC0
304 #define FE_B19_IRQ_SHIFT 6
306 #define FE_B19_ROM 0x38
307 #define FE_B19_ROM_SHIFT 3
309 #define FE_B19_ADDR 0x07
310 #define FE_B19_ADDR_SHIFT 0
317 #define FE_EEPROM_SIZE 32
320 #define FE_EEPROM_CONF 0x00
323 #define FE_EEPROM_DELAY() DELAY(4)
328 #define FE_ATI_EEP_ADDR 0x08
329 #define FE_ATI_EEP_MEDIA 0x18
330 #define FE_ATI_EEP_MAGIC 0x19
331 #define FE_ATI_EEP_MODEL 0x1e
332 #define FE_ATI_MODEL_AT1700T 0x00
333 #define FE_ATI_MODEL_AT1700BT 0x01
334 #define FE_ATI_MODEL_AT1700FT 0x02
335 #define FE_ATI_MODEL_AT1700AT 0x03
336 #define FE_ATI_EEP_REVISION 0x1f
343 #define FE_FILTER_LEN 8
346 #define FE_QUEUEING_MAX 127
349 #define FE_TXLEN_SIZE 2
352 #define FE_RXSTAT_GOODPKT 0x20
353 #define FE_RXSTAT_RMT0900 0x10
354 #define FE_RXSTAT_SHORTPKT 0x08
355 #define FE_RXSTAT_ALIGNERR 0x04
356 #define FE_RXSTAT_CRCERR 0x02
363 #define FE_MBH_ENADDR 0x1A
364 #define FE_MBH0_MASK 0x0D
365 #define FE_MBH0_INTR_ENABLE 0x10
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